Infineon-AP56003 ADC Analog Aspects-AN-v01 00-EN

8/16/32-Bit
A Guide to the Analog Part of the A/D

Converter
AP56003
Application Note
V1.0, 2012-09
Microcontrollers
Edition 2012-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2012 Infineon Technologies AG
All Rights Reserved.
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A Guide to the Analog Part of the A/D Converter
AP56003
Device1
Revision History: V1.0 2012-09
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Application Note 3 V1.0, 2012-09

AP56003
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Transfer Characteristic and Error Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Ideal Transfer Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Differential Non-Linearity Error (DNLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Integral Non-Linearity Error (INLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Principle of Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Sample Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Charge-Redistribution Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Calibration Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Write-Back Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Calibration Mechanism (Error Correction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Calibration Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Reset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Normal Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Disturbance Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Analog Input Circuitry Calculation (AN0 ... ANy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Electrical Model of the A/D Converter Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Accuracy at Sample Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Charge Flow during Sample Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.1 Charge Balance between CAINSW and CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3.2 Charge of CAINSW and CEXT via RASRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4 RASRC Calculation with (0 pF < CEXT < (2r - 1) * CAINSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4.1 Charge-Redistribution Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4.2 Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4.3 Calculation Example with (0 pF < CEXT < (2r -1) * CAINSW) and r = 12 . . . . . . . . . . . . . . . . . . . . . . . 26
5.4.3.1 Resistance of the Analog Source RASRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.3.2 Cycle Time tCYCLEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5 RASRC Calculation with (CEXT > (2r -1) * CAINSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5.1 External Capacitance CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5.2 Cycle Time tCYCLEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.5.3 Cutoff Frequency fC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.5.4 Calculation Example with (CEXT > (2r - 1) * CAINSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.6 RASRC Calculation with (CEXT = 0pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.6.1 Resistance of the Analog Source RASRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.6.2 Calculation Example with (CEXT = 0pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6 Analog Input Circuitry Simulation (AN0 ... ANy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1 Analog Input Circuitry Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7 Reference Voltage Circuitry Calculation (VAREF and VAGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1 Electrical Model of the A/D Converter Reference Voltage Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2 Sources for the Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2.1 Supply Voltage of the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2.2 External Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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7.3 IAREF Calculation without an External Capacitance CAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.4 RREF Calculation with an External Capacitance CAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.4.1 Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.5 Ratiometric Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8 Overload and Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.1 Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.1.1 Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.2 Overload Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.2.1 Overload Current and Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.2.1.1 Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.2.2 Overload Current and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.2.3 Coupling Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9 PCB and Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.1 Component Placing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.3 Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.4 Signal Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.5 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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Introduction
1 Introduction
The majority of Infineon Microcontroller products include an integrated, on-chip A/D (Analog/Digital) converter for
analog signal measurement, with multiplexed input channels and a sample and hold circuit.
Depending on the device type, the integrated A/D converter allows resolutions of 8-bit, 10-bit or 12-bit. Because
the A/D converter uses the Successive Approximation (SAR) method, it is also known as the SAR-A/D converter
(Successive Approximation Register A/D converter). This A/D converter type uses binary weighted conversion
capacitors and one sample and hold unit per A/D converter.
Other types of A/D converter with non binary weighted conversion capacitors, such as FADC (Fast A/D converter)
or with multiple sample and hold units per A/D converter are not covered in this Application Note. The DS-A/D
converter (Delta Sigma A/D converter) is also not covered in this Application Note.
In principle, the A/D converter can be divided into two parts:
• Analog part
– including the converter with sample and hold circuit
• Digital part
– which contains registers and the digital control unit
This Application Note provides basic information and recommendations for the analog part of the A/D converter.
Please refer to the appropriate microcontroller User Manual for the description of the digital part.
For historical and evolutionary reasons, different implementations of the A/D converter are available. The
differences in the analog part mainly concern the values in the A/D converter characteristics specified in the related
Data Sheet.
The resolution (r) of the A/D converter refers to the number of quantization levels an analog input voltage can be
determined to. The number of smallest levels is given in bits and one of these is the Least Significant Bit (LSB).
Figure 1 shows an example of an A/D converter with 210 - 1 = 1023 output quantization levels.
An A/D converter with 10-bit resolution quantizises an analog input voltage of 5 V to a step size of:
5 V / 210 = 4,88 mV
The values represent the digital output range from 0 to 1023.
This theoretical accuracy of an A/D converter is degraded by inaccuracies of the A/D converter itself (total
unadjusted error). Additionally the accuracy of the complete A/D conversion system is degraded by the external
elements which are connected to the analog input ANx and to the reference voltage VAREF. It is the task of the
system designer to keep the inaccuracies caused by the external circuits as low as possible, and this Application
Note provides the necessary basic information to optimize the external circuits of the A/D converter.

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Transfer Characteristic and Error Definition
2 Transfer Characteristic and Error Definition

The following diagrams show the ideal transfer characteristic of an A/D converter and the definitions for the
different kinds of error specified in the related Data Sheet:
• Offset Error
• Gain Error
• Differential Non-Linearity Error (DNLE)
• Integral Non-Linearity Error (INLE)
• Total Unadjusted Error (TUE)
2.1 Ideal Transfer Characteristic

Figure 1 defines the ideal transfer characteristic for an A/D converter.
The Ideal Transfer Curve (1) transfers each input to an output.
Digital Output Ideal Transfer Curve

(1)
TUE related to ideal
Transfer Curve
3FF TUE related to ideal (3) (2)
ADC Transfer Curve Ideal ADC Transfer Curve
3FE (4)
5
10 Bit Resolution
3 TUE related to ideal

Transfer Curve
-|TUE| +|TUE|
2 TUE related to ideal

ADC Transfer Curve
0
0 0.5 1 2 3 4 5 1022 1023 1024
0.5 LSB Inherent Analog Input Voltage [LSB]

Quantization Error
Figure 1 Ideal Transfer Characteristic

The Ideal ADC Transfer Curve (2) includes a quantization error, since all analog input values are presumed to
exist, they must be quantized by partitioning the continuum into discrete digital values. All analog values within a

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given range (quantization step) are represented by the same digital value, which corresponds to the nominal mid-
range value. That is the reason for the quantization uncertainty of +/- 0.5 LSB, which is a natural error and inherent
to each A/D converter.
The analog input voltage range must be within VAGND up to VAREF.
The quantization step size is 1 LSB = VAREF / 2r.
According to the Ideal Transfer Curve (1) the first digital transition, from 0 to 1, is shifted to the analog value of 0.5
LSB to get a minimum quantization uncertainty. That is why the first step width of the Ideal ADC Transfer Curve
(2) is 0.5 LSB, and the last step width is 1.5 LSB with an digital output range from 0 to (2r - 1).
The compensated inherent quantization error in relation to the analog input voltage is shown in Figure 2.
Quantization Error [LSB]
0.5
Analog
Input
0
1 2 3 4 5 1022 1023 1024 Voltage
[LSB]
-0.5
-1.0
Figure 2 Quantization Error
The total unadjusted error includes all A/D converter related inaccuracies such as production process deviations
and internal noise.
The TUE consists of offset error, gain error, DNLE and INLE, but it is not simply the sum of individually measured
errors. Because some ADC errors such as offset and gain, can compensate each other, the TUE can be far less
than the absolute sum of all individual errors. Figure 1 shows the definition of the TUE in relation to the Ideal ADC
Transfer Curve (1).
The real result of the A/D converter is in the range of Ideal ADC Transfer Curve (2) +/- TUE. This area is shaded
in Figure 1 and is between both TUE related to ideal ADC Transfer Curves (3) and (4).
Note: Reference voltages are considered as the ideal. An incorrect reference voltage generates an additional
error.

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2.2 Offset Error

The offset error is the deviation from the Ideal ADC Transfer Curve at the lowest transition level on the Real ADC
Transfer Curve. It is the input voltage required to bring the digital output to zero and can be measured by
determining the first digital transition, from 0 to 1, of the A/D converter. The offset error affects all codes by the
same amount.
In the following figure all other kinds of error (gain, DNLE, INLE) are excluded.
Digital Output
Ideal Transfer Curve

3FF
3FE
Ideal ADC Transfer Curve
5
Real ADC Transfer Curve
10 Bit Resolution
including the Offset Error

4
0
0 1 2 3 4 5 1022 1023 1024
Offset Error Analog Input Voltage [LSB]
Figure 3 Offset Error

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2.3 Gain Error

The gain error is the difference between the slopes of the real ADC Transfer Curve and the Ideal ADC Transfer
Curve at the maximum digital out value.
In the following figure all other kinds of error (offset, DNLE, INLE) are excluded.
Digital Output
Gain Error
3FF
3FE
5
10 Bit Resolution
0
0 1 2 3 4 5 1022 1023 1024
Analog Input Voltage [LSB]
Figure 4 Gain Error

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2.4 Differential Non-Linearity Error (DNLE)

The DNLE describes variations in the analog value between adjacent pairs of digital numbers, over the full range
of the digital output.
If each transition step width is exactly 1 LSB, the DNLE is zero.
If the transitions are 1 LSB +/- 1 LSB, then there is the possibility of missing codes. If a missing code occurs then
one value of the digital output is missing; e.g. the digital output might jump from 0011 to 0101 and miss out 0100
(See the figure that follows).
If the DNLE is less than 1 LSB, then a missing code is automatically excluded. In the following figure all other kinds
of error (offset, gain, INLE) are excluded.
If the output code always increases with an increase of the analog input and always decreases with a decrease
of the analog input, then the A/D converter is monotonic. The A/D converter is called monotonic when the DNLE
is in the range of -1 LSB ≤ DNL ≤ 1 LSB.

Digital Output
3FF
ADC Transfer Curve
3FE
5 Ideal ADC Transfer Curve

10 Bit Resolution
Missing Code
4
0
0 0.5 1 2 3 4 5 1022 1023 1024
DNLE = 1 LSB
Figure 5 Differential Non-Linearity Error

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2.5 Integral Non-Linearity Error (INLE)

The INLE is the maximum difference between the Ideal ADC Transfer Curve and the adjusted Real ADC Transfer
Curve (without offset and gain error). In the following figure DNLE is also excluded.
Digital Output

3FF
3FE
5
10 Bit Resolution
0
0 0.5 1 2 3 4 5 1022 1023 1024
INLE = 1 LSB
Figure 6 Integral Non-Linearity Error

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Principle of Conversion
3 Principle of Conversion
The A/D converter is based on the principle of Successive Approximation. It uses a capacitor network in order to
compare the analog input voltage with a reference voltage, generated from VAREF and VAGND. This reference
voltage is adapted step by step through Successive Approximation.
The capacitor network is also used for the sample and hold function. The conversion is performed in several steps.
A total conversion consists of:
• Sample phase
• Charge-redistribution phase (conversion phase)
• Calibration phase (only A/D converter with enabled calibration)
• Write-back phase
The sequence of the different phases is shown in Figure 7. The total ADC conversion time is controlled via
software. The block diagram in Figure 8 is related to a calibrated A/D converter with 10-bit resolution and
represents the principle connections between the analog input ANx, conversion C-net, comparator, and the A/D
converter result register.
Start of End of
Conversion Conversion
MSB LSB
Sample Calibration
Phase Charge-Redistribution Phase
Phase
Write back
Phase
ADC Conversion Time
Figure 7 A/D Converter Timing
3.1 Sample Phase

During the sample phase, the conversion control unit connects the capacitors of the conversion C-net to one of
the analog input channels via a multiplexer. The capacitor network is therefore charged/discharged to the voltage
level of the connected analog input channel. The hold capacitor CHOLD at the comparator holds the analog input
voltage after the sample phase.
3.2 Charge-Redistribution Phase

At the end of the sample phase and with the start of the charge-redistribution phase, the conversion C-net is
disconnected from the analog input. Now the voltage level stored in the hold capacitor CHOLD is reconstructed by
connecting the C-net capacitors Cr-1 to C0 (r: A/D converter resolution) individually to VAREF or VAGND.
As the capacitor network (conversion C-net) is binary weighted (i.e. Cn = 2*Cn-1), the charge of the capacitors Cr-
1 to C0, corresponds directly to the voltage level of the connected analog input channel. The digital value is found
successively, starting from the most significant bit down to the least significant bit. The comparator is used to
decide whether the actual voltage of the capacitor Cn is below or above the voltage stored in the hold capacitance.
The charge-redistribution phase is finished after ‘r’ steps of successive approximation, with r: 8, 10 or 12.

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Principle of Conversion
3.3 Calibration Phase

Note that only an A/D converter with calibration features can perform a calibration phase.
The conversion accuracy depends on the precision of the conversion C-net and the offset voltage of the
comparator. In order to correct the errors that are introduced through process variations and offset voltage, an
additional C-net (the calibration C-net) is used together with calibration control logic. A detailed description of the
calibration phase is in Chapter 4 “Calibration Mechanism (Error Correction)” on Page 15.
3.4 Write-Back Phase

During the write-back phase, the result of the Successive Approximation is copied to the A/D converter result
register and the conversion C-net is pre-charged with approximately VAREF / 2.
Note: Because of parasitic capacitances caused by the pads and the analog multiplexer, the pre-charge voltage
at the pins can differ from VAREF / 2, but is typically less than VAREF / 2.
Comparator
ADDAT
CHOLD
Calibration C-Net RAM
C7’ C6’ C5’ C4’ C3’ C2’ C1’ C0’
Calibration
Control
Conversion C-Net
C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
Conversion
ANx
Control
VAREF
VAGND
Figure 8 Block Diagram: Analog Part of a 10-bit A/D Converter with Calibration and Conversion C-Nets

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Calibration Mechanism (Error Correction)
4 Calibration Mechanism (Error Correction)

The self-calibration mechanism is implemented in the A/D-converter in order to compensate for the offset error
and to balance differences in the capacitive network due to production variations, which can cause linearity
deviations of the A/D conversion.
Note: Because of different demands for accuracy, die size or conversion time restrictions, not all SAR-A/D
converters provide the calibration feature.
The self-calibration mechanism consists of the:
• Calibration capacitor-net
• Calibration RAM
• Calibration control unit
Note: For a block diagram, see Figure 8.
Self-calibration includes two different kinds of calibration:
• Offset Calibration
– The adjustment of the offset error
• Linearity Calibration
– The binary weight adjustment between the capacitors of the conversion capacitor-net
4.1 Calibration Principle

The additional correction capacitor-net (calibration C-net) is used to add/subtract a capacitive charge to the
comparator input of the A/D converter. A typical implementation of the correction C-net allows an adjustment in
the range of ± 4 LSB with a resolution of 1/32 LSB within ± 128 steps.
The same calibration C-net is used for both the offset and the linearity calibrations:
• During offset calibration the corrective charge is determined, in order to zero-adjust the comparator.
• During linearity calibration, for each of the binary weighted capacitors of the conversion C-net, a correction
value (with respect to the sum of the remaining capacitors) is determined.
The results of the calibration are stored in the calibration RAM. During normal conversion, the stored values are
used to correct the measurement by using the calibration control unit to calculate the appropriate combination of
the calibration capacitors.
4.2 Reset Calibration

After a reset, the calibration RAM is cleared and the A/D converter automatically starts an initial full calibration
sequence (power-up calibration). Both the offset and the linearity deviations are adjusted. The first quarter of this
calibration sequence typically performs a coarse adjustment which becomes more precise during the remaining
three quarters of the sequence. This scheme guarantees a very fast reduction of the offset and linearity error.
Notes
1. After reset, the positive and negative analog reference voltages (VAREF and VAGND) must be stable and within
the specified range, in order to perform a valid reset calibration.
2. The reset calibration can be interrupted by any conversion. If interrupted, the reset calibration is lengthened
by the conversion time. The calibration sequence is performed with the actual values of the control register. A
change of the Conversion Time Control also changes the duration of the calibration sequence.
During the reset calibration sequence, conversion results can exceed the specified maximum TUE.
3. When entering IDLE or Slow Down Mode the reset calibration will continue until it is finished but the Power
Down current increases. It is therefore recommended to wait until reset calibration is finished before entering
IDLE or Slow Down Mode.

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Calibration Mechanism (Error Correction)
4.3 Normal Calibration

With post-calibration enabled during A/D converter operation, a re-calibration is performed after each conversion
in order to adapt to changing operating conditions such as temperature. This re-calibration is performed in single
steps, where a typical calibration step is about ± 1/32 LSB.
4.4 Disturbance Filtering

Because of the way in which the calibration operation is implemented, disturbances can be filtered during the
calibration.
Noise on VAREF or VAGND can disturb calibration for example, but instead of performing a full correction of a
detected deviation (either offset or linearity) in one cycle, the calibration circuit performs a step-by-step reduction
of the deviation. Therefore if during one calibration cycle a deviation caused by a disturbance is detected, the last
correction value will only be incremented or decremented by one calibration step (typically 1/32 LSB).
As an example, if the disturbance would cause an offset deviation of 1 LSB, then 32 calibration steps would be
necessary to correct the error. If, however, a deviation occurs during one calibration cycle but does not appear
during the next calibration cycle, the previous change of the correction value will be cancelled. In other words, an
incorrect calibration caused by disturbances can only occur if the disturbance lasts for a long time. Disturbances
occurring during the reset calibration will be eliminated due to the long calibration sequence and post-calibration
after each conversion.

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Analog Input Circuitry Calculation (AN0 ... ANy)
5 Analog Input Circuitry Calculation (AN0 ... ANy)

Any application where an analog voltage has to be measured needs an accurate calculation of the external circuit
elements involved. This is fundamental to ensure sufficient charging of the A/D converter input capacitance CAINSW
to the same voltage as the analog source, during the sample time. Insufficient charging of CAINSW causes additional
inaccuracy (ErrorANx) to the TUE of the A/D converter.
This chapter explains how to calculate the external circuits for the analog inputs. The derivation of the necessary
formulas is followed by calculation examples.
Because of the different phases of a total conversion (sample and charge-redistribution time) the calculation
examples are shared into different electrical models which fit best to the values of the external circuits used.
The basis for the calculations is the voltage waveform of analog input ANx, which can be observed during a
conversion.
Note: A detailed solution of the calculation without a simplified electrical model leads to at least a 2nd order
differential equation. This is not covered by this document, but a more detailed description of the behavior
of the A/D converter circuitry is described in “Chapter 6 “Analog Input Circuitry Simulation (AN0 ... ANy)”
on Page 34”
5.1 Electrical Model of the A/D Converter Input

Figure 9 is a simplified block diagram of the A/D converter showing only the elements necessary for a calculation
of the external circuits.
Analog Source A/D Converter

AN0
RASRC RAIN Comparator

ANx CAINP
MUX
VAINx Sample
V0 CAINP
ANy CAINSW VAINSW
CEXT
CAINP
VAGND
Central Analog Ground

CAINP = CAINTOT - CAINSW
Figure 9 Block Diagram: A/D Converter Input and Analog Source

The A/D converter input capacitance CAINSW contains the capacitors of the conversion C-net and all parasitic
capacitors which are also switched with the sample switch.
RAIN is the internal series resistance of the A/D converter.
The sample switch represents an analog switch closed only during sample time.
The multiplexer connects the selected analog input ANx with the internal conversion C-net.

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The external capacitance CEXT can be a real external capacitor for noise reduction, or only the parasitic
capacitance caused by the signal line between analog source and A/D converter input.
The analog voltage source is represented by an ideal voltage source V0 and a series resistance RASRC.
The specified values of RAIN, CAINSW and CAINTOT are dependent on technology and the type of A/D converter
implementation. The order of magnitude for the values is:
• CAINSW ~ 20 pF
• CAINTOT ~ 30 pF
• RAIN ~ 1000 Ω
Note: Please refer to the Data Sheet chapter “Electrical Parameter of the A/D converter” for the exact values of the
microcontroller under consideration.
5.2 Accuracy at Sample Time

As described in “Principle of Conversion” on Page 13", a total conversion is divided into two phases:
• Sample phase
• Charge-redistribution phase
The total accuracy of the A/D converter result depends on three elements:
• Specified TUE and the accuracy of the A/D converter itself
• Accuracy of VAREF and VAGND at the charge-redistribution phase
• Voltage level difference between analog source V0 and VAINSW (ErrorANx) at the end of the sample phase
A detailed consideration of the voltage level at CAINSW (or at ANx, respectively) is the condition necessary to
determine the correct values for RASRC, CEXT, sample time, and cycle time of a system.
The worst case voltage deviation (V0 - VAINSW) for the analog input signal is the maximum voltage difference
between the pre-charge voltage of CAINSW (approximately VAREF / 2) and V0 at the beginning of the sample phase.
This case is given for V0 = VAREF or V0 = VAGND.
The following figure shows the absolute voltage difference between V0 and CAINSW (|V0 - VAREF / 2|) at the beginning
of the sample phase.
The formulas in this document are all related to the absolute maximum possible V0 = VAREF. The result can also
be transformed to V0 = VAGND.
Voltages used in the calculations are all referred to VAGND.
|V0-VAINSW |
VAREF/2
V0
VAGND VAREF/2 VAREF
Figure 10 Voltage Difference between V0 and VAINSW at the start of the Sample Time

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Note: The assumed error (ErrorANx) used in this chapter (Analog Input Circuitry Calculation (AN0 ... ANy)) for
the calculation examples references the allowed maximum input voltage at ANx (VAINSWx = VAREF). For input
voltages at ANx smaller than VAREF the additional inaccuracy at VAINx is proportionally less than the value of
ErrorANx used in the example calculations.
The real additional inaccuracy at VAINx is:
ErrorANx_real = (VAINx / VAREF) * ErrorANx
with the condition:
VAGND ≤ VAINx ≤ VAREF
5.3 Charge Flow during Sample Time

The input impedance of the A/D converter is mainly capacitive (CAINSW) with a resistive part RAIN.
However this capacitance applies only to the selected analog input pin ANx during the sample time. For the
remaining time the inputs are extremely high impedance (typical leakage currents are in the range of some 10 nA
for example).
Note: Please refer to ‘Input leakage current of the ADC’ in the appropriate data sheet for the microcontroller under
consideration for more detailed information.
Using a simplified model, two different sequential processes are running during the sample phase.
• CAINSW is charged from CEXT and the voltages at CAINSW and CEXT are assigned the same value
• The common voltage at CAINSW and CEXT is adjusted to V0 via the resistance of the analog source RASRC
Depending on the phases of the A/D converter, different time constants (‘t’) have to be considered:
• t1 : Time constant at the beginning of the sample time
– Contains CAINSW, CEXT and RAIN
• t2 : Time constant during sample time
– Contains CAINSW, CEXT and RASRC
• t3 : Time constant during and after the charge-redistribution phase
– Contains CEXT and RASRC

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5.3.1 Charge Balance between CAINSW and CEXT

The electrical model for t1 is shown in Figure 11.
RAIN
Sample
VAINx
CEXT VAINSW ~ VAREF/2 CAINSW
CEXT includes CAINP
Figure 11 Electrical Model of the A/D Converter during t1

The voltage at CAINSW before the ‘Sample’ switch is closed, is approximately VAREF/2 because of pre-charging
CAINSW at the end of the conversion.
The voltage VAINx at CEXT is nearly V0 depending on the cycle time of the conversion.
When the ‘Sample’ switch is closed, then a charge balance is made between CAINSW and CEXT, with the time
constant t1 (See Figure 11).
Note: Figure 13 shows the corresponding waveform at ANx.
(1)
C AINSW ⋅ C EXT
t 1 = R AIN ⋅ ---------------------------------------
C AINSW + C EXT
Depending on the microcontroller, the values for CAINSW are typically in the range of:
• CAINSW : 5 pF up to 20 pF
The values for RAIN are typically in the range of:

• RAIN : 500 Ω up to 2000 Ω
Typical combinations of an A/D converter are:

• CAINSW = 5 pF and RAIN = 2000 Ω
• CAINSW = 20 pF and RAIN = 1500 Ω
These combinations result in maximum values for t1 of 10 ns and 30 ns, because RAIN and CAINSW are constant
values of the A/D converter.
For the calculation of the sample time, the duration of time constant t1 is in many cases negligible.
• After 7.6*t the voltage error is less than 0.5 LSB10
• After 9*t the voltage error is less than 0.5 LSB12

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The following table gives typical values of 7.6*t1 and 9*t1.
Table 1 Typical Values for 7.6*t1 and 9*t1

CEXT 1 pF 10 pF 100 pF 1 nF 10 nF 100 nF 1 µF
7.6*t1 @ (RAIN=2kW, CAINSW= 5 pF) 1.7 ns 6.7 ns 9.5 ns 10 ns 10 ns 10 ns 10ns
9*t1 @ (RAIN=2kW, CAINSW= 5 pF) 15 ns 60 ns 86ns 90 ns 90 ns 90 ns 90ns
7.6*t1 @ (RAIN=1.5kW, CAINSW=20 pF) 1.4 ns 10 ns 25ns 29 ns 30 ns 30 ns 30ns
9*t1 @ (RAIN=1.5kW, CAINSW=20 pF) 13 ns 90 ns 225ns 265 ns 269 ns 270 ns 270ns
The charge balance between CAINSW and CEXT causes a voltage jump VΔ at the analog input ANx.
Depending on the voltage on ANx when the sample phase starts, the voltage can be increased or decreased.
The example in Figure 13 uses the worst case V0 = VAREF.
At the end of 7.6*t1 the voltage at ANx is reduced (or increased) by the value V∆ with an accuracy of 0.5 LSB10
and after 9*t1 with an accuracy of 0.5 LSB12.
Using this simplified model the charge balance between CEXT and CAINSW results in the formula for V∆:
(2)
C AINSW ⋅ ( V 0 – V CAINSW )
V Δ = -----------------------------------------------------------------
C AINSW + C EXT
Table 2 Typical Values for the Voltage Jump V∆ with Pre-charge disregarding RASRC:
V0 - VCAINSW = 2.5 V and V0 = VAREF
CEXT 1 pF 10 pF 100 pF 1 nF 10 nF 100 nF 1 µF
V∆ 1) 2.4 V 1.7 V 400 mV 50 mV 5 mV 0.5 mV 0.05 mV
2)
V∆ 2.1 V 0.8 V 120 mV 12 mV 1.2 mV 0.1 mV 0.01 mV
1)
Voltage Jump V∆@ CAINSW = 20 pF and RAIN = 1500 Ω
2)
Voltage Jump V∆ @ CAINSW = 5 pF and RAIN = 2000 Ω

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5.3.2 Charge of CAINSW and CEXT via RASRC

The following figure shows the simplified electrical model during sample time with t2.
In this model RAIN is neglected because in typical systems RASRC >> RAIN.
The voltage at CAINSW and CEXT is defined by V0 and V∆ at the beginning of the second phase (’start-voltage’ = V0
- V∆).
RASRC RAIN
V0
CEXT CAINSW

After V∆ has reached the absolute maximum value, CEXT and CAINSW are charged via RASRC from V0 with the time
constant t2.
(3)
t 2 = R ASRC ⋅ ( C AINSW + C EXT )
5.4 RASRC Calculation with (0 pF < CEXT < (2r - 1) * CAINSW)

To ensure reliable results, the input capacitance CAINSW must be completely charged to the desired value during
sample time. This is then digitized by the A/D converter.
Under worst-case conditions, the input capacitance must be charged or discharged by half the input voltage when
V0 = VAREF or when V0 = VAGND.
The input capacitance CAINSW of the A/D converter, the external capacitance CEXT and the resistance of the analog
source RASRC together form an RC lowpass filter, which has the charging function VS(t). In many systems sample
time tS >> t1, therefore t1 is neglected in the formula for VS(t). The waveform is shown in Figure 13.
(4)
–t
----
t2
V s ( t ) = V AREF – V Δ ⋅ e

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The voltage on ANx at the end of the sample time can also be described with the formula VS(tS).
The ErrorANx describes the maximum deviation allowed between the voltage on ANx and V0 when the sample time
is finished.
An assumed ErrorANx of 0.5 LSB is equivalent to the values shown in the following table:
Table 3 Absolute Values of 0.5 LSB for different A/D Converter Resolutions
Resolution 8-bit 10-bit 12-bit
0.5 LSB @ VAREF = 5 V 9.76 mV 2.44 mV 0.61 mV
0.5 LSB @ VAREF = 3.3 V 6.45 mV 1.61 mV 0.40 mV
(5)
V S ( t ) = V AREF – Error ANx
Now it is possible to calculate the maximum value of the analog source resistance RASRC.
The formula for RASRC assumes that RAIN = 0 Ω.
(6)
tS
R ASRC = -----------------------------------------------------------------------
VΔ
( C AIN + C EXT ) ⋅ ln ---------------------- -
Error ANx
The formula is only valid for: V∆ / ErrorANx > 1

An assumed maximum ErrorANx = LSB / 2 leads to CEXT < (2r - 1) * CAINSW
Depending on the A/D converter resolution the relationships between CEXT and CAINSW are:
8-bit resolution:0 pF < CEXT < 255 * CAINSW
Note: This is only an approximate estimation.The accuracy of the model decreases as the value for CEXT
increases, but the model explains the principle behavior of the circuit.

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VAIN
V0 = VAREF t2 t3
ErrorANx
VS(tS)
VΔ
Sampled
Voltage
VS(t)
V0 - VΔ
t1 t2
t
tS tCR
tC
tCYCLEn
tS : Sample time tC : Conversion time

tCYCLEn : Cycle time of channel n t1, t2, t3 : Time constants
V0 : Voltage of the analog source
tCR : Charge-redistribution time (conversion phase)
VΔ : Voltage jump at the start of the sample phase
ErrorANx : Voltage deviation between sampled voltage and
voltage of the analog source
Figure 13 Voltage Waveform at ANx

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5.4.1 Charge-Redistribution Time

During the charge-redistribution time, the ‘Sample’ switch is open and the external capacitance CEXT is charged
via the resistor of the analog source RASRC.
RASRC
V0
CEXT

The time constant during and after charge-redistribution time is t3.
(7)
t 3 = R ASRC ⋅ C EXT
While the external capacitance CEXT is charged via RASRC, the A/D converter performs the Successive
Approximation (charge-redistribution). This is the transformation of the analog voltage into a digital value. The
reference for the transformation is the reference voltage at pin VAREF referred to VAGND. It is very important for an
exact conversion result to hold the reference voltage and the reference ground on a constant level during the
charge-redistribution. See also “Reference Voltage Circuitry Calculation (VAREF and VAGND)” on Page 39.

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5.4.2 Cycle Time

The cycle time tCYCLEn is the duration from the start of a conversion to the next conversion start of the same analog
channel. The following figure shows the relationship between the conversion time of an analog channel and the
cycle time.
chx chy chz chx
tC x tC y tC z tC x
tCYCLEn
tC n : Conversion time of analog channel n

tCYCLEn : Cycle time of analog channel n
chn : analog channel n
Figure 15 Cycle Time

For continuous conversion mode of a channel, the conversion time tC can be equal to the cycle time tCYCLEn.
The cycle time of consecutive conversions is important for the calculation of the voltage on CEXT at the start of the
next conversion. The voltage difference between the analog source V0 and the analog input ANx at the start of a
conversion should be 0 V or negligible.
The recommendation is:
(8)
t CYCLE ≥ 9 ⋅ t 3 + t S
Note: After 9 * t3 the remaining deviation from V0 is 0.012% (~0.5 LSB12) of the assumed ErrorANx for VS(tS).
Using 7.6 * t3 the remaining deviation from V0 is 0.049% (~0.5 LSB10) of the assumed ErrorANx for VS(tS).
5.4.3 Calculation Example with (0 pF < CEXT < (2r -1) * CAINSW) and r = 12
The assumed values used in the example are:
CAINSW = 20 pF tS = 1.5 µs VAREF = V0 = 5 V

RAIN = 1500 Ω tC = 2.3 µs r = 12 (12-bit resolution)
CEXT = 200 pF
ErrorANx = 0.5 LSB12 = VAREF / 4096 ErrorANx = 0.61 mV
The calculation results in the values for RASRC and tCYCLEn.

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5.4.3.1 Resistance of the Analog Source RASRC

The voltage jump V∆ during the sample phase is calculated as:
V∆ = (CAINSW * (VAREF - VAREF / 2)) / (CAINSW + CEXT)

V∆ = (20 pF * (5 V - 2.5 V)) / (20 pF + 200 pF)
V∆ = 227 mV
The maximum allowed resistance of analog source RASRC is then calculated:
RASRC = tS / ((CAINSW + CEXT) * ln(V∆ / ErrorANx))

RASRC = 1.5 µs/ ((20 pF + 200 pF) * ln(227 mV / 0.61 mV))
RASRC = 1152 Ω
The table shows the different results of RASRC with the assumed values used in the example.
Table 4 Maximum Values for RASRC and different CEXT

CEXT[pF] 1 20 40 60 80 100 150 200 250 500 1000 10000
RASRC [kW] 8.6 4.9 3.5 2.7 2.2 1.9 1.4 1.2 1.0 0.6 0.35 0.07
Note: The capacitive load at the analog inputs ANx should be as small as possible because it reduces the allowed
resistance of the analog source RASRC (as shown in Table 4). The only exception is the use of a very high
value for the external capacitance CEXT, which supplies the A/D converter with the necessary charge during
the sample phase.

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5.4.3.2 Cycle Time tCYCLEn

The recommended minimum value of the cycle time is:
tCYCLEn = 9 * RASRC * CEXT + tS

tCYCLEn = 9 * 1152 Ω * 200 pF + 1.5 µs
tCYCLEn = 3.6µs
The calculated cycle time tCYCLEn is longer than the conversion time tC and, in that case, continuous conversion of
this analog channel is only possible by inserting a waiting period to charge the external capacitance CEXT.
5.5 RASRC Calculation with (CEXT > (2r -1) * CAINSW)

This is the typical method of connecting a signal to the analog input. The selected external capacitance has to be
high enough that the total charge, which is necessary to load the internal C-net (CAINSW) of the A/D converter, is
provided by the external capacitor CEXT.
The considerations outlined in the next subsection (“External Capacitance CEXT” on Page 28) use a value for
the external capacitance CEXT with respect to the assumed maximum ErrorANx caused by discharging CEXT during
sample time. The cycle time tCYCLEn has to be long enough to reload the external capacitor CEXT before starting the
next sample time.
5.5.1 External Capacitance CEXT

The calculation of the external capacitance CEXT is based on the assumption that VAREF - V∆ is the sampled
voltage and V∆ is the maximum allowed ErrorANx (See Figure 16 “Voltage VAINx with CEXT > 2r * CAINSW and
periodical Conversions” on Page 30). After the charge balance which causes the voltage drop V∆, the voltage
variation at the capacitors during the sample phase is extremely small. This is because of the time constant t3 (t3
= RASRC* CEXT) which is almost in the ms range, and the voltage drop which is in the mV range.
The example to determine the value of the external capacitance CEXT is calculated with the assumption of a
maximum allowed error, ErrorANx = LSBr / 2.
Error = LSBr / 2
Error = VAREF / (2r * 2)
Error > V∆ = (CAINSW * (VAREF - VAREF / 2)) / (CAINSW + CEXT)
Condition for the external capacitance:

(9)
r
C EXT > ( 2 – 1 ) ⋅ C AINSW
Depending on the A/D converter resolution the relationship between CEXT and CAINSW is:
8-bit resolution: CEXT > 255 * CAINSW

The condition CEXT > (2 r - 1) * CAINSW allows the choice of a very short sample time tS because of the small time
constant t1. Table 1 can be used to help with the appropriate selection of a sample time. Note that the value of
RASRC has a direct influence on the conversion cycle time tCYCLEn.

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5.5.2 Cycle Time tCYCLEn

The calculation of the cycle time takes into account that the external capacitor is not totally charged to the voltage
of the analog source V0 (worst cases are V0 = VAREF or V0 = VAGND), but a small voltage rest VR is missing (See
Figure 16 “Voltage VAINx with CEXT > 2r * CAINSW and periodical Conversions” on Page 30).
With the condition CAINSW << CEXT the formula for V∆ can be simplified:
V∆ = (CAINSW * (VAREF - VAREF/2)) / (CAINSW + CEXT)

V∆ ~ CAINSW * VAREF / (2 * CEXT)
The condition V∆ + VR ≤ ErrorANx with VR = VAREF - VC (tCYCLEn)
is based on Figure 16.
The charge curve VC(t) of the capacitor CEXT via the resistance of the analog source RASRC is:
(10)
–----t
t3
V C ( t ) = V AREF – Error ANx ⋅ e
With an assumed maximum allowed error of LSBr / 2 (ErrorANx = (VAREF / 2 r) / 2) and with t3 = RASRC * CEXT the
formulas result in the relation:
(11)
C EXT
t CYCLE ≥ R ASRC ⋅ C EXT ⋅ ln ----------------------------------------------------
-
r
C EXT – ( 2 ⋅ C AINSW )
This formula is only valid for CEXT > 2r *

CAINSW

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VAINx
V0 = VAREF tCYCLEn tCYCLEn

VR
ErrorANx
VC(tCYCLEn) VΔ
VC(t)
Sampled
Voltage
tCYCLEn : Cycle time of channel n V0 : Voltage of the analog source

VC(t) : Charge curve for CEXT VR : Voltage rest at the end of tCYCLEn
VΔ : Voltage drop at the start of the sample phase
ErrorANx : Voltage deviation between sampled voltage and
voltage of the analog source
Figure 16 Voltage VAINx with CEXT > 2r * CAINSW and periodical Conversions
5.5.3 Cutoff Frequency fC

The resistance of the analog source RASRC and the external capacitance CEXT act as a low-pass filter with the cutoff
frequency fC. A check is necessary to determine whether the cutoff frequency fits to the frequency of the analog
source.
When the relation between the A/D converter cycle frequency (fCYCLE = 1 / tCYCLEn) and the cutoff frequency is
fCYCLE / fC ~ 0.05, then the analog signal is damped with ~1 o/oo (~1 LSB10).
(12)
1
f C = --------------------------------------------
2 ⋅ π ⋅ R ASRC ⋅ C EXT
Note: If the external circuit reaches the cutoff frequency then the voltage of the analog source V0 is damped with the factor
-3 dB (VAIN ~ 0.7 * V0 @ cutoff frequency fC ).

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5.5.4 Calculation Example with (CEXT > (2r - 1) * CAINSW)

The assumed values used in the example are:

RASRC = 20 kΩ CEXT > 4096 * CAINSW = 82 nF CEXT = 100 nF
ErrorANx = 0.5 LSB12 = VAREF / 4096 / 2 ErrorANx = 0.61 mV
The calculations result in the values of cycle time tCYCLEn and cutoff frequency fC.
The values of the external capacitance CEXT and resistance of the analog source RASRC are fixed in relation to the
cycle time tCYCLEn:
tCYCLEn ≥ RASRC * CEXT * ln(CEXT / (CEXT - 2r * CAINSW))

tCYCLEn ≥ 20 kΩ * 100 nF * ln(100 nF / (100 nF - 212 * 20 pF))
tCYCLEn ≥ 3.4 ms
The cutoff frequency is calculated from:
fC = 1 / (2 * π * RASRC * CEXT)
fC = 1 / (2 * π * 20 kΩ * 100 nF)
fC = 80 Hz
Table 5 shows calculation results of the cycle time in [ms] for different values of RASRC with the assumed values
of the example (ErrorANx = 0.5 LSB12).
Table 5 Cycle Time tCYCLEn for different Values of RASRC with CEXT = 100nF
RASRC [kΩ] 1 5 10 15 20 25 30 40 50 100
tCYCLEn [ms] 0.2 0.9 1.7 2.6 3.4 4.3 5.1 6.8 8.6 17.1
Table 6 shows calculation results of the cutoff frequency in [Hz] for different values of RASRC with the assumed
values of the example (ErrorANx = 0.5 LSB12).
Table 6 Cutoff Frequency fC for different Values of RASRC with CEXT = 100nF
RASRC [kΩ] 1 5 10 15 20 25 30 40 50 100
fC [Hz] 1592 318 159 106 80 64 53 40 32 16

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5.6 RASRC Calculation with (CEXT = 0pF)

In this example, which in real systems is hard to realize and which is very sensitive to noise, the external
capacitance is neglected. The electrical model is shown in Figure 17. It can be used for an approximate estimation
of the external components if the value of CEXT is nearly zero pF. The internal C-net capacitance of the A/D
converter is directly charged via RASRC and RAIN.
RASRC RAIN
V0 CAINSW
Figure 17 Electrical Model of the A/D Converter during t2 with CEXT = 0 pF
5.6.1 Resistance of the Analog Source RASRC

When the external capacitance is CEXT = 0 pF then the time constant t1 = 0 s and the maximum voltage drop V∆ at
the beginning of the sample time is approximately VAREF / 2, equal to the precharge value of the internal C-net.
V∆ = (CAINSW * (VAREF - VAREF / 2)) / CAINSW

V∆ = VAREF / 2
The resistance of the analog source RASRC, is calculated with the formula for systems with a small external
capacitance but without CEXT and with RAIN.
(13)
tS
R ASRC = ------------------------------------------------------ – R AIN
VΔ
C AINSW ⋅ ln ---------------------- -
Error ANx
The calculation of the cycle time is not necessary because during sample time the internal C-net is connected to
the analog source. In the other phases of the cycle time the internal C-net is disconnected from the analog source.
Therefore no external capacitance has to be charged via RASRC until the start of the next sample time.

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5.6.2 Calculation Example with (CEXT = 0pF)

This example gives an approximate estimation for the allowed maximum of RASRC if CEXT is nearly zero pF.
The assumed values in the example are:

CEXT = 0 pF precharge voltage: V∆ = VAREF / 2
ErrorANx = 0.5 LSB12 = VAREF / 4096 ErrorANx = 0.61 mV
The calculation results in the value for RASRC with V∆ = VAREF / 2.
RASRC = tS / (CAINSW * ln(V∆ / ErrorANx)) - RAIN

RASRC = 1.5 µs / (20 pF * ln(2.5 V / 0.61 mV)) - 1500 Ω
RASRC = 7516 Ω
The table shows the maximum values for RASRC and different sample times with the assumed values of the
example:
Table 7 Maximum Values for RASRC and sample Times tS @ CEXT = 0 pF

tS [µs] 0.5 1 1.5 2 3 4 5 6 7 8 9 10
RASRC [kΩ] 1.5 4.5 7.5 10.5 16.5 22.5 28.6 34.6 40.6 46.6 52.6 58.6
Note: The leakage current specified in the Data Sheet for the given microcontroller can influence the accuracy of
the analog input voltage, when the value of RASRC exceeds a certain limit. This limit depends on the allowed
inaccuracy (VAINx), which is determined by the demands of the system. See also ““Overload and Leakage
Current” on Page 46”.

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Analog Input Circuitry Simulation (AN0 ... ANy)
6 Analog Input Circuitry Simulation (AN0 ... ANy)

The simplified electrical model used for the calculation of the analog input circuitry described in this document,
does contain some inaccuracies, but it can still be used for the start values of an A/D converter circuitry simulation.
A simulation based on the A/D converter block diagram using the specified values from the Data Sheet of the given
microcontroller, combined with the external circuitry used, shows the realistic dynamic behavior of the different
components.
The simulation examples given here are created with ngspice. Ngspice is an open source SPICE simulator which
can be used as a local install or online.
An assessment of the A/D converter input circuitry and software settings (sample and conversion time) can be
made by analyzing the voltage difference between the analog source voltage V0 and the internal C-net voltage
VAINSW of the A/D converter. The lower this difference at the end of the sample time tS, the better the A/D converter
input circuitry selection and software settings. This is because at the end of the sample time the voltage at CAINSW
is the voltage which is converted to the digital output via Successive Approximation (charge-redistribution phase).
6.1 Analog Input Circuitry Simulation Model

The simulation model given here consists of a typical external circuit with voltage source V0 and the low pass filter
RASRC and CEXT.
The external capacitance is selected with CEXT > (2 r-1) * CAINSW.
Sample time behavior is realized with a sample switch.
The pre-charge voltage behavior is realized with a pre-charge voltage and a pre-charge switch.
The influence of the leakage current can be verified by adapting IOZ to the Data Sheet values of the appropriate
microcontroller.
The model circuitry is shown in Figure 18 “Simplified Model of the A/D converter Input Circuitry” on Page 35.
The assumed values for the example are:
CAINSW_MAX = 20 pF maximum switched capacitance

RAIN_MAX = 1500 Ω distributed to Rin = 500 Ω and Ron = 1000 Ω (sample switch)
RON = 1000 Ω sample switch on resistance
tS = 600 ns sample time
tC = 1.4µs conversion time
tCYCLEn = 3400 µs cycle time, time until start of the next conversion of the same channel
VPRECHARGE = 2.5 V precharge voltage at the end of the conversion time
CEXT = 100 nF external analog input capacitance
RASRC = 20000 Ω resistance of the analog source
V0 =5V is one worst case (or V0 = 0V) for recharging CAINSW after pre-charging
IOZ = +/-30 nA typical leakage source at room temperature
V_LSB10 = 4.995 V limit voltage V0 - 1LSB10 for plot
V_LSB12 = 4.9988 V limit voltage V0 - 1LSB12 for plot

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External Circuitry A/D Converter Input Circuitry
Pulse Pulse
Sample Precharge
RASRC RAIN
V0 VAINx VAINS VAINSW VPRECHARGE
20k 1.5k
DC CEXT CAINP IOZ CAINSW DC

5.0 V 100nF 10p 10p 2.5 V
Figure 18 Simplified Model of the A/D converter Input Circuitry
Analog Input Circuitry Simulation Netlist for ngspice

* ngspice file: ADC_model.asc
* ADC Input Circuitry
Rasrc V0 Vainx 20k
Rin Vainx Vains 500
Cext Vainx 0 100n
Cainp Vainx 0 10p
Cainsw Vainsw 0 20p
*----- sample and precharge control

S1 Vainsw Vains sample_on/off 0 ISWITCH
S2 Vprecharge Vainsw precharge_on/off 0 ISWITCH
V_sample_control sample_on/off 0 PULSE(0 1 10n 5n 5n 600n 3400u)

V_precharge_control precharge_on/off 0 PULSE(0 1 1.2u 5n 5n 190n 3400u)
.model ISWITCH SW(Ron=1k Roff=10G Vt=0.5)
*----- leakage current

B_leak Vainx 0 I=12n*V(Vainx)-30n
*----- voltages
Vanalog_source V0 0 5.0
V_precharge Vprecharge 0 2.5
V_LSB12 LSB_12 0 4.9988
V_LSB10 LSB_10 0 4.995
.tran 10u 50m

.end

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6.2 Simulation Results

Figure 19 and Figure 20 “Simulation Result with Leakage Current (VAINx, V0 and VLSB_12)” on Page 37 show
the simulation results of voltage VAINx, which can be measured at the analog input pin ANx to VAGND. After a certain
‘settling’ time, there is a constant peak to peak amplitude of discharging CEXT during sample time and charging
CEXT via RASRC until the start of the next sample event.
After pre-charging CAINSW to VAREF/2 at the end of the conversion, CAINSW has to be charged to V0 during the sample
time via the charge stored in CEXT.
The constant voltage VLSB12 shows a limit of V0 - 1LSB12 (4.998V).
After the circuitry settling period, the charge for loading CAINSW and the charge for loading CEXT are in balance.
Note that the simulation result in Figure 19 does not consider the influence of the leakage current. In Figure 20 a
typical leakage current at room temperature is included in the simulation. In this example the maximum additional
error contributed by the leakage current is about 0.5 LSB12.
Figure 19 Simulation Result without Leakage Current (VAINx, V0 and VLSB_12)

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Figure 20 Simulation Result with Leakage Current (VAINx, V0 and VLSB_12)

The simulation results in Figure 21 “VAINSW without Leakage Current” on Page 38 and Figure 22 “VAINSW with
Leakage Current” on Page 38 show the voltage VAINSW at CAINSW during sample time. This is the voltage which
is converted to a digital value while Successive Approximation is running. This value is then transferred to the A/D
converter result register.
The constant voltage VLSB12 shows the limit of V0 - 1LSB12 (4.998V).
The error of the sampled voltage without considering the leakage current is about 0.5 LSB12. With the leakage
current considered, it is approximately 1 LSB12. Therefore the analog voltage for conversion at CAINSW is about
1.2mV below the voltage of the analog source V0.
When V0 is less than VAREF (VAREF / 2 < V0 < VAREF) then this “input circuit error” is proportionally less than the
1.2mV shown.
The following analog input circuit parameter changes increase the “input circuit error”:
• Increasing RASRC
• Decreasing sample time
• Decreasing cycle time

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Figure 21 VAINSW without Leakage Current
Figure 22 VAINSW with Leakage Current

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Reference Voltage Circuitry Calculation (VAREF and VAGND)
7 Reference Voltage Circuitry Calculation (VAREF and VAGND)

During the charge-redistribution and calibration phases, each group of capacitors from the C-net is individually
switched to either VAREF or VAGND. Because of this switching and the resulting charge transfers in the C-net, the
A/D converter requires a dynamic current at pin VAREF. As a result, the resistance of the voltage reference source
must be low enough to supply the current for the charge-redistribution and calibration phase.
The external circuit at VAREF has a direct influence on the required resistance of the voltage reference. If an
external capacitance CAREF, between VAREF and VAGND is used, then the voltage reference only has to supply a
small continuous current to charge the external capacitor. The necessary peak current during the charge-
redistribution phase is supplied by the external capacitance CAREF. The continuous current and the charge duration
(tCYCLE) must be high enough to fill the external capacitance CAREF to a sufficient voltage level before the next
charge-redistribution phase starts.
7.1 Electrical Model of the A/D Converter Reference Voltage Input

Figure 23 is a simplified block diagram of the A/D converter reference voltage input. The block diagram includes
only the elements necessary for a calculation of the external circuits.
The reference voltage input capacitance CREFSW contains the capacitors of the conversion C-net and all parasitic
capacitors which are also switched during the successive approximation phase.
RAREF is the internal series resistance of the A/D converter reference input.
The bit conversion switch represents an analog switch that is periodically closed during successive approximation.
A/D Converter
tbit_conversion
VAREF
RAREF
VAREF CAREFP
CAREFSW
VAGND
CAREFP = CAREFTOT - CAREFSW
Figure 23 Block Diagram: A/D Converter Reference Voltage Input

The specified values of RAREF, CAREFSW and CAREFTOT are dependent on technology and the type of A/D converter
implementation. The order of magnitude for the values is:
CAREFSW ~ 20 pF
CAREFTOT ~ 30 pF
RAREF ~ 1000 Ω
Note: Please refer to the relevant microcontroller Data Sheet chapter “Electrical Parameter of the A/D converter”
for the exact values.

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7.2 Sources for the Voltage Reference

Depending on the requirements, several different kinds of voltage reference can be used in a system. The supply
voltage of the microcontroller can be selected for the reference voltage for example, but the accuracy is in the
percentage range. The accuracy of an external high precision voltage reference is in the per mille range.
7.2.1 Supply Voltage of the Microcontroller

In most systems, the voltage reference used for the A/D converter is the microcontroller supply voltage VDD. The
typical accuracy of a voltage regulator is 2% (please refer to the relevant power semiconductor Data Sheets from
Infineon for specific details).
When the digital supply voltage of the microcontroller is used as a voltage reference, the recommendation is to
insert a low pass filter between VDD and VAREF (See the figure that follows). The low pass filter has to suppress the
supply ripple on VDD to get a noise free reference voltage VAREF. This is necessary because noise on the reference
voltage has a direct influence to the accuracy of the A/D converter results.
5V VDD
RREF
VAREF
Microcontroller
CAREF
Power
Supply
VAGND
Central
Analog
Ground
GND VSS
Central Digital Ground
Figure 24 Supply Voltage used for Voltage Reference

The values of the capacitance CAREF and the resistor RREF depend on the characteristics of the system and have
a direct influence on overall accuracy.
CAREF provides the necessary charge for loading the MSB of the internal C-net at the start of the charge
redistribution phase, and RREF charges CAREF to a sufficient accuracy.
If there is noise on the system supply voltage with a low frequency, then the low pass cut-off frequency can be
reduced via an appropriate capacitance added in parallel to CAREF, which stabilizes the voltage reference.
Note: The impedance and the noise caused by the connection between Central Analog Ground and Central Digital
Ground should be as low as possible.

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7.2.2 External Voltage Reference

The source for an external voltage reference can be a standard supply voltage with increased accuracy. For
systems where a high accuracy is required, a high precision voltage reference can be used with a typical accuracy
in the range of 2.5 mV ... 20 mV.
VDD
Voltage
Reference RREF
5.000 V VAREF
CAREF
Microcontroller
GND VAGND
Central
Power Analog
Supply Ground
5V VDD
GND VSS
Figure 25 External Voltage Reference

Note: If the supply voltage of the microcontroller and the voltage reference of the A/D converter are switched on
and off at different times, then it is very important that the voltage reference is switched on or off only when
the supply voltage of the microcontroller is ‘on’, otherwise the voltage reference supplies the system with
current via the ESD clamp diode. In that case it is necessary to reduce the overload current to the specified
absolute maximum ratings (See “Overload and Leakage Current” on Page 46). The overload current can
be reduced via a resistor or a diode. If the additional external clamp resistor causes an unacceptable
additional error at VAREF then an external clamp diode should be used.
7.3 IAREF Calculation without an External Capacitance CAREF

If there is no external capacitance between VAREF and VAGND then the voltage reference has to directly supply the
peak current at the charge redistribution phase. This peak current flows only at the beginning of the MSB
conversion and becomes smaller with each converted bit down to the LSB. The minimum current to be supplied
by the voltage reference is:
(14)
V RF
I AREF ≥ ----------------
R AREF
Note: It is not recommended to use a VAREF circuit without an external capacitance CAREF because of the high peak
current in the charge redistribution phase.

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7.4 RREF Calculation with an External Capacitance CAREF

This calculation is based on the assumption that there is an external capacitance CAREF between VAREF and VAGND.
The selected external capacitance has to be high enough such that the total charge, which is necessary to load
the internal C-net (CAREFSW) for a total conversion phase, is provided by the external capacitor CAREF.
Voltage A/D Converter

Reference VERROR tbit_conversion
IAREF
VAREF
RAREF_INT RREF CAREFP RAREF
VRF CAREF VAREF CAREFSW
VAGND
Central Analog Ground CAREFP = CAREFTOT - CAREFSW
Figure 26 A/D Converter during Conversion Phase with CAREF

The following considerations include the value of the external capacitance CAREF with respect to the assumed
maximum voltage error at VAREF (ErrorAREF) caused by CAREF, and the necessary time tCYCLE to reload the external
capacitor.
The relationship between the external capacitance CAREF, the internal C-net CREFSW and the assumed maximum
error caused by CAREF is:
(15)
r+E C AREFSW
C AREF ≥ 2 ⋅ -----------------------
2
with:
r = 8 : 8-bit resolution E = 0 : ErrorAREF = LSBr ErrorAREF = LSBr / 2E

r = 10 : 10-bit resolution E = 1 : ErrorAREF = LSBr / 2 LSBr = VAREF / 2r
r = 12 : 12-bit resolution E = 2 : ErrorAREF = LSBr / 4
Note: The maximum voltage error (ErrorAREF) at VAREF caused by CAREF is referenced to the allowed maximum
input voltage at ANx (VAINx = VAREF). For input voltages at ANx smaller than VAREF the additional in-accuracy
at VAINx is proportionally less than the value of ErrorAREF used in the example calculations. The real additional
inaccuracy at VAINx is:
ErrorAREF_real = (VAINx / VAREF) * ErrorAREF with the condition: VAGND ≤ VAINx ≤ VAREF
Table 8 shows the minimum CAREF values required for different values of A/D converter resolution, and the
maximum allowed ERRORAREF at the reference voltage input VAREF.

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Table 8 CAREF Minimum Value for different Conditions

A/D converter resolution 8bit 10bit 12bit
CAREF_MIN (ERRORAREF = 1 LSB): 4 nF 15 nF 61 nF
CAREF_MIN (ERRORAREF = 0.5 LSB): 8 nF 31 nF 123 nF
The condition (CAREF ≥ 2r+E * CAREFSW / 2) allows a free choice of the A/D converter clock, but the cycle time tCYCLE
has a direct influence on the accuracy of the conversion. The cycle time (total conversion time) has to be long
enough to recharge the external capacitance CAREF before the next charge-redistribution phase is started.
The external capacitance CAREF has to be charged from the voltage reference. The minimum current, which is
drawn from the voltage reference, is based on the charge that is necessary for a complete conversion. The charge
QCONV for a complete charge-redistribution phase and a calibration phase is:
(16)
Q CONV = C AREFSW ⋅ V AREF
The current for the voltage reference depends on the minimum cycle time for a total conversion:
(17)
Q CONV
I AREF = ------------------
t CYCLE
The external resistance RREF between the voltage reference VRF and the input VAREF of the A/D converter has a
significant influence on the accuracy.
Note: This resistor should be as small as possible because the continuous current IAREF causes a voltage drop
VERROR between the voltage reference VRF and the reference voltage input VAREF of the A/D converter (See
Figure 26).
(18)
V ERROR = R REF ⋅ I AREF

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7.4.1 Calculation Example

The assumed values in this example are:
CAREFSW = 30 pF tS = 0.6 µs VRF = 5V

RAREF = 1000 Ω tC = 1.4 µs r = 12 (12-bit resolution)
E =1 ErrorAREF = 0.5 LSB12 = VRF / 4096 / 2 ErrorAREF = 0.62 mV
The value for the external capacitance between VAREF and VAGND is:
CAREF ≥ 2 r+E * CAREFSW / 2

CAREF ≥ 212+1 * 30pF / 2
CAREF ≥ 123nF
Note: A typical recommendation for the value of the external capacitance is CAREF = 220 nF.
Using some µF, external capacitance CAREF can significantly suppress noise on VAREF and increase total
accuracy.
Assuming VAREF = VRF, the minimum continuous current which has to be supplied by the voltage reference is:
IAREF ≥CAREFSW * VAREF / tCYCLE tCYCLE = tS + tC

IAREF ≥ 30 pF * 5 V / 2 µs tCYCLE = 0.6 µs + 1.4 µs
IAREF ≥75 µA tCYCLE = 2 µs
The maximum allowed value for the resistor RREF between voltage reference VRF and input VAREF of the A/D
converter is:
RREF ≤ VERROR / IAREF

RREF ≤ 0.61 mV / 75 µA
RREF ≤ 8.1 Ω @ 12 bit resolution and ErrorAREF = 0.5 LSB12
Using 10 bit resolution:
RREF ≤ 32.5 Ω @ 10 bit resolution and ErrorAREF = 0.5 LSB10
Note: In an overload condition it is possible that RREF has to be increased, to limit the overload current to the
specified values. If the value of RREF exceeds the error limit of the system, an external diode between VAREF
and VDD can reduce the overload current (See Figure 25 “External Voltage Reference” on Page 41).
Note: Depending on the implementation, in the best case there should be one input pin VAREF per A/D converter.
Some microcontrollers however may only have one VAREF pin for several different A/D converters because
of the pin limitations of the package being used. In this instance the external circuitry at pin VAREF has to be
selected after considering and summing up all individual A/D converter requirements.

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7.5 Ratiometric Configuration

In a non-ratiometric configuration there is no relation between the voltage of the analog source and the reference
voltage at pin VAREF. Both the accuracy of the reference voltage and the accuracy of the analog source have an
influence on the accuracy of the total A/D conversion system, because any changes in the supply voltage of the
analog source results in a change at the analog input voltage (ANx) seen by the A/D converter. Since the voltage
reference is independent from the analog source excitation, the A/D conversion result will reflect the changed
excitation.
Figure 27 shows the principle of a ratiometric configuration. The same voltage reference source is used for the
analog source excitation and the reference voltage input VAREF. Therefore a given change in the analog source
excitation causes the same change at the reference voltage VAREF.
The A/D converter conversion result is the ratio of the analog input ANx, to the reference voltage VAREF. Since both
the analog input ANx and the reference voltage VAREF are derived from the same voltage reference source,
changes do not cause measurement errors. The A/D converter conversion result is therefore independent of
variations in the analog source excitation or from variations in the reference voltage input VAREF. A stable voltage
reference is therefore not necessary to achieve an accurate measurement result.
Voltage
Reference VDD
Analog RREF
Source
VAREF
CAREF
VAGND Microcontroller
Central Analog Ground
ANx
Power
Supply
5V VDD
GND VSS
Figure 27 Ratiometric Configuration

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Overload and Leakage Current
8 Overload and Leakage Current

Both overload and leakage currents are specified in the Data Sheet of the selected microcontroller. Consideration
of these currents can influence the design of the external components of the analog source. Figure 28 is a
simplified electrical model with ESD structure (clamp diodes) and leakage current of an analog input.
Analog VDD
Source
Microcontroller
IOZx IOV>0
ANx
MUX
RASRC IOV<0 IOZx
VLEAK
V0 VSS VSS
ESD Structure Leakage Source
Figure 28 A/D Converter Input with ESD Structure and Leakage Source
Note: The ESD structure of the reference voltage VAREF and of the reference ground VAGND is the same as shown
in Figure 28.

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8.1 Leakage Current

The input leakage current is the sum of all currents which can flow into or out of an input pin caused by parasitic
effects of the input structure (see Figure 28).
The maximum input leakage current of the A/D converter is specified in the ’DC Characteristics’ section of the
appropriate Data Sheet.
Note: The symbol for the input leakage current used in the Data Sheet is in most cases IOZx.
The input leakage current has to be taken into account for the calculation of the maximum allowed error of the A/D
converter result with reference to the analog source, because the resistance of the analog source RASRC and the
input leakage current IOZx can cause an additional error via the external ’leakage voltage’ VLEAK.
(19)
V LEAK = I OZx ⋅ R ASRC
The leakage voltage VLEAK can cause an additional un-adjusted error AUELEAK.
(20)
V LEAK
AUE LEAK = -----------------
1LSBr
8.1.1 Calculation Example

Assumed system values:
AUELEAK = 0.5 LSB Assumed maximum additional un-adjusted error caused by

resistance of the analog source RASRC and leakage current
VAREF =5V 1 LSB12 = 1.22 mV
IOZx = |± 200 nA| Maximum input leakage current
To calculate the allowed maximum resistance of the analog source RASRC:
RASRC = VLEAK / IOZx

RASRC = AUELEAK * 1LSB / IOZx
RASRC = 0.5 * 1.22 mV / 200 nA
RASRC = 3050 Ω
Note: The Input Leakage Current can significantly reduce the total A/D conversion accuracy when the resistance
of the analog source RASC has a high value.

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8.2 Overload Current

An overload condition is not a normal operating condition. It occurs if the standard operating conditions are
exceeded; i.e. the voltage on an A/D converter input pin VAINx exceeds the specified range (VAINx > VDD + 0.5 V
or VAINx < VSS - 0.5 V). The supply voltage must remain within the specified limits.
Where there is an overload condition on an A/D converter input pin, one of the clamp diodes becomes conductive:
• If VAINx > VDD + 0.5 V then the clamp diode connected to VDD begins to conduct
• If VAINx < VSS - 0.5 V then the clamp diode connected to VSS begins to conduct
(See Figure 28 “A/D Converter Input with ESD Structure and Leakage Source” on Page 46)
Notes
1. The symbol for the overload current (also called injection current) used in the relevant microcontroller Data
Sheet is in most cases IOV.
2. The specified value of the A/D converter overload current depends on the device type. Please refer to the
appropriate Data Sheet for the exact value.
3. The overload current has to be taken into account for the calculation of external resistors which protect the
microcontroller inputs. These external resistors guarantee that, in case of a system error, the specified
maximum value of the overload current will not be exceeded. The calculation also has to consider the specified
absolute sum of input overload currents on all port pins or a pin group of the microcontroller, and especially
the specified absolute sum of the A/D converter input.
8.2.1 Overload Current and Absolute Maximum Ratings

The parameters of the Absolute Maximum Ratings are stress ratings only. The functional operation of the
microcontroller is not guaranteed at these or other conditions above the ’operation conditions’.
Attention: Stresses above the absolute maximum ratings may cause permanent damage to the
microcontroller. Exposing the microcontroller to absolute maximum rating conditions for
extended periods may affect device reliability.
When the system is switched off, or in periods where it is not necessary to guarantee correct operation, the
absolute maximum ratings are the fundamental information for the calculation of the input overload current, which
may occur in case of a system error. In those instances the specified maximum overload current specified in the
relevant Data Sheet may not be exceeded.
8.2.1.1 Calculation Example

VDD =0V System supply voltage is off (worst case)

VErr_max = 14 V Maximum voltage of the analog signal in case of a fatal system error
IOV_max = |±10 mA| Maximum input leakage current (absolute maximum rating)
To calculate the minimum value for the external resistor RP to protect an analog input pin for a short time overload
condition:
RP_min = (VErr_max - VDD - 0.5 V) / IOV_max

RP_min = (14 V - 0 V - 0.5 V) / 10 mA
RP_min = 1350 Ω

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8.2.2 Overload Current and Operating Conditions

The Operating Conditions must not be exceeded in order to ensure correct operation of the microcontroller.
The specified operating conditions allow a typical maximum overload current of IOV = ±3 mA on any pin, and the
absolute sum over input overload currents on all port pins is typically |50| mA.
The specified TUE of the A/D converter is guaranteed only if the specified absolute sum of input overload currents
on all analog input pins is not exceeded. For the exact values, please refer to the appropriate Data Sheet.

VDD = 4.5 V Minimum system supply voltage during operating conditions (worst
case)
VErr_max = 14 V Maximum voltage of the analog signal in case of a fatal system error
IOV_max = |±3 mA| Maximum of the overload current during operating conditions
To calculate the minimum value of the external resistor RP to protect an analog input of the microcontroller and
ensure correct operation:
RP_min = (VErr_max - VDD - 0.5 V) / IOV_max

RP_min = (14 V - 4.5 V - 0.5 V) / 3mA
RP_min = 3000 Ω
Note: Overload current must be drained via ESD to VDD line, otherwise VDD could be charged up to 14V.
8.2.3 Coupling Factor

Depending on the A/D converter used, an overload current coupling factor for positive and negative overload
currents (KOV) is specified:
• KOVAP is usually specified for positive overload currents
• KOVAN is usually specified for negative overload currents
An overload current (IOV) through a pin injects an error current (|IINJ| = |IOV| * KOV) into the direct adjacent pins. This
error current adds to that pin’s leakage current (IOZ).
The value of the error current depends on the overload current and is defined by the overload coupling factor KOV.
The polarity of the injected error current is reversed from the polarity of the overload current that produces it.
The total leakage current through a pin is:
|IOZTOT| = |IOZ| + |IINJ|

|IOZTOT| = |IOZ| + (|IOV| * KOV)
The additional error current IINJ distorts the analog input voltage VAINX because of the additional voltage VLEAK at
RASRC. Details are shown in the following figure.

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ANx+/-1
Microcontroller
Over Voltage IOV MUX
IINJ = IOV * KOV

VDD
Analog
Source
IOZTOT ANx IOV>0 MUX
RASRC IOV<0
VAINx
VLEAK IOZ
CEXT
V0 VSS VSS
ESD Structure Leakage Source
Figure 29 Relationship between Overload Current, Leakage Current and the Coupling Factor

IOV = |±3 mA| IOZ = |±200 nA|

KOVAP = 0.00001 KOVAN = 0.0001
Note: Details of the Overload Current, Leakage Current and Coupling Factor are described in the appropriate Data
Sheet for each particular device.
To calculate the total leakage current:
IOZTOT_MAX = |IOZ| + (|-IOV| * KOVAN) IOZTOT_MIN = -|IOZ| + (-|IOV| * KOVAP)

IOZTOT_MAX = 200 nA + 3 mA * 0.0001 IOZTOT_MIN = -200 nA - 3 mA * 0.00001
IOZTOT_MAX = 500 nA IOZTOT_MIN = -230 nA

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PCB and Design Considerations
9 PCB and Design Considerations

This chapter is an introduction to mixed signal board design and offers a list of guidelines for optimum printed
circuit board layout for microcontrollers with an on-chip A/D converter.
9.1 Component Placing

The guidelines for component placing are:
• Partition the board with all analog components grounded together in one area and all digital components in the
other. Common power supply related components should be centrally located. An example is shown in
Figure 31 “Example for functional Partitioning” on Page 52.
• Mixed signal components, including the microcontroller, should only bridge the partitions with analog pins in
the analog area and digital pins in the digital area. Rotating the microcontroller can often make this task easier.
9.2 Power Supply

The guidelines for the power supply are:
• Place the analog power and voltage reference regulators over the analog plane.
• The digital power regulators should be over the digital plane.
• Analog power traces should be over the analog ground plane.
• Digital power traces should be over the digital ground plane.
• De-coupling capacitors should be close to the microcontroller pins, or positioned for the shortest connection to
pins with wide traces to reduce impedance.
• If both large and small ceramic capacitors are recommended, position the small ceramic capacitor closest to
the microcontroller pins.
Via connection to GND
VSS
Microcontroller
CAP
CAP
VDD
Via connection
to V DD
VDDP
Via connection to V DDP
Figure 30 Example for Decoupling Capacitor Placing

AP56003
9.3 Ground Planes

The guidelines for ground planes are:
• Have separate analog and digital ground planes on the same layer, separated by a gap, with the digital
components over the digital ground plane and the analog components over the analog ground plane. An
example for functional partitioning is shown in Figure 31.
• Analog and digital ground planes should only be connected at one point (in most cases). One of the best places
is below the microcontroller. Have vias available in the board to allow alternative connection points.
• The connection of the analog and digital ground planes should be near to one of the following:
– the power supply
– the power supply connections to the board
– the microcontroller
• For boards with more than two layers, do not overlap analog and digital related planes. Do not have a plane
that crosses the gap between the analog ground plane and the digital ground plane region.
Figure 31 Example for functional Partitioning

AP56003
9.4 Signal Lines

The guidelines for signal lines are:
• Analog signal traces should be over the analog ground plane.
• Digital signal traces should be over the digital ground plane.
• Regions between analog signal traces should be filled with copper, which should be electrically attached to the
analog ground plane.
• Regions between digital signal traces should be filled with copper, which should be electrically attached to the
digital ground plane. These regions should not be left floating as this increases interference. The use of ground
plane fill has been shown to reduce digital to analog coupling by up to 30 dB.
9.5 Clock Generation

The guidelines for clock generation are:
• Locate the quartz crystal, ceramic resonator or external oscillator as close as possible to the microcontroller.
• Keep digital signal traces, especially the clock signal, as far away from the analog input and voltage reference
pins as possible.
• Avoid multiple oscillators or asynchronous clocks. Best results are obtained when all circuits are synchronous
to the A/D converter sampling clock.

AP56003
Abbreviations
10 Abbreviations
Abbreviation used in this document with an associated explanation.
Table 9 Abbreviations
Abbreviation Explanation
ADC Analog Digital Converter
ANx Analog input x
AUELeak Additional unadjusted error caused by the leakage current
CAINSW A/D converter switched input capacitance (internal C-net) CAINWS = CAINTOT - CAINP
CAINSW_max Maximum value of the A/D converter switched input capacitance
CAINP A/D converter input pad capacitance
CAINTOT A/D converter input pad total capacitance
CAREF External capacitance connected to the reference voltage input VAREF
CAREFP A/D converter input pad capacitance at VAREF
CAREFSW A/D converter switched reference capacitance. CAREFWS = CAREFTOT - CAREFP
CAREFTOT A/D converter total input pad capacitance at VAREF
CEXT External capacitance connected to the analog input
C-Net Internal A/D converter capacitor network.
C 9 - C0 C-net for conversion (10-bit resolution).
C7’ - C0’ C-net for calibration.
chn Analog channel n
DNLE Differential nonlinearity error
E Variable for allowed Error to calculate CAREF
ErrorAINx Maximum voltage difference between V0 and VANx at the end of the sample time
ErrorAREF Maximum voltage error at VAREF caused by CAREF
ESD Electrostatic discharge
fCPU CPU frequency
fC Cutoff frequency
fCYCLE Cycle frequency of sample events (fCYCLE = 1 / tCYCLEn)
fCYCLEn Cycle frequency of sample events at channel n
INLE Integral nonlinearity error
IAREF Current of the voltage reference
IINJ Error current which is injected by an overload current to the direct adjacent pins
IOV Overload current
IOV_max Specified maximum rating of the overload current or Specified maximum of the
overload current during operating conditions
IOZTOT Total input leakage current including Error current caused by overload current at
adjacent pin
IOZTOT_MAX Maximum total input leakage current
IOZx Input leakage current
KOVA Analog overload coupling factor

AP56003
Abbreviations
KOVAN Analog overload coupling factor for negative overload current
KOVAP Analog overload coupling factor for positive overload current
LSB Least significant bit (general)
LSBr Least significant bit referred to r-bit resolution (LSBr = VAREF / 2r)
MSB Most significant bit
r Resolution of the A/D converter
RAIN Internal series resistance of the A/D converter
RASRC Internal resistance of the analog source
RREF Resistance between voltage reference and VAREF input
RAREF_EXT Internal resistance of the voltage reference
RP External resistor RP to protect an analog input in case of an overload condition
RP_min Minimum value for the external resistor RP
RON Simulation: Sample switch RON resistance
tC Conversion time
tCn Conversion time of analog channel n
tCYCLE Cycle time
tCYCLEn Cycle time of analog channel n
tS Sample time
t1, t2, t3 Time constants for the different phases of a conversion
TUE Total unadjusted error
VAREF Reference voltage input for the A/D converter
VAGND Reference ground for the A/D converter
VANx Voltage at the analog input ANx
VCAINSW Voltage at the internal C-net
VC (t) Charge curve of CEXT for a total cycle
VC (tCYCLE) Voltage of CEXT at the end of a total cycle
VDD Supply voltage
VERROR Voltage at RREF
VERR_max Maximum voltage of an analog signal in case of a fatal system error
VLeak Leakage voltage at RASRC
VLSB_12 Simulation: Limitvoltage for the simulation plot (VLSB_12 = V0 - 1LSB12)
VPRECHARGE Precharge voltage of the internal C-Net at start of sample time
VR Missing rest voltage of VAINx at the end of a conversion cycle
VRF Voltage reference
VSS Digital GND
VS(t) Voltage curve during sample time
VS(tS) Voltage at the end of sample time

AP56003
Abbreviations
V0 Voltage of the analog source
V∆ Voltage drop at the beginning of the sample time

w w w . i n f i n e o n . c o m
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8/16/32-Bit

A Guide to the Analog Part of the A/D

We Listen to Your Comments

Application Note 3 V1.0, 2012-09

Application Note 4 V1.0, 2012-09

7.3 IAREF Calculation without an External Capacitance CAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Application Note 5 V1.0, 2012-09

Application Note 6 V1.0, 2012-09

Transfer Characteristic and Error Definition

2 Transfer Characteristic and Error Definition

2.1 Ideal Transfer Characteristic

Digital Output Ideal Transfer Curve

3 TUE related to ideal

2 TUE related to ideal

0.5 LSB Inherent Analog Input Voltage [LSB]

Figure 1 Ideal Transfer Characteristic

Application Note 7 V1.0, 2012-09

Transfer Characteristic and Error Definition

Quantization Error [LSB]

Application Note 8 V1.0, 2012-09

Transfer Characteristic and Error Definition

2.2 Offset Error

Ideal Transfer Curve

including the Offset Error

Offset Error Analog Input Voltage [LSB]

Figure 3 Offset Error

Application Note 9 V1.0, 2012-09

Transfer Characteristic and Error Definition

2.3 Gain Error

Application Note 10 V1.0, 2012-09

Transfer Characteristic and Error Definition

2.4 Differential Non-Linearity Error (DNLE)

Ideal Transfer Curve

5 Ideal ADC Transfer Curve

Application Note 11 V1.0, 2012-09

Transfer Characteristic and Error Definition

2.5 Integral Non-Linearity Error (INLE)

Ideal Transfer Curve

Application Note 12 V1.0, 2012-09

Figure 7 A/D Converter Timing

3.1 Sample Phase

3.2 Charge-Redistribution Phase

Application Note 13 V1.0, 2012-09

3.3 Calibration Phase

3.4 Write-Back Phase

Calibration C-Net RAM

C7’ C6’ C5’ C4’ C3’ C2’ C1’ C0’

Application Note 14 V1.0, 2012-09

Calibration Mechanism (Error Correction)

4 Calibration Mechanism (Error Correction)

4.1 Calibration Principle

4.2 Reset Calibration

Application Note 15 V1.0, 2012-09

Calibration Mechanism (Error Correction)

4.3 Normal Calibration

4.4 Disturbance Filtering

Application Note 16 V1.0, 2012-09

Analog Input Circuitry Calculation (AN0 ... ANy)

The following table gives typical values of 7.6t1 and 9t1.

Table 1 Typical Values for 7.6t1 and 9t1