Infineon-AP56003 ADC Analog Aspects-AN-v01 00-EN
Infineon-AP56003 ADC Analog Aspects-AN-v01 00-EN
Infineon-AP56003 ADC Analog Aspects-AN-v01 00-EN
Application Note
V1.0, 2012-09
Microcontrollers
Edition 2012-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2012 Infineon Technologies AG
All Rights Reserved.
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A Guide to the Analog Part of the A/D Converter
AP56003
Device1
Revision History: V1.0 2012-09
Previous Version(s):
Page Subjects (major changes since last revision)
– This is the first release …
Trademarks
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Transfer Characteristic and Error Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Ideal Transfer Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Differential Non-Linearity Error (DNLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Integral Non-Linearity Error (INLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Principle of Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Sample Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Charge-Redistribution Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Calibration Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Write-Back Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Calibration Mechanism (Error Correction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Calibration Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Reset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Normal Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Disturbance Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Analog Input Circuitry Calculation (AN0 ... ANy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Electrical Model of the A/D Converter Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Accuracy at Sample Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Charge Flow during Sample Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.1 Charge Balance between CAINSW and CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3.2 Charge of CAINSW and CEXT via RASRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4 RASRC Calculation with (0 pF < CEXT < (2r - 1) * CAINSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4.1 Charge-Redistribution Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4.2 Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4.3 Calculation Example with (0 pF < CEXT < (2r -1) * CAINSW) and r = 12 . . . . . . . . . . . . . . . . . . . . . . . 26
5.4.3.1 Resistance of the Analog Source RASRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.3.2 Cycle Time tCYCLEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5 RASRC Calculation with (CEXT > (2r -1) * CAINSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5.1 External Capacitance CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5.2 Cycle Time tCYCLEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.5.3 Cutoff Frequency fC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.5.4 Calculation Example with (CEXT > (2r - 1) * CAINSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.6 RASRC Calculation with (CEXT = 0pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.6.1 Resistance of the Analog Source RASRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.6.2 Calculation Example with (CEXT = 0pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6 Analog Input Circuitry Simulation (AN0 ... ANy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1 Analog Input Circuitry Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7 Reference Voltage Circuitry Calculation (VAREF and VAGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1 Electrical Model of the A/D Converter Reference Voltage Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2 Sources for the Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2.1 Supply Voltage of the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2.2 External Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Introduction
1 Introduction
The majority of Infineon Microcontroller products include an integrated, on-chip A/D (Analog/Digital) converter for
analog signal measurement, with multiplexed input channels and a sample and hold circuit.
Depending on the device type, the integrated A/D converter allows resolutions of 8-bit, 10-bit or 12-bit. Because
the A/D converter uses the Successive Approximation (SAR) method, it is also known as the SAR-A/D converter
(Successive Approximation Register A/D converter). This A/D converter type uses binary weighted conversion
capacitors and one sample and hold unit per A/D converter.
Other types of A/D converter with non binary weighted conversion capacitors, such as FADC (Fast A/D converter)
or with multiple sample and hold units per A/D converter are not covered in this Application Note. The DS-A/D
converter (Delta Sigma A/D converter) is also not covered in this Application Note.
In principle, the A/D converter can be divided into two parts:
• Analog part
– including the converter with sample and hold circuit
• Digital part
– which contains registers and the digital control unit
This Application Note provides basic information and recommendations for the analog part of the A/D converter.
Please refer to the appropriate microcontroller User Manual for the description of the digital part.
For historical and evolutionary reasons, different implementations of the A/D converter are available. The
differences in the analog part mainly concern the values in the A/D converter characteristics specified in the related
Data Sheet.
The resolution (r) of the A/D converter refers to the number of quantization levels an analog input voltage can be
determined to. The number of smallest levels is given in bits and one of these is the Least Significant Bit (LSB).
Figure 1 shows an example of an A/D converter with 210 - 1 = 1023 output quantization levels.
An A/D converter with 10-bit resolution quantizises an analog input voltage of 5 V to a step size of:
5 V / 210 = 4,88 mV
The values represent the digital output range from 0 to 1023.
This theoretical accuracy of an A/D converter is degraded by inaccuracies of the A/D converter itself (total
unadjusted error). Additionally the accuracy of the complete A/D conversion system is degraded by the external
elements which are connected to the analog input ANx and to the reference voltage VAREF. It is the task of the
system designer to keep the inaccuracies caused by the external circuits as low as possible, and this Application
Note provides the necessary basic information to optimize the external circuits of the A/D converter.
3FE (4)
5
10 Bit Resolution
0
0 0.5 1 2 3 4 5 1022 1023 1024
given range (quantization step) are represented by the same digital value, which corresponds to the nominal mid-
range value. That is the reason for the quantization uncertainty of +/- 0.5 LSB, which is a natural error and inherent
to each A/D converter.
The analog input voltage range must be within VAGND up to VAREF.
The quantization step size is 1 LSB = VAREF / 2r.
According to the Ideal Transfer Curve (1) the first digital transition, from 0 to 1, is shifted to the analog value of 0.5
LSB to get a minimum quantization uncertainty. That is why the first step width of the Ideal ADC Transfer Curve
(2) is 0.5 LSB, and the last step width is 1.5 LSB with an digital output range from 0 to (2r - 1).
The compensated inherent quantization error in relation to the analog input voltage is shown in Figure 2.
0.5
Analog
Input
0
1 2 3 4 5 1022 1023 1024 Voltage
[LSB]
-0.5
-1.0
Figure 2 Quantization Error
The total unadjusted error includes all A/D converter related inaccuracies such as production process deviations
and internal noise.
The TUE consists of offset error, gain error, DNLE and INLE, but it is not simply the sum of individually measured
errors. Because some ADC errors such as offset and gain, can compensate each other, the TUE can be far less
than the absolute sum of all individual errors. Figure 1 shows the definition of the TUE in relation to the Ideal ADC
Transfer Curve (1).
The real result of the A/D converter is in the range of Ideal ADC Transfer Curve (2) +/- TUE. This area is shaded
in Figure 1 and is between both TUE related to ideal ADC Transfer Curves (3) and (4).
Note: Reference voltages are considered as the ideal. An incorrect reference voltage generates an additional
error.
Digital Output
3FE
Ideal ADC Transfer Curve
5
Real ADC Transfer Curve
10 Bit Resolution
0
0 1 2 3 4 5 1022 1023 1024
Digital Output
Gain Error
3FF
Ideal Transfer Curve
3FE
Ideal ADC Transfer Curve
5
Real ADC Transfer Curve
10 Bit Resolution
0
0 1 2 3 4 5 1022 1023 1024
Analog Input Voltage [LSB]
Figure 4 Gain Error
3FF
Ideal Transfer Curve
ADC Transfer Curve
3FE
Real ADC Transfer Curve
Missing Code
4
0
0 0.5 1 2 3 4 5 1022 1023 1024
Analog Input Voltage [LSB]
DNLE = 1 LSB
Figure 5 Differential Non-Linearity Error
Digital Output
3FE
Ideal ADC Transfer Curve
5
Real ADC Transfer Curve
10 Bit Resolution
0
0 0.5 1 2 3 4 5 1022 1023 1024
Analog Input Voltage [LSB]
INLE = 1 LSB
Figure 6 Integral Non-Linearity Error
Principle of Conversion
3 Principle of Conversion
The A/D converter is based on the principle of Successive Approximation. It uses a capacitor network in order to
compare the analog input voltage with a reference voltage, generated from VAREF and VAGND. This reference
voltage is adapted step by step through Successive Approximation.
The capacitor network is also used for the sample and hold function. The conversion is performed in several steps.
A total conversion consists of:
• Sample phase
• Charge-redistribution phase (conversion phase)
• Calibration phase (only A/D converter with enabled calibration)
• Write-back phase
The sequence of the different phases is shown in Figure 7. The total ADC conversion time is controlled via
software. The block diagram in Figure 8 is related to a calibrated A/D converter with 10-bit resolution and
represents the principle connections between the analog input ANx, conversion C-net, comparator, and the A/D
converter result register.
Start of End of
Conversion Conversion
MSB LSB
Sample Calibration
Phase Charge-Redistribution Phase
Phase
Write back
Phase
ADC Conversion Time
Principle of Conversion
Comparator
ADDAT
CHOLD
Calibration
Control
Conversion C-Net
C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
Conversion
ANx
Control
VAREF
VAGND
Figure 8 Block Diagram: Analog Part of a 10-bit A/D Converter with Calibration and Conversion C-Nets
Notes
1. After reset, the positive and negative analog reference voltages (VAREF and VAGND) must be stable and within
the specified range, in order to perform a valid reset calibration.
2. The reset calibration can be interrupted by any conversion. If interrupted, the reset calibration is lengthened
by the conversion time. The calibration sequence is performed with the actual values of the control register. A
change of the Conversion Time Control also changes the duration of the calibration sequence.
During the reset calibration sequence, conversion results can exceed the specified maximum TUE.
3. When entering IDLE or Slow Down Mode the reset calibration will continue until it is finished but the Power
Down current increases. It is therefore recommended to wait until reset calibration is finished before entering
IDLE or Slow Down Mode.
VAINx Sample
V0 CAINP
ANy CAINSW VAINSW
CEXT
CAINP
VAGND
The external capacitance CEXT can be a real external capacitor for noise reduction, or only the parasitic
capacitance caused by the signal line between analog source and A/D converter input.
The analog voltage source is represented by an ideal voltage source V0 and a series resistance RASRC.
The specified values of RAIN, CAINSW and CAINTOT are dependent on technology and the type of A/D converter
implementation. The order of magnitude for the values is:
• CAINSW ~ 20 pF
• CAINTOT ~ 30 pF
• RAIN ~ 1000 Ω
Note: Please refer to the Data Sheet chapter “Electrical Parameter of the A/D converter” for the exact values of the
microcontroller under consideration.
|V0-VAINSW |
VAREF/2
V0
VAGND VAREF/2 VAREF
Figure 10 Voltage Difference between V0 and VAINSW at the start of the Sample Time
Note: The assumed error (ErrorANx) used in this chapter (Analog Input Circuitry Calculation (AN0 ... ANy)) for
the calculation examples references the allowed maximum input voltage at ANx (VAINSWx = VAREF). For input
voltages at ANx smaller than VAREF the additional inaccuracy at VAINx is proportionally less than the value of
ErrorANx used in the example calculations.
Depending on the phases of the A/D converter, different time constants (‘t’) have to be considered:
• t1 : Time constant at the beginning of the sample time
– Contains CAINSW, CEXT and RAIN
• t2 : Time constant during sample time
– Contains CAINSW, CEXT and RASRC
• t3 : Time constant during and after the charge-redistribution phase
– Contains CEXT and RASRC
RAIN
Sample
VAINx
CEXT VAINSW ~ VAREF/2 CAINSW
C AINSW ⋅ C EXT
t 1 = R AIN ⋅ ---------------------------------------
C AINSW + C EXT
Depending on the microcontroller, the values for CAINSW are typically in the range of:
• CAINSW : 5 pF up to 20 pF
The charge balance between CAINSW and CEXT causes a voltage jump VΔ at the analog input ANx.
Depending on the voltage on ANx when the sample phase starts, the voltage can be increased or decreased.
The example in Figure 13 uses the worst case V0 = VAREF.
At the end of 7.6*t1 the voltage at ANx is reduced (or increased) by the value V∆ with an accuracy of 0.5 LSB10
and after 9*t1 with an accuracy of 0.5 LSB12.
Using this simplified model the charge balance between CEXT and CAINSW results in the formula for V∆:
(2)
C AINSW ⋅ ( V 0 – V CAINSW )
V Δ = -----------------------------------------------------------------
C AINSW + C EXT
Table 2 Typical Values for the Voltage Jump V∆ with Pre-charge disregarding RASRC:
V0 - VCAINSW = 2.5 V and V0 = VAREF
CEXT 1 pF 10 pF 100 pF 1 nF 10 nF 100 nF 1 µF
V∆ 1) 2.4 V 1.7 V 400 mV 50 mV 5 mV 0.5 mV 0.05 mV
2)
V∆ 2.1 V 0.8 V 120 mV 12 mV 1.2 mV 0.1 mV 0.01 mV
1)
Voltage Jump V∆@ CAINSW = 20 pF and RAIN = 1500 Ω
2)
Voltage Jump V∆ @ CAINSW = 5 pF and RAIN = 2000 Ω
RASRC RAIN
V0
CEXT CAINSW
The voltage on ANx at the end of the sample time can also be described with the formula VS(tS).
The ErrorANx describes the maximum deviation allowed between the voltage on ANx and V0 when the sample time
is finished.
An assumed ErrorANx of 0.5 LSB is equivalent to the values shown in the following table:
Table 3 Absolute Values of 0.5 LSB for different A/D Converter Resolutions
Resolution 8-bit 10-bit 12-bit
0.5 LSB @ VAREF = 5 V 9.76 mV 2.44 mV 0.61 mV
0.5 LSB @ VAREF = 3.3 V 6.45 mV 1.61 mV 0.40 mV
(5)
Now it is possible to calculate the maximum value of the analog source resistance RASRC.
The formula for RASRC assumes that RAIN = 0 Ω.
(6)
tS
R ASRC = -----------------------------------------------------------------------
VΔ
( C AIN + C EXT ) ⋅ ln ---------------------- -
Error ANx
VAIN
V0 = VAREF t2 t3
ErrorANx
VS(tS)
VΔ
Sampled
Voltage
VS(t)
V0 - VΔ
t1 t2
t
tS tCR
tC
tCYCLEn
RASRC
V0
CEXT
t 3 = R ASRC ⋅ C EXT
While the external capacitance CEXT is charged via RASRC, the A/D converter performs the Successive
Approximation (charge-redistribution). This is the transformation of the analog voltage into a digital value. The
reference for the transformation is the reference voltage at pin VAREF referred to VAGND. It is very important for an
exact conversion result to hold the reference voltage and the reference ground on a constant level during the
charge-redistribution. See also “Reference Voltage Circuitry Calculation (VAREF and VAGND)” on Page 39.
tC x tC y tC z tC x
tCYCLEn
Note: After 9 * t3 the remaining deviation from V0 is 0.012% (~0.5 LSB12) of the assumed ErrorANx for VS(tS).
Using 7.6 * t3 the remaining deviation from V0 is 0.049% (~0.5 LSB10) of the assumed ErrorANx for VS(tS).
5.4.3 Calculation Example with (0 pF < CEXT < (2r -1) * CAINSW) and r = 12
The assumed values used in the example are:
The table shows the different results of RASRC with the assumed values used in the example.
Note: The capacitive load at the analog inputs ANx should be as small as possible because it reduces the allowed
resistance of the analog source RASRC (as shown in Table 4). The only exception is the use of a very high
value for the external capacitance CEXT, which supplies the A/D converter with the necessary charge during
the sample phase.
The calculated cycle time tCYCLEn is longer than the conversion time tC and, in that case, continuous conversion of
this analog channel is only possible by inserting a waiting period to charge the external capacitance CEXT.
Error = LSBr / 2
Error = VAREF / (2r * 2)
Error > V∆ = (CAINSW * (VAREF - VAREF / 2)) / (CAINSW + CEXT)
Depending on the A/D converter resolution the relationship between CEXT and CAINSW is:
The condition CEXT > (2 r - 1) * CAINSW allows the choice of a very short sample time tS because of the small time
constant t1. Table 1 can be used to help with the appropriate selection of a sample time. Note that the value of
RASRC has a direct influence on the conversion cycle time tCYCLEn.
The charge curve VC(t) of the capacitor CEXT via the resistance of the analog source RASRC is:
(10)
–----t
t3
V C ( t ) = V AREF – Error ANx ⋅ e
With an assumed maximum allowed error of LSBr / 2 (ErrorANx = (VAREF / 2 r) / 2) and with t3 = RASRC * CEXT the
formulas result in the relation:
(11)
C EXT
t CYCLE ≥ R ASRC ⋅ C EXT ⋅ ln ----------------------------------------------------
-
r
C EXT – ( 2 ⋅ C AINSW )
VAINx
ErrorANx
VC(tCYCLEn) VΔ
VC(t)
Sampled
Voltage
Figure 16 Voltage VAINx with CEXT > 2r * CAINSW and periodical Conversions
Note: If the external circuit reaches the cutoff frequency then the voltage of the analog source V0 is damped with the factor
-3 dB (VAIN ~ 0.7 * V0 @ cutoff frequency fC ).
The calculations result in the values of cycle time tCYCLEn and cutoff frequency fC.
The values of the external capacitance CEXT and resistance of the analog source RASRC are fixed in relation to the
cycle time tCYCLEn:
fC = 1 / (2 * π * RASRC * CEXT)
fC = 1 / (2 * π * 20 kΩ * 100 nF)
fC = 80 Hz
Table 5 shows calculation results of the cycle time in [ms] for different values of RASRC with the assumed values
of the example (ErrorANx = 0.5 LSB12).
Table 5 Cycle Time tCYCLEn for different Values of RASRC with CEXT = 100nF
RASRC [kΩ] 1 5 10 15 20 25 30 40 50 100
tCYCLEn [ms] 0.2 0.9 1.7 2.6 3.4 4.3 5.1 6.8 8.6 17.1
Table 6 shows calculation results of the cutoff frequency in [Hz] for different values of RASRC with the assumed
values of the example (ErrorANx = 0.5 LSB12).
Table 6 Cutoff Frequency fC for different Values of RASRC with CEXT = 100nF
RASRC [kΩ] 1 5 10 15 20 25 30 40 50 100
fC [Hz] 1592 318 159 106 80 64 53 40 32 16
RASRC RAIN
V0 CAINSW
The resistance of the analog source RASRC, is calculated with the formula for systems with a small external
capacitance but without CEXT and with RAIN.
(13)
tS
R ASRC = ------------------------------------------------------ – R AIN
VΔ
C AINSW ⋅ ln ---------------------- -
Error ANx
The calculation of the cycle time is not necessary because during sample time the internal C-net is connected to
the analog source. In the other phases of the cycle time the internal C-net is disconnected from the analog source.
Therefore no external capacitance has to be charged via RASRC until the start of the next sample time.
The table shows the maximum values for RASRC and different sample times with the assumed values of the
example:
Note: The leakage current specified in the Data Sheet for the given microcontroller can influence the accuracy of
the analog input voltage, when the value of RASRC exceeds a certain limit. This limit depends on the allowed
inaccuracy (VAINx), which is determined by the demands of the system. See also ““Overload and Leakage
Current” on Page 46”.
Pulse Pulse
Sample Precharge
RASRC RAIN
V0 VAINx VAINS VAINSW VPRECHARGE
20k 1.5k
*----- voltages
Vanalog_source V0 0 5.0
V_precharge Vprecharge 0 2.5
V_LSB12 LSB_12 0 4.9988
V_LSB10 LSB_10 0 4.995
A/D Converter
tbit_conversion
VAREF
RAREF
VAREF CAREFP
CAREFSW
VAGND
CAREFP = CAREFTOT - CAREFSW
CAREFSW ~ 20 pF
CAREFTOT ~ 30 pF
RAREF ~ 1000 Ω
Note: Please refer to the relevant microcontroller Data Sheet chapter “Electrical Parameter of the A/D converter”
for the exact values.
5V VDD
RREF
VAREF
Microcontroller
CAREF
Power
Supply
VAGND
Central
Analog
Ground
GND VSS
VDD
Voltage
Reference RREF
5.000 V VAREF
CAREF
Microcontroller
GND VAGND
Central
Power Analog
Supply Ground
5V VDD
GND VSS
Note: It is not recommended to use a VAREF circuit without an external capacitance CAREF because of the high peak
current in the charge redistribution phase.
VAGND
r+E C AREFSW
C AREF ≥ 2 ⋅ -----------------------
2
with:
Note: The maximum voltage error (ErrorAREF) at VAREF caused by CAREF is referenced to the allowed maximum
input voltage at ANx (VAINx = VAREF). For input voltages at ANx smaller than VAREF the additional in-accuracy
at VAINx is proportionally less than the value of ErrorAREF used in the example calculations. The real additional
inaccuracy at VAINx is:
ErrorAREF_real = (VAINx / VAREF) * ErrorAREF with the condition: VAGND ≤ VAINx ≤ VAREF
Table 8 shows the minimum CAREF values required for different values of A/D converter resolution, and the
maximum allowed ERRORAREF at the reference voltage input VAREF.
The condition (CAREF ≥ 2r+E * CAREFSW / 2) allows a free choice of the A/D converter clock, but the cycle time tCYCLE
has a direct influence on the accuracy of the conversion. The cycle time (total conversion time) has to be long
enough to recharge the external capacitance CAREF before the next charge-redistribution phase is started.
The external capacitance CAREF has to be charged from the voltage reference. The minimum current, which is
drawn from the voltage reference, is based on the charge that is necessary for a complete conversion. The charge
QCONV for a complete charge-redistribution phase and a calibration phase is:
(16)
The current for the voltage reference depends on the minimum cycle time for a total conversion:
(17)
Q CONV
I AREF = ------------------
t CYCLE
The external resistance RREF between the voltage reference VRF and the input VAREF of the A/D converter has a
significant influence on the accuracy.
Note: This resistor should be as small as possible because the continuous current IAREF causes a voltage drop
VERROR between the voltage reference VRF and the reference voltage input VAREF of the A/D converter (See
Figure 26).
(18)
The value for the external capacitance between VAREF and VAGND is:
Note: A typical recommendation for the value of the external capacitance is CAREF = 220 nF.
Using some µF, external capacitance CAREF can significantly suppress noise on VAREF and increase total
accuracy.
Assuming VAREF = VRF, the minimum continuous current which has to be supplied by the voltage reference is:
The maximum allowed value for the resistor RREF between voltage reference VRF and input VAREF of the A/D
converter is:
Note: In an overload condition it is possible that RREF has to be increased, to limit the overload current to the
specified values. If the value of RREF exceeds the error limit of the system, an external diode between VAREF
and VDD can reduce the overload current (See Figure 25 “External Voltage Reference” on Page 41).
Note: Depending on the implementation, in the best case there should be one input pin VAREF per A/D converter.
Some microcontrollers however may only have one VAREF pin for several different A/D converters because
of the pin limitations of the package being used. In this instance the external circuitry at pin VAREF has to be
selected after considering and summing up all individual A/D converter requirements.
Voltage
Reference VDD
Analog RREF
Source
VAREF
CAREF
VAGND Microcontroller
Central Analog Ground
ANx
Power
Supply
5V VDD
GND VSS
Central Digital Ground
Analog VDD
Source
Microcontroller
IOZx IOV>0
ANx
MUX
RASRC IOV<0 IOZx
VLEAK
V0 VSS VSS
Figure 28 A/D Converter Input with ESD Structure and Leakage Source
Note: The ESD structure of the reference voltage VAREF and of the reference ground VAGND is the same as shown
in Figure 28.
The leakage voltage VLEAK can cause an additional un-adjusted error AUELEAK.
(20)
V LEAK
AUE LEAK = -----------------
1LSBr
Note: The Input Leakage Current can significantly reduce the total A/D conversion accuracy when the resistance
of the analog source RASC has a high value.
Notes
1. The symbol for the overload current (also called injection current) used in the relevant microcontroller Data
Sheet is in most cases IOV.
2. The specified value of the A/D converter overload current depends on the device type. Please refer to the
appropriate Data Sheet for the exact value.
3. The overload current has to be taken into account for the calculation of external resistors which protect the
microcontroller inputs. These external resistors guarantee that, in case of a system error, the specified
maximum value of the overload current will not be exceeded. The calculation also has to consider the specified
absolute sum of input overload currents on all port pins or a pin group of the microcontroller, and especially
the specified absolute sum of the A/D converter input.
To calculate the minimum value for the external resistor RP to protect an analog input pin for a short time overload
condition:
VDD = 4.5 V Minimum system supply voltage during operating conditions (worst
case)
VErr_max = 14 V Maximum voltage of the analog signal in case of a fatal system error
IOV_max = |±3 mA| Maximum of the overload current during operating conditions
To calculate the minimum value of the external resistor RP to protect an analog input of the microcontroller and
ensure correct operation:
Note: Overload current must be drained via ESD to VDD line, otherwise VDD could be charged up to 14V.
The additional error current IINJ distorts the analog input voltage VAINX because of the additional voltage VLEAK at
RASRC. Details are shown in the following figure.
ANx+/-1
Microcontroller
Analog
Source
RASRC IOV<0
VAINx
VLEAK IOZ
CEXT
V0 VSS VSS
Figure 29 Relationship between Overload Current, Leakage Current and the Coupling Factor
Note: Details of the Overload Current, Leakage Current and Coupling Factor are described in the appropriate Data
Sheet for each particular device.
To calculate the total leakage current:
VSS
Microcontroller
CAP
CAP
VDD
Via connection
to V DD
VDDP
Via connection to V DDP
Abbreviations
10 Abbreviations
Abbreviation used in this document with an associated explanation.
Table 9 Abbreviations
Abbreviation Explanation
ADC Analog Digital Converter
ANx Analog input x
AUELeak Additional unadjusted error caused by the leakage current
CAINSW A/D converter switched input capacitance (internal C-net) CAINWS = CAINTOT - CAINP
CAINSW_max Maximum value of the A/D converter switched input capacitance
CAINP A/D converter input pad capacitance
CAINTOT A/D converter input pad total capacitance
CAREF External capacitance connected to the reference voltage input VAREF
CAREFP A/D converter input pad capacitance at VAREF
CAREFSW A/D converter switched reference capacitance. CAREFWS = CAREFTOT - CAREFP
CAREFTOT A/D converter total input pad capacitance at VAREF
CEXT External capacitance connected to the analog input
C-Net Internal A/D converter capacitor network.
C 9 - C0 C-net for conversion (10-bit resolution).
C7’ - C0’ C-net for calibration.
chn Analog channel n
DNLE Differential nonlinearity error
E Variable for allowed Error to calculate CAREF
ErrorAINx Maximum voltage difference between V0 and VANx at the end of the sample time
ErrorAREF Maximum voltage error at VAREF caused by CAREF
ESD Electrostatic discharge
fCPU CPU frequency
fC Cutoff frequency
fCYCLE Cycle frequency of sample events (fCYCLE = 1 / tCYCLEn)
fCYCLEn Cycle frequency of sample events at channel n
INLE Integral nonlinearity error
IAREF Current of the voltage reference
IINJ Error current which is injected by an overload current to the direct adjacent pins
IOV Overload current
IOV_max Specified maximum rating of the overload current or Specified maximum of the
overload current during operating conditions
IOZTOT Total input leakage current including Error current caused by overload current at
adjacent pin
IOZTOT_MAX Maximum total input leakage current
IOZx Input leakage current
KOVA Analog overload coupling factor
Abbreviations
Table 9 Abbreviations
Abbreviation Explanation
KOVAN Analog overload coupling factor for negative overload current
KOVAP Analog overload coupling factor for positive overload current
LSB Least significant bit (general)
LSBr Least significant bit referred to r-bit resolution (LSBr = VAREF / 2r)
MSB Most significant bit
r Resolution of the A/D converter
RAIN Internal series resistance of the A/D converter
RASRC Internal resistance of the analog source
RREF Resistance between voltage reference and VAREF input
RAREF_EXT Internal resistance of the voltage reference
RP External resistor RP to protect an analog input in case of an overload condition
RP_min Minimum value for the external resistor RP
RON Simulation: Sample switch RON resistance
tC Conversion time
tCn Conversion time of analog channel n
tCYCLE Cycle time
tCYCLEn Cycle time of analog channel n
tS Sample time
t1, t2, t3 Time constants for the different phases of a conversion
TUE Total unadjusted error
VAREF Reference voltage input for the A/D converter
VAGND Reference ground for the A/D converter
VANx Voltage at the analog input ANx
VCAINSW Voltage at the internal C-net
VC (t) Charge curve of CEXT for a total cycle
VC (tCYCLE) Voltage of CEXT at the end of a total cycle
VDD Supply voltage
VERROR Voltage at RREF
VERR_max Maximum voltage of an analog signal in case of a fatal system error
VLeak Leakage voltage at RASRC
VLSB_12 Simulation: Limitvoltage for the simulation plot (VLSB_12 = V0 - 1LSB12)
VPRECHARGE Precharge voltage of the internal C-Net at start of sample time
VR Missing rest voltage of VAINx at the end of a conversion cycle
VRF Voltage reference
VSS Digital GND
VS(t) Voltage curve during sample time
VS(tS) Voltage at the end of sample time
Abbreviations
Table 9 Abbreviations
Abbreviation Explanation
V0 Voltage of the analog source
V∆ Voltage drop at the beginning of the sample time