Ug Altera Phylite-683716-813924

PHY Lite for Parallel Interfaces
Intel® FPGA IP User Guide

Updated for Quartus® Prime Design Suite: 24.1
Online Version 683716

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Contents
Contents
1. About the PHY Lite for Parallel Interfaces IP ................................................................. 5

1.1. Device Family Support............................................................................................5
1.2. Features...............................................................................................................6
2. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-Series Devices................... 7
2.1. Release Information...............................................................................................7
2.2. Functional Description............................................................................................ 7
2.2.1. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-Series Devices
Top Level Interfaces................................................................................... 8
2.2.2. Dynamic Reconfiguration.......................................................................... 17
2.3. Getting Started....................................................................................................22
2.3.1. Parameter Settings.................................................................................. 24
2.3.2. Signals................................................................................................... 26
2.4. I/O Standards..................................................................................................... 29
2.4.1. Design Guidelines.................................................................................... 30
2.5. Design Example...................................................................................................45
2.5.1. Generate the Design Example....................................................................45
2.5.2. Verify Simulation Design Examples using Tester IP....................................... 51
3. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 M-Series Devices................ 57
3.1. Release Information............................................................................................. 57
3.2. Functional Description.......................................................................................... 57
3.2.1. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 M-Series Devices
Top Level Interfaces................................................................................. 58
3.2.2. Dynamic Reconfiguration.......................................................................... 66
3.2.3. I/O Timing.............................................................................................. 70
3.3. Getting Started....................................................................................................71
3.3.1. Parameter Settings.................................................................................. 71
3.3.2. Signals................................................................................................... 74
3.4. I/O Standards..................................................................................................... 77
3.4.1. Design Guidelines.................................................................................... 78
3.5. Design Example...................................................................................................80
3.5.1. Generating the Design Example................................................................. 80
3.5.2. Verifying Simulation Design Examples using Tester IP................................... 84
4. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-Series
Devices.................................................................................................................... 86
4.1. Release Information............................................................................................. 86
4.2. Functional Description.......................................................................................... 86
4.2.1. Agilex 7 F-Series and I-Series I/O Sub-bank Interconnects............................ 88
4.2.2. Agilex 7 F-Series and I-Series Input DQS/Strobe Tree................................... 98
4.2.3. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-
Series Devices Top Level Interfaces.......................................................... 100
4.2.4. Dynamic Reconfiguration.........................................................................105
4.2.5. I/O Timing............................................................................................ 113
4.3. Getting Started..................................................................................................113
4.3.1. Parameter Settings.................................................................................114
4.3.2. Signals................................................................................................. 118
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4.4. I/O Standards....................................................................................................120

4.4.1. Input Buffer Reference Voltage (VREF)...................................................... 120
4.4.2. On-Chip Termination (OCT)..................................................................... 121
4.5. Design Guidelines.............................................................................................. 123
4.5.1. Guidelines: Group Pin Placement.............................................................. 123
4.5.2. Reference Clock..................................................................................... 125
4.5.3. Reset....................................................................................................125
4.6. Design Example................................................................................................. 126
4.6.1. Generating the Design Example............................................................... 126
5. PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 Devices.......................... 132
5.1. Release Information........................................................................................... 132
5.2. Functional Description.........................................................................................132
5.2.1. Top Level Interfaces............................................................................... 134
5.2.2. Clocks.................................................................................................. 134
5.2.3. Output Path...........................................................................................135
5.2.4. Input Path.............................................................................................138
5.3. Getting Started..................................................................................................160
5.3.2. Signals................................................................................................. 169
5.4. I/O Standards....................................................................................................173
5.5.2. Reference Clock..................................................................................... 180
5.5.3. Reset....................................................................................................180
5.5.4. Constraining Multiple PHY Lite for Parallel Interfaces Intel FPGA IP to One
I/O Bank............................................................................................... 181
5.5.6. Timing.................................................................................................. 181
5.6. Design Example................................................................................................. 189
6. PHY Lite for Parallel Interfaces Intel FPGA IP for Arria 10 and Cyclone 10 GX
Devices.................................................................................................................. 196
6.1. Release Information........................................................................................... 196
6.2. Functional Description.........................................................................................197
6.2.1. Top Level Interfaces............................................................................... 198
6.2.2. Clocks.................................................................................................. 200
6.2.3. Output Path...........................................................................................202
6.2.4. Input Path.............................................................................................204
6.3. Getting Started..................................................................................................225
6.3.2. Signals................................................................................................. 233
6.4. I/O Standards....................................................................................................238
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Contents
6.5.2. Reference Clock..................................................................................... 246

6.5.3. Reset....................................................................................................247
6.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank............247
6.5.6. Timing.................................................................................................. 247
6.6. Design Example................................................................................................. 255
6.7. Application Specific Design Example..................................................................... 269
6.7.1. Implementation using the PHY Lite for Parallel Interfaces Intel FPGA IP......... 270
7. PHY Lite for Parallel Interfaces Intel FPGA IP User Guide Document Archives............274
8. Document Revision History for the PHY Lite for Parallel Interfaces Intel FPGA IP
User Guide ............................................................................................................ 275
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1. About the PHY Lite for Parallel Interfaces IP

This user guide describes the following IPs:
• PHY Lite for Parallel Interfaces Agilex™ 5 FPGA IP (E-Series)
• PHY Lite for Parallel Interfaces Agilex 7 FPGA IP (M-Series)
• PHY Lite for Parallel Interfaces Agilex 7 FPGA IP (F-Series and I-Series)
• PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP
• PHY Lite for Parallel Interfaces Arria® 10 FPGA IP
• PHY Lite for Parallel Interfaces Cyclone® 10 GX FPGA IP
You can primarily use the PHY Lite for Parallel Interfaces IPs for building custom
memory interface PHY blocks. You can use this solution to interface with protocols
such as DDR2, LPDDR2, LPDDR, TCAM, Flash, ONFI (synchronous mode), and mobile
DDR. The PHY Lite for Parallel Interfaces Intel® FPGA IP is suitable for simple parallel
interfaces.
The IPs have a dedicated PHY clock tree in each I/O bank. The PHY clock tree is short
that yields lower jitter and duty cycle distortion (DCD), enabling designs to achieve
higher performance. This IP controls the strobe-based capture I/O elements. Each
instance of the IP can support interfaces of data/strobe capture groups.
In addition, this IP supports the Dynamic Reconfiguration feature, which enables

reconfiguration of the data and strobe delays. You can align the data and strobe
through calibration to achieve timing closure at high frequencies.
Related Information
PHY Lite for Parallel Interfaces Intel FPGA IP User Guide Document Archives on page
274
Provides a list of user guides for previous versions of the PHY Lite for Parallel
Interfaces Intel FPGA IP core.
1.1. Device Family Support

The PHY Lite for Parallel Interfaces Intel FPGA IPs support the following devices:
• Agilex 5 (E-Series)
• Agilex 7 (F-Series, I-Series, and M-Series)
• Stratix 10
• Arria 10
• Cyclone 10 GX
For Arria V, Cyclone V, and Stratix V devices, use the ALTDQ_DQS2(1) Intel FPGA IP
instead.
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any ISO
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the 9001:2015
application or use of any information, product, or service described herein except as expressly agreed to in Registered
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
1. About the PHY Lite for Parallel Interfaces IP
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Related Information
ALTDQ_DQS2 IP Core User Guide
Provides more information about the ALTDQ_DQS2 IP.
1.2. Features
Features of the PHY Lite for Parallel Interfaces Intel FPGA IPs:
• Support interface frequency range of 150 MHz to 1250 MHz (for Agilex 5 and
Agilex 7 M-Series and devices) or 100 MHz to 1200 MHz (for Agilex 7 F-Series,
Agilex 7 I-Series, and older devices).
• Support input, output, and bidirectional data channels.
• Support the DQS gating and ungating circuitry for strobe-based interfaces.
• Support output delays through interpolator.
• Support dynamic on-chip termination (OCT) control.
• Support quarter-rate, half-rate, and full-rate mode of the interface clock
conversions.
• Support input, output, and read enable, strobe enable, and OCT enable paths.
• Support single and double data rates (SDR and DDR) at the I/Os.
• Support the PHY clock tree.
• Support dynamically reconfigurable delay chains using the Avalon® memory-
mapped interface.
• Support process, voltage, and temperature (PVT) or non-PVT compensated input
and DQS delay chains
Note: For Stratix 10, Arria 10, and Cyclone 10 GX devices, you can set the non-
PVT compensated component of the input delay through Quartus Settings
File (.qsf) assignment in the Quartus Prime software.
(1) ALTDQ_DQS is only available in the Quartus® Prime Standard Edition software.
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2. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex

5 E-Series Devices
2.1. Release Information

The Intel FPGA IP versioning scheme is X.Y.Z and this version number can change with
each Quartus Prime software version. A change in:
• X indicates a major revision of the IP. If you update the Quartus Prime software,
you must regenerate the IP.
• Y indicates the IP includes new features. Regenerate your IP to include these new
features.
• Z indicates the IP includes minor changes. Regenerate your IP to include these
changes.
The following table provides the release information of PHY Lite for Parallel Interfaces
Intel FPGA IP for Agilex 5 E-Series.
Table 1. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-Series Release
Information
Item Description
IP Version 5.0.0
Quartus Prime Pro Version 24.1
Release Date 2024.04.01
2.2. Functional Description

The PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-Series devices utilizes
the IO96 I/O banks in Agilex 5 E-Series devices. In general, each IO96 I/O bank has
eight I/O lanes with 12 pins in each lane, providing a total of 96 pins per bank. Each
bank contains pins that you can use for data and pins that are reserved for single-
ended or differential strobe, reference clock, and RZQ. Some Agilex 5 E-Series
packages may have partially bonded out I/O banks. The PHY Lite IP can still be used
in these partially bonded out I/O banks, but with fewer than 96 pins available. For
details about supported I/O banks, refer to the Agilex 5 E-Series Device Handbook.
The following figure shows the Agilex 5 E-Series HSIO Bank Structure (Die Top View).
2. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-Series Devices
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Figure 1. Agilex 5 HSIO Bank Structure (Die Top View)

This figure shows the HSIO bank structure of the Agilex 5 device. The figure shows the view of the die as
shown in the Quartus Prime Chip Planner. In the Pin Planner, this corresponds to the "Bottom View".
Different device packages have different number of HSIO banks. Refer to the device pin-out files for available
HSIO banks and the locations of the HPS shared HSIO banks for each device package.
HPS I/O Bank HPS Shared GPIO-B Bank
SDM I/O Bank HSIO Bank
Top Index Sub-Bank Bottom Index Sub-Bank

Index: #48-#95 Index: #0-47
HPS 3A 3B
Top I/O Bank Row

I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane
Bottom I/O Bank Row
2A 2B Top Index Bottom Index

SDM
I/O PLL I/O PLL
HMC Clock Fabric HMC

SERDES & DPA OCT
Wide Network PLL Slim
Differential I/O Buffer Pair I/O Center
2.2.1. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-Series
Devices Top Level Interfaces
For E-Series devices, the PHY Lite for Parallel Interfaces Intel FPGA IP consists of four
top level RTL modules:
• Clocks and reset (phylite_clocking)— includes PLL and clock phase alignment
(CPA) circuitries.
• Fabric (phylite_c2p_p2c_mapping)— maps connections between PHY Lite top-
level ports and IO96 ports.
• PHY data and control (phylite_lane)— includes core-to-periphery (C2P) and
periphery-to-core (P2C) fabric adaptor (FA), PHY adaptor, Byte and Byte control.
Each PHY Lite group corresponds to either one or two lanes. Depending on the
configuration, one PHY Lite instance can have up to eight groups of single lane
each or four groups of double lane each.
• I/O (phylite_iobufs)— includes input and output buffers.
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Figure 2. Top Level Diagram of the PHY Lite for Parallel Interfaces IP for E-Series
Devices
phylite_top
phylite_clocking
IOPLL CPA
phylite_iobufs
phylite_lane (up to 8)
User Interface Output I/O Interface
Buffer
phylite_c2p_p2c_mapping C2P (per output
Fabric BYTE pin)
Adaptor PHY
Connection Mapping Adaptor Input
P2C Buffer
Fabric BYTE (per input
Adaptor Control pin)
2.2.1.1. Clocks
The PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-Series sources an
external reference clock from a dedicated clock pin to the PLL inside the IP. This PLL
provides four clock domains for the output and input paths.
Table 2. Clock Domains of the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex
5 E-Series
Clock Domain Description
Interface clock This is the clock frequency of the external device connected to the FPGA I/Os.
VCO clock The PLL generates this clock internally. The input and output paths use the VCO
clock to generate interpolator delays that compensates for PVT variations.
PHY clock The IP uses this clock internally for PHY circuitry.
Core clock The IP generates this clock internally and uses it for all transfers between the
FPGA core fabric and I/O banks. The clock phase alignment (CPA) circuitry keeps
the clock in phase with the PHY clock for transfers between the core and the
periphery.
The clock frequency of user logic and other clocks are derived from the interface clock
frequency based on predetermined PHYLITE_IN_RATE and PHYLITE_OUT_RATE
parameters as shown in the following equation and are summarized in the following
table. The calculated core clock frequency is fixed based on the selected interface
clock frequency and displayed in the IP parameter editor as a grayed-out value as
shown in the following figure.
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Equation 1. Relationships Between Clock Domains

These equations describe the relationships between the clock domains available in the PHY Lite for Parallel
Interfaces Intel FPGA IP for Agilex 5 E-Series.
Core Clock Frequency = Interface Clock Frequency÷PHYLITE_IN_RATE

VCO Clock Frequency = Interface Clock Frequency×PHYLITE_OUT_RATE
Where: PHYLITE_IN_RATE = Core Clock Rate
PHYLITE_OUT_RATE = VCO Frequency Multiplier Factor
Table 3. Interface Frequencies Supported by the PHY Lite for Parallel Interfaces Intel
FPGA IP for Agilex 5 E-Series Devices
Interface PHYLITE_IN_RATE PHYLITE_OUT_RATE VCO Clock PHY Clock Core Clock
Frequency (Core Clock Rate) (VCO Frequency Frequency Frequency Frequency
(MHz) Multiplier Factor) (MHz) (MHz) (MHz)
600-1250 4 1 600-1250 300-625 150-312.5
300-600 2 2 600-1200 300-600 150-300
150-300 1 4 600-1200 300-600 150-300
Note: • For the boundary frequencies of 300 MHz, PHYLITE_IN_RATE = 1 and

PHYLITE_OUT_RATE = 4.
• For the boundary frequencies of 600 MHz, PHYLITE_IN_RATE = 2 and
PHYLITE_OUT_RATE = 2.
Figure 3. Clock Settings in the IP Parameter Editor of PHY Lite for Parallel Interfaces
Intel FPGA IP for Agilex 5 E-Series Devices
2.2.1.2. Output Path
The simplified output path consists of pipeline registers, TX FIFO, shift register, and
phase shift blocks. The following figure shows strobe and data coming from the core,
together with the related enable signals, go through the pipeline stages before the TX
FIFO.
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Figure 4. Simplified Output Path

This figure shows the simplified output path for the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-
Series devices.
Pipeline Phase Shift

group_<n>_data_from_core Registers
group_<n>_data_out/
TX FIFO Phase Shift

Pipeline group_<n>_strobe_out/
Registers group_<n>_strobe_out_n
group_<n>_strobe_from_core
Inherent Delay TxDqDelay
Pipeline Shift Register

Registers
group_<n>_oe_from_core
Pipeline
Shift Register
Registers
group_<n>_strobe_out_en
Table 4. Internal Components of the Simplified Output Path

Component Description
Pipeline Registers Represent pipeline stages in the output path.
TX FIFO Stores the data to be transmitted out.
Shift Register Delays the enable signal at the read side of the TX FIFO at VCO cycle increment.
Phase Shift Delays TX data and strobe at 1/128 of a VCO cycle increments.
There are two types of delay in the output path, namely inherent latency and output
delay, TxDqDelay.
Table 5. Types of Delay in Output Path

Delay Type Description
Inherent latency Static Captured in the pipeline stages from the assertion of the output enable
in the core (group_<n>_oe_from_core[]) until the data go into TX
FIFO.
The parameter Additional Write Latency in the IP Parameter Editor
is added to the inherent latency.
TxDqDelay delay (output Dynamic You can configure this 11-bit wide register in the control registers. The
delay) TxDqDelay register consists of two parts, as described in the next
table. The integer part of the delay uses a shift register to delay the
enable signal that goes to the read side of TX FIFO.
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Table 6. Output Path Reconfigurable Delays

This table describes the reconfigurable output path delay.
Feature Description Min Max
TxDqDelay[10:7] Integer number of VCO clock cycles 0 15
TxDqDelay[6:0] Additional phase shift measured in 1/128 of VCO clock period 0 127
The following figure shows an example of TX data transfer in QR DDR. In this

illustration, the data_from_core signal for each pin is 8 bits wide. To enable one
extra preamble cycle before the data start, the output strobe enable signal,
strobe_out_en, should first transition from 0x0 to 0x8 one core clock cycle before
the output data enable, oe_from_core, transitions to 0xF as shown in the figure.
Setting the Output strobe phase parameter to 90 degrees in the IP Parameter Editor
causes the PHY Lite IP to send the data signal, data_out, center aligned with respect
to the output strobe signal, strobe_out.
Figure 5. Output Operation

This figure shows the output operation for the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-
Series devices.
core_clk
data_from_core ABCDEFGH IJKLMNOP
strobe_from_core 55
oe_from_core 0 F 0
strobe_out_en 8 F 0
data_out HG F E D C B A P O NML K J I
strobe_out
strobe_out_n
= Signals Truncated
Figure 6. Default Output Path Settings

This figure shows the default output path settings in IP Parameter Editor for the PHY Lite for Parallel Interfaces
Intel FPGA IP for Agilex 5 E-Series devices.
The inherent latency in the output path measured from the assertion of output enable
in the core until the data appear in the PHY is presented in the following table. The
GUI parameter Additional Write latency is added to the inherent latency. The
maximum allowed value for this parameter is shown in the third column in the
following table.
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Table 7. Output Path Inherent Latency and Maximum Additional Write Latency
I/O Frequency (MHz) Inherent Latency in the Output Path (# of IO Clock Maximum Additional Write Latency
Cycles)
600 - 1250 27 15
300 - 600 13 7
150 - 300 7 3
2.2.1.3. Input Path
The simplified input path of the IP consists of the pipeline registers, receiver FIFO,
shift registers, and phase shift logics.
Figure 7. Simplified Input Path

This figure shows the input path for the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-Series
devices.
Inherent Delay RxRcvEnPi
Pipeline RcvEn Shift Register Phase Shift

Registers
group_<n>_rdata_en
Pipeline Clock
Registers Shift Register Gate
group_<n>_rdata_valid group_<n>_strobe_in/
group_<n>_strobe_in_n
Per Group read_enable_offset
Per Pin RxDqsNDelayPi/

fifo_read_enable RxDqsPDelayPi
Phase Shift
RX FIFO
Pipeline
Registers
group_<n>_data_to_core group_<n>_data_in
Table 8. Components in the Simplified Input Path of the PHY Lite for Parallel
Interfaces Intel FPGA IP
Pipeline Registers Represent pipeline stages in the input path
2x RX FIFOs Perform 2:1 rate conversion on the RX data

• At positive edge of strobe_in signal
• At negative edge of strobe_in signal
Shift Registers Perform the following functions:

• Delay the RcvEn signal in VCO cycle increments
• The read_enable_offset shift register delays the rdata_valid signal
Phase Shift Logics Perform the following functions:

• Delay RcvEn signal in 1/128 VCO cycle increments
• Delay RxDqsNDelayPi and RxDqsPDelayPi signals
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There are five types of delay in the input path. The following table describes the
reconfigurable input path delays for the PHY Lite for Parallel Interfaces Intel FPGA IP
for Agilex 5 E-Series.
Table 9. Types of Delay in Input Path

Inherent latency Static Captured in pipeline stages from the assertion of

group_<n>_rdata_en signal in core until internal signal,
RcvEn, is asserted.
RcvEn delay (internal signal generated Dynamic You can reconfigure these delays in the control registers.
from input signal rdata_en) You can program the RcvEn delay statically or dynamically
through the Additional Receiver Enable Latency
Positive-edge strobe_in delay settings in the IP Parameter Editor.
Negative-edge strobe_in delay
rdata_valid delay
Table 10. Input Path Reconfigurable Delays Description

This table lists all the reconfigurable input path delays for the PHY Lite for Parallel Interfaces Intel FPGA IP for
Agilex 5 E-Series devices.
Feature Description Bit-field Description Min Max
RxRcvEnPiRank0[10:7 • RcvEn delay Bit 10 to bit 7 0 15

] • There are two RxRcvEnPiRank0 registers per represents integer
lane. One controls the lower nibble (6 pins) number of VCO clock
and the other controls the upper nibble of the cycles to delay RcvEn
lane. signal.
• In PHY Lite IP, the nibbles cannot be used
RxRcvEnPiRank0[6:0] Bit 6 to bit 0 0 127
independently. Both control signals must be represents additional
programmed to the same value.
phase shift in RcvEn
• Changing these delays requires the ODT and signal measured in
SA settings to be adjusted according to 1/128 of VCO clock
Settings for DQ/DQS ODT/SA Delays table. period.
RxDqsNDelayPi[6:0] • strobe_in delay Phase shift in the 0 127

• There are two RxDqsNDelayPi and negative edge of the
DQS for each pin
RxDqsPDelayPi for each pin. Each pin
measured in 1/128 of
receives a copy of the DQS and can phase-shift
VCO clock period.
each edge of the DQS independently of other
pins. Phase shift in the 0 127
RxDqsPDelayPi[6:0]
• Usually both edges should be set to the same positive edge of the
delay value, but different values can be used DQS for each pin
to correct uneven duty cycle. The effective measured in 1/128 of
range of this delay setting is up to 1 VCO clock VCO clock period.
cycle.
read_enable_offset[ • rdata_valid delay Delay before reading 0 15

3:0] • An adjustable setting that changes the delay from the RX FIFO
before starting to read from the RX FIFO, measured in number
effectively delaying the rdata_valid signal. of PHY clock cycles.
• This delay setting is downstream from the
integer portion of the RcvEn delay, so any
additional RcvEn delay applies to the
rdata_valid signal as well. Refer to Allowed
Values for read_enable_offset Based on
RcvEn Coarse Delay for allowed delay values
based on RcvEn delay.
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Figure 8. Input Operation

This figure shows the input operation for the PHY Lite for Parallel Interfaces Agilex 5 E-Series FPGA IP / PHY
Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-Series devices.
core_clk
rdata_en 0 F 0 0
data_in H G F E D C B A P O NM L K J I
strobe_in
strobe_in_n
rdata_valid 0 0 0 F 0
data_to_core ABCDEFGH IJKLMNOP
= Signals Truncated
The preceding figure shows an example of RX data transfer in QR DDR. In this

illustration, the data_to_core output signal to the FPGA fabric for each pin is 8 bits
wide. The PHY Lite IP uses DDR4 preamble settings, expecting one cycle of preamble
by default.
Setting the parameter Capture strobe phaseshift to 90 degrees in the IP Parameter

Editor, as shown in the following figure, causes the PHY Lite IP to accept edge-aligned
input data, data_in, with respect to the input strobe signal, strobe_in.
Figure 9. Default Input Path Settings
The inherent latency in the RcvEn path measured from the assertion of read enable in
the core until the RcvEn signal (internal) is asserted is presented in the following
table. The parameter Additional receiver enable latency is added to the inherent
latency. The maximum allowed value for this parameter is shown in the third column
in the following table.
Table 11. RcvEn Path Inherent Latency and Maximum Additional Rcven Latency
I/O Frequency (MHz) Inherent Latency in the RcvEn Path (# of IO Clock Maximum Additional RcvEn Latency
Cycles)
600 - 1250 27 15
300 - 600 13 7
150 - 300 7 3
To ensure that the IP uses only clock edges associated with valid input data, gate the
receiver off when PHY Lite for Parallel Interfaces IP is not accepting input data. If
there are extra toggling signals or noise on the DQS port, use a refined version of the
received strobe. The gating signal, RcvEn (receiver enable), is derived internally from
the rdata_en signal. Use the RcvEn signal to ungate the DQS gate window by
asserting RcvEn up to one cycle before the first rising edge of DQS, as shown in the
following figure. You require no more than one cycle preamble in the strobe signal.
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Figure 10. Ungating DQS Gate Window

This figure shows the ungating of the DQS window by internally asserting the RcvEn signal.
data_in H G
strobe_in
strobe_in_n
RcvEn to be
Asserted
The process of shutting off the DQS gate happens automatically after the last burst
ends.
In the input path, program the on die termination (ODT) and sense amplifier (SA)
when you dynamically reconfigure the RcvEn delay.
To save power in idle mode, gate off the ODT and SA using two enable signals tapped
from the same shift register as RcvEn.
Whenever you reconfigure the RcvEn delay, reconfigure the following ODT and SA
settings to ensure that all parts of the receiver circuitry turns on at the correct time:
• DqsSenseAmpDelay
• DqsSenseAmpDuration
• DqSenseAmpDuration
• DqSenseAmpDelay
• DqOdtDuration
• DqOdtDelay
• DqsOdtDuration
• DqsOdtDelay
Adjust these settings for both upper and lower nibbles in the lane according to the
following table.
Table 12. Settings for DQ/DQS ODT/SA Delays

This table lists the settings adjustments for both the upper and lower nibbles in the lane.
RxRcvEnPi[10:7]>>Gear4(2) DqsOdtDelay DqOdtDelays Dq/Dqs SenseAmpDelay
0 2 3 3
1 3 4 4
2 4 5 5
3 5 6 6
4 6 7 7
continued...
(2)
This value is the shifted value of RxRcvEnPi[10:7] and Gear4 value is always 1.
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RxRcvEnPi[10:7]>>Gear4(2) DqsOdtDelay DqOdtDelays Dq/Dqs SenseAmpDelay
5 7 8 8
6 8 9 9
7 9 10 10
When changing the RcvEn coarse delay or RxRcvEnPiRank0[10:7], Intel

recommends that you update read_enable_offset to avoid receiving misaligned
data in the core. The small values of read_enable_offset can cause RX FIFO
underflow, while large values may cause an overflow.
Table 13. Allowed Values For read_enable_offset Based on RcvEn Coarse Delay
RxRcvEnPiRank0[10:7] Allowed values for read_enable_offset
0, 1, 4, 5, 8, 9, 12, 13 3, 5, 7, 9, 11
2, 3, 6, 7, 10, 11, 14, 15 4, 6, 8, 10, 12
2.2.2. Dynamic Reconfiguration

If you enable dynamic reconfiguration, you can use an Avalon memory-mapped
interface to reconfigure the input and output delays in the PHY and calibrate the
delays. Through calibration, you can optimize the delay settings to maximize the
capture window. You can access the Avalon memory-mapped interface through the
Calibration Intel FPGA IP. The IP provides an ARM AMBA* AXI4 Lite Interface. You can
connect the Calibration IP to up to two PHY Lite for Parallel Interfaces IP instances in
an I/O bank.
You can only reset the PHY by enabling dynamic reconfiguration and writing to the
TrainReset bit. The reset port in PHY Lite for Parallel Interfaces IP is only for power-up
reset.
Figure 11. Connection of the Calibration IP to the PHY Lite for Parallel Interfaces IP for
Agilex 5 E-Series Devices
AXI-Lite Interface
Calibration IP
AVMM
Interface
Core Interface IO Interface

PHYLite_ph2
(2)
This value is the shifted value of RxRcvEnPi[10:7] and Gear4 value is always 1.
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2.2.2.1. Calibration IP
The Calibration IP provides access to the IOPLL and PHY registers through the AXI4-
Lite IP interface. You can connect the Calibration IP to up to two periphery interfaces
and three PLLs.
Table 14. ARM AMBA* AXI4-Lite IP Interface Signals

This table describes the ARM AMBA* AXI4-Lite IP interface signals.
Signal Name Direction Width Description
fbr_axil_clk Input 1 Clock
fbr_axil_rst_n Input 1 Reset
fbr_axil_awaddr Input 27 Write address
fbr_axil_awvalid Input 1 Write address valid
fbr_axil_awready Output 1 Write address ready
fbr_axil_wdata Input 32 Write data
fbr_axil_wstrb Input 4 Write strobes
fbr_axil_wvalid Input 1 Write valid
fbr_axil_wready Output 1 Write ready
fbr_axil_bresp Output 2 Write response
fbr_axil_bvalid Output 1 Write response valid
fbr_axil_bready Input 1 Response ready
fbr_axil_araddr Input 27 Read address
fbr_axil_arvalid Input 1 Read address valid
fbr_axil_arready Output 1 Read address ready
fbr_axil_rdata Output 32 Read data
fbr_axil_rresp Output 2 Read response
fbr_axil_rvalid Output 1 Read valid
fbr_axil_rready Input 1 Read Ready
fbr_axil_awprot Input 3 Write protection type
fbr_axil_arprot Input 3 Read protection type
2.2.2.2. Dynamic Reconfigurable Delays
The following table lists the delays that can only be reconfigured when the
corresponding read/write path is not being used. For differential data, the output delay
settings should be programmed for both pins in a differential pair. The input settings,
however, should be programmed only for the even pin.
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Table 15. Dynamic Reconfigurable Delays

Configurable Settings Width Description Unit Granularity
TxDqDelay 11 Output delay for data and strobe 1 / 128 of VCO cycle per pin
RxDqsNDelayPi 7 Phase shift in negative edge of DQS 1 / 128 of VCO cycle per pin
RxDqsPDelayPi 7 Phase shift in positive edge of DQS 1 / 128 of VCO cycle per pin
RxRcvEnPiRank0 11 RcvEn delay 1 / 128 of VCO cycle per nibble
DqsSenseAmpDelay 5 DQS sense amplifier delay PHY clock cycle per nibble
DqSenseAmpDuration 4 DQ sense amplifier duration PHY clock cycle per nibble
DqSenseAmpDelay 5 DQ sense amplifier delay PHY clock cycle per nibble
DqOdtDuration 4 DQ ODT duration PHY clock cycle per nibble
DqOdtDelay 5 DQ ODT delay PHY clock cycle per nibble
DqsOdtDuration 4 DQS ODT duration PHY clock cycle per nibble
DqsOdtDelay 5 DQS ODT delay PHY clock cycle per nibble
DqsSenseAmpDuration 4 DQS sense amplifier duration PHY clock cycle per nibble
read_enable_offset 4 Delay before reading from the RX FIFO PHY clock cycle per lane
RxDataVrefL 9 IO reference voltage lower nibble 1 / 512 of VCCN per nibble
RxDataVrefU 9 IO reference voltage upper nibble 1 / 512 of VCCN per nibble
TrainReset 1 Reset the training to clear non-permanent states — per lane

- self clearing
RLTrainingMode 1 Enables read leveling training mode — per lane
DataTrainFeedback_N0 12 Provides feedback for different training steps. — per nibble

In RL Training mode it is simply a counter.
2.2.2.3. Register Map
When you generate the IP, the IP automatically creates the address register map file
(addr_map.vh) and the corresponding C header file. It contains the Avalon memory-
mapped interface registers that you can read and write to use the AXI4-Lite IP
interface of the Calibration IP.
Since these registers include multiple fields for different settings, only change with a
read-modify-write cycle to ensure that other fields in the register remain intact. The
address of a register is 24 bits, consisting of an 11-bit base address right padded with
13’b0, and a 13-bit offset address left-padded with 11’b0. The padding is done to
make the base address and offset address 24 bits.
The 11-bit base address is configured as:
Base address = {3’b011, 3-bit instance ID, 2-bit atom ID, 3-bit lane ID},
where atom ID is 2’b00 for Byte control. All the reconfigurable PHY Lite for Parallel
Interfaces Intel FPGA IP for Agilex 5 E-Series settings are in Byte control, i.e., 2’b00.
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The offset address for different registers in the address map, as well as bit-field
description of the registers, are provided in AXI4-Lite IP Interface Signals table. The
Avalon memory-mapped interface registers are 32-bit wide, but AXI4-Lite IP Interface
Signals only shows the relevant bit-fields in the registers as they appear in the
automatic generated address map.
As an example, suppose that the PHY Lite for Parallel Interfaces Intel FPGA IP for
Agilex 5 E-Series Instance ID is 0 and group 0 is assigned to lane 0. To change the
output delay of pin 0, you need to modify the
INSTANCE_0_GROUP_0_PIN_00_DDRCRTIMINGCONTROL register.
The base and offset addresses are derived as:
Base address = {3’b011, 3’b000, 2’b00, 3’b000, 13’b0} = 24'h60_0000
Offset address = {11’b0, 0x100} = 24'h00_0100
Full address = Base address + Offset address = 24’h60_0100
Before adjusting any delays with dynamic reconfiguration, set the InternalClocksOn
and reset the training. After calibration, reset InternalClocksOn to zero to save power.
Follow these steps:
1. Set InternalClocksOn=1
2. Reset the training by setting TrainReset from 0 to 1 and back to 0.
3. Perform calibration.
4. Set InternalClocksOn=0.
Table 16. Address Register Map

Register name Offset address Description Bit-field Bit-field Description
(11 bits)
INSTANCE_<n>_GROUP_<n>_PIN 0x100 DQ and DQS [31:21] TxDqDelay

_00_DDRCRTIMINGCONTROL timing
INSTANCE_<n>_GROUP_<n>_PIN 0xfc
_01_DDRCRTIMINGCONTROL
INSTANCE_<n>_GROUP_<n>_PIN 0xf8
INSTANCE_<n>_GROUP_<n>_PIN 0xf4
INSTANCE_<n>_GROUP_<n>_PIN 0xf0 [13:7] RxDqsNDelayPi

INSTANCE_<n>_GROUP_<n>_PIN 0xec
INSTANCE_<n>_GROUP_<n>_PIN 0xe8
INSTANCE_<n>_GROUP_<n>_PIN 0xe4
INSTANCE_<n>_GROUP_<n>_PIN 0xe0 [6:0] RxDqsPDelayPi

continued...
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(11 bits)
INSTANCE_<n>_GROUP_<n>_PIN 0xdc
INSTANCE_<n>_GROUP_<n>_PIN 0xd8
INSTANCE_<n>_GROUP_<n>_PIN 0xd4
INSTANCE_<n>_PHY_LANE_<n>_ 0x114 RcvEn delay [10:0] RxRcvEnPiRank0

UPPER_NIBBLE_RCVEN for upper
nibble
INSTANCE_<n>_PHY_LANE_<n>_ 0x11c RcvEn delay [10:0] RxRcvEnPiRank0

LOWER_NIBBLE_RCVEN for lower
nibble
INSTANCE_<n>_PHY_LANE_<n>_ 0x10c DQ/DQS ODT, [31:27] DqsSenseAmpDelay

UPPER_NIBBLE_DATACONTROL2 DQ sense amp
delay and [26:23] DqSenseAmpDuration
duration upper
nibble [22:18] DqSenseAmpDelay
[17:14] DqOdtDuration
[13:9] DqOdtDelay
[8:5] DqsOdtDuration
[4:0] DqsOdtDelay
INSTANCE_<n>_PHY_LANE_<n>_ 0x110 DQ/DQS ODT, [31:27] DqsSenseAmpDelay

LOWER_NIBBLE_DATACONTROL2 DQ sense amp
duration lower
[13:9] DqOdtDelay
[4:0] DqsOdtDelay
INSTANCE_<n>_PHY_LANE_<n>_ 0x124 DQS sense [29:26] DqsSenseAmpDuration

UPPER_NIBBLE_DQSSENSEAMPDU amp duration
RATION upper nibble
INSTANCE_<n>_PHY_LANE_<n>_ 0x128 ovrd_val for [31] rx_ana_ovrd_val

LOWER_NIBBLE_DQSSENSEAMPDU RX path
RATION
ovrd_en for [30] rx_ana_ovrd_en
RX path
DQS sense [29:26] DqsSenseAmpDuration

amp duration
lower nibble
INSTANCE_<n>_PHY_LANE_<n>_ 0x13c Read enable [3:0] read_enable_offset

RXFIFO offset change
read valid
delay
INSTANCE_<n>_PHY_LANE_<n>_ 0x160 Train reset [14] TrainReset

DATATRAINFEEDBACK and training
mode [9] RLTrainingMode
continued...
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(11 bits)
INSTANCE_<n>_PHY_LANE_<n>_ 0x1f4 Train feedback [23:12] DataTrainFeedback_N1

TRAINFEEDBACK
[11:0] DataTrainFeedback_N0
INSTANCE_<n>_PHY_LANE_<n>_ 0x104 Internal [11] InternalClocksOn

DATACONTROL0 Clocks
INSTANCE_<n>_PHY_LANE_<n>_ 0x130 Vref IO [29:21] RxDataVrefL

DATACONTROL6 Voltage
[20:12] RxDataVrefU
2.3. Getting Started

You can instantiate the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-
Series devices from IP Catalog in the Quartus Prime software. Intel provides an
integrated parameter editor that allows you to customize this IP to support a wide
variety of applications. The IP generation can be invoked from both the GUI and
command line.
In IP Catalog, you can search the PHY Lite IP from, Libraries > Basic Function >
I/O as shown in the following figure.
Figure 12. PHY Lite for Parallel Interfaces Intel FPGA IP in IP Catalog
This figure shows Invoking PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-Series devices.
Selecting PHY Lite for Parallel Interfaces Intel FPGA IP launches the IP Parameter
Editor as shown in the succeeding figure.
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Figure 13. IP Parameter Editor

This figure shows the IP Parameter Editor for PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-Series
devices.
The IP parameters can be set from the IP Parameter Editor. The grayed-out
parameters are computed automatically. The parameters with an adjacent checkbox
can either be set automatically or manually. For example, in the preceding figure, if
the checkbox Use recommended PLL reference clock frequency is selected, the
parameter PLL reference clock frequency is grayed out and its value is computed
automatically. Unchecking the checkbox enables selecting other values for this
parameter. After parameterizing, users can select Generate HDL or Generate
Example Design.
Alternatively, the IP GUI can be invoked with the following command:

qsys-edit <IP name>.ip --new-component-type=phylite_ph2 --family=”Agilex 5”
--part=<part_name>
For example:
qsys-edit new.ip --new-component-type=phylite_ph2 --family=”Agilex 5”
--part=A5EC065BB32AE5S
Using ip-deploy command, the default value for a few of the parameters can be
changed:
ip-deploy --family="Agilex 5" --part=" A5EC065BB32AE5SR0" --output-name="dut"
--component-name="phylite_ph2"
--component-param="GUI_PHYLITE_MEM_CLK_FREQ_MHZ=800.0"
--component-param="BYTE_IO_STANDARD=IO_STANDARD_IOSTD_POD12"
--component-param="GUI_GROUP_0_PIN_TYPE=INPUT"
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2.3.1. Parameter Settings

The following table provides the parameter settings for PHY Lite for Parallel Interfaces
Intel FPGA IP for Agilex 5 E-Series.
Table 17. Parameter Settings

Parameter Values Default Value Description
Parameter
Number of groups 1 to 8 1 Number of data and strobe groups in the

interface. The value is set to 1 by default.
I/O Instance ID 0-7 0 Use to assign different base addresses to two

instances in the same bank.
General Tab- these parameters are set on a per interface basis
Clocks
Interface clock frequency 150 MHz – 1250 533 MHz External interface clock frequency.
MHz
Use recommended PLL On, Off On Turn on to calculate the PLL reference clock
reference clock frequency frequency automatically for the best performance.
Turn off to specify your own PLL reference clock
frequency.
PLL reference clock Dependent on 266.5 MHz PLL reference clock frequency. Feed a clock of this
frequency interface clock frequency to the PLL reference clock input of the
frequency memory interface.
Select the desired PLL reference clock frequency.
The values available depend on the interface clock
frequency or the user clock rate logic.
VCO clock frequency Calculated 1066.5 MHz The PLL calculates the VCO clock frequency
internally by PLL automatically based on the interface clock and the
core clock rate.
Core clock frequency Calculated 266.5 MHz The PLL calculates the core clock frequency
internally by PLL automatically based on clock rate of user logic.
Dynamic Reconfiguration
Use dynamic On, Off Off Enables an Avalon memory-mapped interface that
reconfiguration allows you to dynamically reconfigure the PHY Lite
for Parallel Interfaces IP settings.
I/O Settings
I/O standard SSTL-12 SSTL-12 Specifies the I/O standard of the interface's
1.2-V POD strobe and data pins written.
1.1-V POD
1.2-V HSTL
1.2-V HSUL
1.1-V LVSTL
1.05-V LVSTL
Reference clock I/O Single-ended, Single-ended Specifies the reference clock I/O configuration.
configuration True Differential
with on-chip
termination,
True Differential
without on-chip
termination
Group<x> - these parameters are set on a per group basis

continued...
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Group<x> Pin Settings
Pin type Input, Output, Bidirectional Direction of data pins.

Bidirectional
Pin width 1 to 22 8 Number of pins in this data/strobe group. The pin

width includes the number of strobe pins.
DDR/SDR DDR/SDR DDR Double/single data rate.
Data Configuration Single ended, Single ended Selects the type of data.
Differential
Group<x> Input Path Settings
Additional receiver enable 0 to 15 0 The number of external interface clock cycles to

latency delay the internal receiver enable signal in
addition to the inherent latency in the receiver
enable path. The valid range depends on the user
clock rate and memory interface frequency set in
the General tab.
Capture strobe phase 0, 45, 90 90 Internally phase-shift the input strobe relative to
shift the input data.
Group<x> Output Path Settings
Additional Write latency 0 to 15 0 The number of external interface clock cycles to

delay the output data in addition to the inherent
write latency. The valid range is the set of sub
core clock cycles, which is dependent on the user
clock rate set in the General tab. To delay by a
larger amount, register the data in the core.
Output strobe phase 0, 45, 90, 135, 90 Phase shift of the output strobe relative to th
180 output data.
Group<x> General Strobe Settings

Note: These parameters are disabled when Copy parameters from another group is enabled.
Strobe configuration Differential, Differential Selects the type of strobe.

Single ended Refer to the I/O Standards table for a list of
supported I/O standards.
Group<x> OCT Settings
Use Default OCT Values On, Off On Use default OCT values based on the I/O
standard parameter setting.
Input OCT Value 40 ohm with 60 ohm with Specifies the group's data and strobe input
calibration, calibration termination values.
50 ohm with Disable the Use Default OCT Values parameter
calibration, to select the desired input OCT value.
50 ohm without
calibration,
60 ohm with
calibration
Output OCT Value 34 ohm with 40 ohm with Specifies the group's data and strobe output
34 ohm without Disable the Use Default OCT Values parameter
calibration, to select the desired output OCT value.
40 ohm with
calibration,
40 ohm without
calibration
continued...
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Pin Placement
RZQ index 38, 62 38 Specifies the RZQ pin index in the I/O bank. It
should be reserved at pin 38 or pin 62.
Enable manual location of On, Off Off By default, all the data pins are placed in an
data pins ordered-dense format i.e., no gap pins. Enable
this option if data pins are required to be spaced
out, i.e., with gap-pins. Adhere to all restrictions
in the user guide.
Pin Placement Settings Comma separated — Provides a CSV list of pin locations one per each
values data pin. For example, a value of 0, 1, 8, 9 places
data[0], data[1], data[2], data[3] on pin0, pin1,
pin8, pin9 of IO48 Tile respectively, leaving pin
2-7 not used for data. These unused pins may be
used for PLL reference clocks, RZQ pin or strobes
(subject to the constraints mentioned in the user
guide).
Related Information
• I/O Standards on page 29
For more information about the supported I/O standards in Agilex 5 E-Series
devices.
• Pin Placement Restrictions on page 30
For guidelines on pin placement in Agilex 5 E-Series devices.
• Table 7 on page 13
For more information about the IP write latency values.
For more information about the IP read latency values.
• Maximum Number of DQ Data Pin Configurations on page 32
For example configurations to accommodate the maximum number of DQ data
pins.
2.3.2. Signals
2.3.2.1. Clock and Reset Interface Signals
The following table provides the clock and reset interface signals in PHY Lite for
Parallel Interfaces Intel FPGA IP for Agilex 5 E-Series devices.
Table 18. Clock and Reset Interface Signals

ref_clk Input 1 Reference clock for the PLL. The reference clock must be
synchronous with group_strobe_in to ensure the
dqs_enable signal is in-sync with group_strobe_in.
reset_n Input 1 Resets the interface. This is only for power-up reset. Reset
of the PHY can only be achieved by enabling dynamic
reconfiguration and writing to the TrainReset bit.
interface_locked Output 1 The interface_locked signal from PHY Lite for Parallel
Interfaces Agilex FPGA IP to the core logic. This signal
indicates that the PLL and PHY circuitry are locked.
continued...
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Data transfer should start after the assertion of this signal

and control signals should be kept at zero before
interface_locked is asserted.
core_clk_out Output 1 Use this core clock in the core-to-periphery transfer of soft
logic data and control signals.
The core_clk_out frequency depends on the interface
frequency and clock rate of user logic parameter.
rzq Input 1 This interface will be visible if on-chip termination (OCT)

with calibration is selected in the IP Parameter Editor GUI.
2.3.2.2. Output Path Signals
The following table provides the output path signals in PHY Lite for Parallel Interfaces
Table 19. Output Path Signals

Output path signals are signals that are available when you set Pin Type to either Output or Bidirectional.
The <n> in the signal names in the following table represents the group number in the IP.
group_<n>_data_fro Input Quarter rate DDR: 8 x Data signal from the Intel FPGA core.
m_core PIN_WIDTH Synchronous to the core_clk_out output
Half rate DDR: 4 x from the IP.
PIN_WIDTH
Full rate DDR: 2 x
PIN_WIDTH
Quarter rate SDR: 4 x
PIN_WIDTH
Half rate SDR: 2 x
PIN_WIDTH
Full rate SDR: 1 x
PIN_WIDTH
group_<n>_oe_from_ Input Quarter rate: 4 Output enable signal from the FPGA core.
core Half rate: 2 Synchronous to the core_clk_out output
Full rate: 1 from the IP.
Each group has separate output enable.
group_<n>_strobe_o Input Quarter rate: 4 Strobe output enable from the FPGA core.
ut_en Half rate: 2 Synchronous to the core_clk_out output
Full rate: 1 from the IP.
Each group has separate strobe enable.
group_<n>_strobe_f Input Quarter rate: 8 Strobe pattern from core. Simple strobe
rom_core Half rate: 4 pattern can be generated by this signal with
8’h55 values.
Full rate: 2
group_<n>_data_out Output 1 to 22 Data output from the IP. Synchronous to the

/group_<n>_data_io group_<n>_strobe_out or
group_<n>_strobe_io output from the IP.
If the Pin Type is set to Output, the
group_<n>_data_out signals are used.
If the Pin Type is set to Bidirectional, the
group_<n>_data_io signals are used.
continued...
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group_<n>_data_out Output 1 to 22 Differential data output from the IP.

_n/ Synchronous to the
group_<n>_data_io_ group_<n>_strobe_out_n or
n group_<n>_strobe_io_n output from the
IP.
group_<n>_strobe_o Output 1 Positive output strobe from the IP.

ut/ If the Pin Type is set to Output, the
group_<n>_strobe_i group_<n>_strobe_out signal is used.
o If the Pin Type is set to Bidirectional, the
group_<n>_strobe_io signal is used.
group_<n>_strobe_o Output 1 Negative output strobe from the IP.

ut_n/ This is used if the Strobe Configuration is
group_<n>_strobe_i set to Differential.
o_n If the Pin Type is set to Output, the
group_<n>_strobe_out_n signal is used.
If the Pin Type is set to Bidirectional, the
group_<n>_strobe_io_n signal is used.
2.3.2.3. Input Path Signals
The following table provides the input path signals in PHY Lite for Parallel Interfaces
Table 20. Input Path Signals

Input path signals are signals that are available when you set Pin Type to Input or Bidirectional. The <n> in
the signal names in this table represent the group number in the IP.
group_<n>_data_to_c Input Quarter rate DDR: 8 x Output data to the core logic. Valid on
ore PIN_WIDTH group_<n>_rdata_valid. Synchronous
Half rate DDR: 4 x to the core_clk_out output from the IP.
PIN_WIDTH
Full rate DDR: 2 x
PIN_WIDTH
Quarter rate SDR: 4 x
PIN_WIDTH
Half rate SDR: 2 x
PIN_WIDTH
Full rate SDR: 1 x
PIN_WIDTH
group_<n>_rdata_en Input Quarter rate: 4 Read enable signal.

Half rate: 2 This signal is set to high after a read
Full rate: 1 command is issued. Synchronous to the
core_clk_out output from the IP.
When using the IP as a receiver, assert this
signal after interface_locked signal is
asserted and group_strobe_in is stable.
Each group has separate read enable.
group_<n>_rdata_val Output Quarter rate: 4 Read valid signal.

id Half rate: 2 This signal determines which data are valid
Full rate: 1 when reading from RX FIFO.
Synchronous to the core_clk_out output
from the IP.
continued...
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group_<n>_data_in/ Input/ 1 to 22 Input data from external device.

group_<n>_data_io Bidirectional Synchronous to the
group_<n>_strobe_in or
group_<n>_strobe_io input. The first
data_in must be associated with positive
edge of group_<n>_strobe_in/
group_<n>_strobe_io.
If the pin type is set to Input, the
group_<n>_data_in ports are used.
If the pin type is set to Bidirectional, the
group_<n>_data_io ports are used.
group_<n>_data_in_n Input/ 1 to 22 Differential input data from external device.

/ Bidirectional Synchronous to the
group_<n>_data_io_n group_<n>_strobe_in_n or
group_<n>_strobe_io_n output from
the IP.
group_<n>_strobe_in Input/ 1 Input strobe from external device. If the

/ Bidirectional pin type is set to Input, the
group_<n>_strobe_io group_<n>_strobe_in signal is used. If
the pin type is set to Bidirectional, the
group_<n>_strobe_io signal is used.
group_<n>_strobe_in Input/ 1 Negative strobe from external device. This

_n/ Bidirectional is used if the Strobe Configuration is set
group_<n>_strobe_io to Differential.
_n If the pin type is set to Input, the
group_<n>_strobe_in_n signal is used.
If the pin type is set to Bidirectional, the
2.4. I/O Standards

The PHY Lite for Parallel Interfaces IP allows you to set I/O standards on the pins
associated with the generated configuration. The I/O standard controls the available
strobe configurations and OCT settings for all groups. One RZQ group supports up to
two different output terminations and one input termination. RZQ pin cannot be used
as data pin.
Supported I/O standards are listed in the following table. Differential data are
supported for all I/O standards. Differential ref_clk is not supported in the same
lane as PHY Lite for LVSTL I/O standards.
Table 21. I/O Standards and Termination Values for Agilex 5 E-Series Devices
I/O Standard Valid Input Input Termination Valid Output Output Termination RZQ (Ω)
Terminations (Ω) Without Terminations (Ω) Without Calibration
Calibration (Ω) (Ω)
SSTL-12 50, 60 50 34, 40 34, 40 240
1.2-V POD 40, 50, 60 50 34, 40 34, 40 240
1.1-V POD 40, 50, 60 50 34, 40 34, 40 240
1.2-V HSTL 50, 60 50 34, 40 34, 40 240

continued...
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I/O Standard Valid Input Input Termination Valid Output Output Termination RZQ (Ω)
Terminations (Ω) Without Terminations (Ω) Without Calibration
Calibration (Ω) (Ω)
1.2-V HSUL — — 34, 40 34, 40 240
1.1-V LVSTL 40, 50, 60 50 34, 40 34, 40 240
1.05-V LVSTL 40, 50, 60 50 34, 40 34, 40 240
2.4.1. Design Guidelines
2.4.1.1. DQS Trees
The PHY Lite for Parallel Interfaces IP supports two DQS trees, namely an x8 tree that
spans over one lane and an x16 tree that spans over two adjacent lanes, as described
in the following table.
Table 22. DQS Trees in Agilex 5 E-Series Devices

DQS tree Lane(s) used Group size Strobe pins
x8 Any lane 1 - 10 Pin 4, 5
x16 [0,1] 1 - 22 Pin 4, 5 of the even lane

[2,3]
[4,5]
[6,7]
For single-ended strobe, only pin 4 is used as DQS. The remaining strobe pin (pin 5)
cannot be used as data.
2.4.1.2. Pin Placement Restrictions
Follow these guidelines to place the PHY Lite for Parallel Interfaces IP group pins:
1. Assign each lane to only one group. Each group is either mapped to one lane (x8
mode) or two lanes (x16 mode). When using x16 DQS tree, the first lane should
be an even lane. A group cannot share a lane with another group.
2. If using termination with calibration, reserve pin 38 or 62 for RZQ. RZQ is a 240
ohm resistor that you attach it to a specific pin as an impedance reference to
calibrate driving and termination impedances to avoid signal reflection. One RZQ
group can support up to two different output terminations and one input
termination. RZQ pin cannot be used as data pin.
3. No input or bidirectional pins can be placed in the same lane as RZQ, i.e., lane 3
(pin 38) or lane 5 (pin 62). Only output pins can be placed in the same lane as the
RZQ pin.
4. Place differential data on two adjacent pins. The first pin should be an even pin.
The following figure shows two differential data pins placed on pins 2-3 and 12-13
pairs, occupying 4 pins in total. This example uses an x16 DQS tree since the data
pins span over two lanes.
5. Differential ref_clk is not supported in the same lane as PHY Lite IP for the
LVSTL I/O standard.
6. For both auto and manual pin placements, ensure that the ref_clk pins are
reserved only in any of the following eight pins:
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• Pins 34, 35 (Lane 2)

• Pins 36, 37 (Lane 3)
• Pins 58, 59 (Lane 4)
• Pins 60, 61 (Lane 5)
7. PHY Lite IP instances in different I/O banks must be connected to different
Calibration IPs.
8. PHY Lite IP instances in the same I/O bank will be connected to the same
Calibration IP, but different Instance ID must be assigned in the IP Parameter
Editor to differentiate the base address of the instances (Rev B only).
9. In the input-only pins with I/O standard, SSTL-12 or HSTL-12, toggle rddata_en
to benefit from On-Die Termination (ODT) rotation. If RX is enabled 100% of the
time (if rddata_en is not toggled), only 32 data pins are allowed.
Rotation happens when rddata_en goes low. However, if receiving data in bursts
and the burst sizes are not equal, the maximum imbalance should be 40% to 60%
to get credit for the first row in the On-Die Termination (ODT) table.
To support 100% Activity Factor (AF), toggle rddata_en at least 80% of the time
with a maximum imbalance of 40% to 60%.
Figure 14. Differential Data Pin Placement
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Figure 15. On-Die Termination (ODT) Rotation
Table 23. On-Die Termination (ODT)

Case Maximum Input Pins
90%<AF≤100% 32
80%<AF≤90% 38
70%<AF≤80% 48
60%<AF≤70% 58
0%<AF≤60% 96
2.4.1.3. Maximum Number of DQ Data Pin Configurations
This section describes the automatic and manual pin placements, as well as example
pin configurations for single-ended, differential, and mixed pin groups.
2.4.1.3.1. Automatic and Manual Pin Placement
The IP Parameter Editor of the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex
5 E-Series devices allows automatic pin placement, as shown in the following figure.
To manually place the pins, check the Enable manual location of data pins
checkbox as shown in the next figure.
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Figure 16. Automatic placement of data pins in PHY Lite IP Parameter Editor
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Figure 17. Enable Manual Location of Data Pins in PHY Lite IP Parameter Editor
Although the ref_clk is not visible in the IP Parameter Editor, Intel recommends 1 or
2 pins to be reserved for single-ended or differential ref_clk in the IO96 bank where
the PHY Lite IP is to be placed. The following error message will be displayed in the
System Messages panel of the IP Parameter Editor if no pin is reserved for the
ref_clk and using automatic pin placement.
THIS PHYLITE IP REQUIRES A TOTAL OF N DATA PINS. ONLY N-1 DATA PINS SUPPORTED FOR
SELECTED CONFIGURATION.
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Figure 18. Error Message in PHY Lite IP Parameter Editor if No Pin is Reserved for
ref_clk
If the ref_clk is not reserved in any of the eight dedicated pins, the following error
message will be displayed in the System Messages panel of the IP Parameter Editor.
REFCLK MUST BE PLACED EITHER ON PIN 34, 35, 36, 37, 58, 59, 60 OR 61. ALL THESE
PINS ARE CURRENTLY ASSIGNED AS DATA PINS.
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Figure 19. Error Message in PHY Lite IP Parameter Editor if ref_clk is Not Reserved in
Any of the Eight Dedicated Pins
The reset_n pin for each PHY Lite instance can be placed in the same or different
IO96 bank.
2.4.1.3.2. Single-Ended Pin Configurations
Single-ended DQ output data pins can be configured into a maximum of 8 groups

using x8 DQS trees, with a maximum of 10 single-ended DQ data pins per group
except for the RZQ lane. The RZQ lane can have a maximum of 9 single-ended DQ
data pins. If the ref_clk pin is reserved in the same RZQ lane, then the maximum
number of DQ data pins in this lane will be 8 or 7, depending on 1 or 2 pins for single-
ended or differential ref_clk. For instance, using a single-ended ref_clk and
differential strobe pins, the maximum number of single-ended DQ output data pins in
this 8-group configuration can be determined as follows:
LANES 0, 1, 2, 4, 5, 6, and 7 : 7 groups/lanes x 10 DQ pins = 70 DQ pins
LANE 3 : 1 group/lane x 8 DQ pins = 8 DQ pins
TOTAL : 78 DQ pins
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Figure 20. Single-ended DQ Output Data Pin Configuration for 8 Groups
Single-ended DQ output data pins can also be configured into a maximum of 22 pins
per group, with a maximum of 4 groups using x16 DQS trees. Using the same
scenario of a single-ended ref_clk reserved on pin 36 (Lane 3) and using differential
strobe pins, the maximum number of single-ended DQ output data pins in this 4-
group configuration can be determined as follows:
LANES 0-1, 4-5, and 6-7 : 3 groups x 22 DQ pins = 66 DQ pins
LANES 2-3 : 1 group x 20 DQ pins = 20 DQ pins
TOTAL : 86 DQ pins
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Figure 21. Single-ended DQ Output Data Pin Configuration for 4 Groups
Single-ended DQ input or bidirectional data pins cannot share the same lane as the
RZQ pin. Thus, input or bidirectional data pins can be configured into a maximum of 7
groups using x8 DQS trees, with a maximum of 10 pins per group. Using the same
scenario of a single-ended ref_clk reserved on pin 36 (Lane 3) and using differential
strobe pins, the maximum number of single-ended DQ input or bidirectional data pins
in this 7-group configuration can be determined as follows:
TOTAL : 70 DQ pins
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Figure 22. Single-ended DQ Input or Bidirectional Data Pin Configuration for 7 Groups
Single-ended input or bidirectional data pins can also be configured into a maximum
of 4 groups using x16 DQS trees, with a maximum of 22 pins per group except for the
group containing the RZQ lane, which cannot be shared with any input or bidirectional
data pin. Using the same scenario of a single-ended ref_clk reserved on pin 36 or
37 (Lane 3) and using differential strobe pins, the maximum number of single-ended
DQ input or bidirectional data pins in this 4-group configuration can be determined as
follows:
LANES 0-1 and 6-7 : 2 groups x 22 DQ pins = 44 DQ pins
LANES 2 : 1 group x 10 DQ pins = 10 DQ pins
LANE 3 : 0 group x 0 DQ pin = 0 DQ pin
Total : 76 DQ pins
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Figure 23. Single-ended DQ Input or Bidirectional Data Pin Configuration for 4 Groups
2.4.1.3.3. Differential Pin Configurations
Differential DQ output data pins can be configured into a maximum of 8 groups using
x8 DQS trees, with a maximum of 5 differential DQ data pins per group except for the
RZQ lane. The RZQ lane can have a maximum of 4 differential DQ data pins. For
instance, using a single-ended ref_clk reserved on pin 36 or 37 (Lane 3) and using
differential strobe pins, the maximum number of single-ended DQ output data pins in
this 8-group configuration can be determined as follows:
TOTAL : 38 DQ pins
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Figure 24. Differential DQ Output Data Pin Configuration for 8 Groups
Differential DQ output data pins can also be configured into a maximum of 11 pins per
group, with a maximum of 4 groups using x16 DQS trees. Using the same scenario of
a single-ended ref_clk reserved on pin 36 or 37 (Lane 3) and using differential
strobe pins, the maximum number of single-ended DQ output data pins in this 4-
group configuration can be determined as follows:
TOTAL : 42 DQ pins
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Figure 25. Differential DQ Output Data Pin Configuration for 4 Groups
Differential DQ input or bidirectional data pins cannot share the same lane as the RZQ
pin. Thus, input or bidirectional data pins can be configured into a maximum of 7
groups using x8 DQS trees, with a maximum of 5 pins per group. Using the same
scenario of a single-ended ref_clk reserved on pin 36 or 37 (Lane 3) and using
differential strobe pins, the maximum number of differential DQ input or bidirectional
data pins in this 7-group configuration can be determined as follows:
TOTAL : 35 DQ pins
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Figure 26. Differential DQ Input or Bidirectional Data Pin Configuration for 7 Groups
Differential input or bidirectional data pins can also be configured into a maximum of 4
groups using x16 DQS trees, with a maximum of 11 pins per group except for the RZQ
lane, which cannot be shared with any input or bidirectional data pin. Using the same
scenario of a single-ended ref_clk reserved on pin 36 or 37 (Lane 3) and using
differential strobe pins, the maximum number of differential DQ input or bidirectional
data pins in this 4-group configuration can be determined as follows:
LANE 2 : 1 group x 5 DQ pins = 5 DQ pins
LANE 3 : 0 group x 0 DQ pins = 0 DQ pins
Total : 38 DQ pins
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Figure 27. Differential DQ Input or Bidirectional Data Pin Configuration for 4 Groups
2.4.1.3.4. Mixed Pin Configurations
The PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-Series devices allows a
mixture of pin configurations, provided that general pin restrictions are followed. For
instance, the following table and figure show a mixed pin configuration, using the
same scenario of a single-ended ref_clk reserved on pin 36 (Lane 3) and using
differential strobe pins. The total number of DQ pins depends on the mixed pin
configuration setting.
Table 24. Example of Mixed Pin Configuration Settings

Group Pin Type Pin Width DDR/SDR Pin Configuration
0 Bidirectional 10 DDR Single-ended
1 Input 10 DDR Single-ended
2 Output 11 DDR Differential
3 Output 8 SDR Single-ended
4 Bidirectional 9 DDR Single-ended
5 Bidirectional 11 DDR Differential
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Figure 28. Example of Mixed Pin Configuration
2.5. Design Example

The PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-Series devices is able
to generate a design example that matches the same configuration chosen for the IP.
The design example is a simple design that does not target any specific application.
However, you can use the design example as a reference on how to instantiate the IP
and what behavior to expect in a simulation.
You can generate a design example by clicking Generating Example Design in the
IP Parameter Editor.
Note: The generated .qsys files are for internal use during design example generation only.
You should not edit the files.
2.5.1. Generate the Design Example

To generate a design example, click Generating Example Design in the IP
Parameter Editor.
The software generates a user-defined directory in which the design example files
reside.
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There are two variants of design example available for PHY Lite for Parallel Interfaces
Intel FPGA IP for Agilex 5 E-Series devices:
• Without dynamic reconfiguration
• With dynamic reconfiguration
The following table describes the generated .qsys design files for design example with
and without dynamic reconfiguration.
Table 25. PHY Lite for Parallel Interfaces IP Design Example Variants
Design Example Variant Design File Description
Dynamic Reconfiguration On ed_synth.qsys (synthesis only) Consists of PHY Lite for Parallel
Interfaces IP instance with Calibration
IP.
ed_sim.qsys (simulation only) Consists of PHY Lite for Parallel

Interfaces IP instance with Calibration
IP, IOSSM Tester, Tester Core, and
Tester I/O
Off ed_synth.qsys (synthesis only) Consists of PHY Lite for Parallel

Interfaces IP instance.
ed_sim.qsys (simulation only) Consists of PHY Lite for Parallel

Interfaces IP instance with Tester Core
and Tester I/O.
2.5.1.1. Design Example without Dynamic Reconfiguration
When the Enable dynamic reconfiguration option is not selected, the Quartus
Prime software generates a design example of PHY Lite for Parallel Interfaces IP
without a dynamic reconfiguration module. This design example consists of simulation
and synthesis design files.
2.5.1.1.1. Generate the Synthesis Design Example without Dynamic Reconfiguration
The make_qii_design.tcl generates a synthesizable hardware design example and

an Quartus Prime project, ready for compilation.
To generate synthesizable design example, run the following script at the end of IP
generation:
quartus_sh -t make_qii_design.tcl
To specify an exact device to use, run the following script:

quartus_sh -t make_qii_design.tcl [device_name]
This script generates a qii directory containing a project called ed_synth.qpf. Use
the Quartus Prime software to open and compile this project.
The following figure shows a high-level view of the generated synthesis design
example without dynamic reconfiguration and one group of data pins.
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Figure 29. High-Level View of the Synthesis Design Example with One Group
This figure shows a high-level view of the synthesis design example with one group of data pins.
data_from_core data_to_core
strobe_from_core rdata_valid
rdata_en data_io
oe_from_core strobe_io
Phylite_ph2
strobe_out_en strobe_io_n
ref_clk interface_locked
reset_n reset_out_n core_clk_out
ninit_done Reset Handler
Init
2.5.1.1.2. Generate the Simulation Design Example Without Dynamic Reconfiguration
The make_sim_design.tcl generates a simulation design example and tool-specific

scripts to compile and elaborate the necessary files.
To generate the design example for a Verilog or a mixed-language simulator, run the
following script at the end of IP generation:
quartus_sh -t make_sim_design.tcl VERILOG
To generate the design example for a VHDL-only simulator, run the following script:
quartus_sh -t make_sim_design.tcl VHDL
This script generates a sim directory containing one subdirectory for each supported
simulation tool. Each subdirectory contains the specific scripts to run simulation using
the corresponding tool.
The simulation design example provides a generic example of the core and I/O
connectivity for your IP configuration. Functionally, the simulation triggers read and
write operations over each group in your configured IP. The following diagram shows a
simple one group PHY Lite for Parallel Interfaces IP instantiation in the testbench.
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Figure 30. High-Level View of the Simulation Design Example without Dynamic
Reconfiguration
This figure shows a high-level view of the generated simulation design example without dynamic
reconfiguration, consisting of a PHYLite IP instance, an IO model, and a PHYLite Interface module.
Example Design
Tester
IO Interface
I0 Model
Pass/Fail
PHYLite_ph2
Core Interface
PHYLite Interface
2.5.1.1.3. Run the Simulation Design Example Without Dynamic Reconfiguration
Follow these steps to compile and simulate the design:

1. Change the working directory to <Example Design>\sim\ed_sim
\<Simulator>.
2. Run the simulation script for the simulator of your choice. Refer to the following
table.
Table 26. Steps to Run Simulation Script for Different Simulators

Simulator Working Directory Steps
Questasim <Example Design>/sim/ed_sim/mentor • vsim

• do msim_setup.tcl
• ld_debug
• Add desired signals into the
waveform window
• run -all
VCS <Example Design>/sim/ed_sim/ sh vcs_setup.sh

synopsys/vcs
VCSMX <Example Design>/sim/ed_sim/synopsys/ sh vcsmx_setup.sh

vcsmx
Xcelium <Example Design>/sim/ed_sim/xcelium sh xcelium_setup.sh
2.5.1.2. Design Example with Dynamic Reconfiguration
When you select the Use dynamic reconfiguration option and click Generate
Example Design, the Quartus Prime software generates the dynamic reconfiguration
simulation and synthesis-based examples.
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2.5.1.2.1. Generate the Synthesis Design Example With Dynamic Reconfiguration

generation:

The synthesis design example provides an example of the core and I/O connectivity
for your IP configuration with Calibration IP as the interface for the Avalon memory
mapped calibration addresses.
Figure 31. High-Level View of the Synthesis Design Example with Dynamic
Reconfiguration
This figure shows a high-level view of the generated synthesis design example with dynamic reconfiguration
and one group of data pins.
rdata_en data_io
strobe_out_en Phylite_ph2 strobe_io_n
ninit_done Reset Handler calbus_param_table
Init calbus_0
calbus_readdata
AXI-Lite Interface Cal IP
2.5.1.2.2. Generate the Simulation Design Example with Dynamic Reconfiguration
The make_sim_design.tcl generates a simulation design example and tool specific

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Figure 32. High-Level View of the Simulation Design Example with Dynamic
Reconfiguration
This figure shows a high-level view of the simulation design example with dynamic reconfiguration, consisting
of a PHY Lite IP instance, Calibration IP, IOSSM Tester, IO Model, and PHYLite Interface modules.
Example Design
Tester
AXI-Lite Interface
Calibration IP I0SSM Tester
Avalon
Memory-
Mapped
Interface
IO Interface
I0 Model
Pass/Fail
PHYLite_ph2 Core Interface PHYLite Interface
2.5.1.2.3. Run the Simulation Design Example Without Dynamic Reconfiguration

1. Change the working directory to <Example Design>\sim\ed_sim
\<Simulator>.
2. Run the simulation script for the simulator of your choice. Refer to the following
table.
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Table 27. Steps to Run Simulation Script for Different Simulators

Questasim <Example Design>/sim/ed_sim/mentor • vsim

• do msim_setup.tcl
• ld_debug
• Add desired signals into the
waveform window
• run -all
VCS <Example Design>/sim/ed_sim/synopsys/vcs sh vcs_setup.sh
VCSMX <Example Design>/sim/ed_sim/synopsys/ sh vcsmx_setup.sh

vcsmx
Xcelium <Example Design>/sim/ed_sim/xcelium sh xcelium_setup.sh
2.5.2. Verify Simulation Design Examples using Tester IP

The design examples, both with dynamic reconfiguration and without dynamic
reconfiguration, use Tester IP to verify PHY Lite for Parallel Interfaces IP functionality.
The tester exercises read and write operations to the PHY Lite for Parallel Interfaces IP
to verify its functionality.
At a high level, the tester is a state machine that repeatedly performs read/write
operations. Disabling a test causes the corresponding tester state to be skipped. The
following lists the tester states in the order they are performed:
1. STATE_INIT: Initialization
2. STATE_TEST_CALBUS: Calibration when dynamic reconfiguration is enabled
3. STATE_TEST_WRITE: Enabled only in output and bidirectional modes
4. STATE_TEST_READ: Enabled only in input and bidirectional modes
5. STATE_DONE: All bursts of data successfully transmitted
The following table shows the port connections between the PHY Lite for Parallel
Interfaces IP instance and Tester module. Tester ports not shown in the table are
pass_out and fail_out which signal the success or failure of the test. Multiple PHY
Lite for Parallel Interfaces IP groups can be tested by daisy chaining testers and
connecting pass_out and fail_out of each tester to the pass_in and fail_in
ports of the next tester in chain. The Calbus ports are not shown in the table as well.
In the write tests, PHYLite Interface module sends pseudorandom binary sequence
(PRBS) pattern, strobe, and control signals to PHY Lite IP instance, and PHY Lite IP
instance outputs the data and strobe to the I/O model, where the data are checked
against the PRBS pattern. In the read tests, the reverse happens.
Table 28. PHY Lite IP Instance and Tester Port Connections

This table lists the PHY Lite IP instance and Tester port connections.
Ports Connection PHY Lite for Parallel Interfaces Width Tester Ports
Ports
PHY Lite for Parallel group_X_data_from_core GROUP_DATA_WIDTH group_data_from_core

Interfaces interface
submodule group_X_oe_from_core GROUP_CTRL_WIDTH group_oe_from_core
group_X_strobe_from_core GROUP_STROBE_WIDTH group_strobe_from_core

continued...
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Ports
group_X_strobe_out_en GROUP_CTRL_WIDTH group_strobe_out_en
group_X_data_to_core GROUP_DATA_WIDTH group_data_to_core
group_X_rdata_en GROUP_CTRL_WIDTH group_rdata_en
group_X_rdata_valid GROUP_CTRL_WIDTH group_rdata_valid
I/O model group_X_data_out GROUP_PIN_WIDTH group_data_out
group_X_data_out_n GROUP_PIN_WIDTH group_data_out_n
group_X_data_in GROUP_PIN_WIDTH group_data_in
group_X_data_in_n GROUP_PIN_WIDTH group_data_in_n
group_X_data_io GROUP_PIN_WIDTH group_data_io
group_X_data_io_n GROUP_PIN_WIDTH group_data_io_n
group_X_strobe_out 1 group_strobe_out
group_X_strobe_out_n 1 group_strobe_out_n
group_X_strobe_in 1 group_strobe_in
group_X_strobe_in_n 1 group_strobe_in_n
group_X_strobe_io 1 group_strobe_io
group_X_strobe_io_n 1 group_strobe_io_n
The tester instantiates the following three submodules:

• I/O model: Connects to the PHY Lite for Parallel Interfaces I/O interface. Includes
two instances of pseudorandom binary sequence (PRBS) channel, one to generate
random pattern for read tests, and one to check the received pattern in the write
tests.
• PHYLite interface: Connects to the PHY Lite for Parallel Interfaces IP core interface.
Includes two instances of PRBS channel, one to generate random pattern for write
tests, and one to check received pattern in the read tests. Reframing logic is also
included in this module.
• IOSSM tester: Exposes an AXI4-Lite IP Interface and performs reads and writes to
change the TX delay on pin 0. Only available for simulation example design with
dynamic reconfiguration.
Table 29. Tester Module Top Level Interfaces

Module Parameter Default value Description
IOSSM Tester TESTER_PRBS_SEED 36'b00000011111000001111000011 Seed for the LFSRs

1000110010 used to generate the
pseudorandom
bitstream that is
used for test data
TESTER_NUM_REPEATS 8 How many times to

repeat the test
sequence
continued...
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Module Parameter Default value Description
TESTER_NUM_BURSTS 1024 Number of bursts to

send per test. In this
tester a "burst"
refers to one core
clock of data (e.g., 8
bits in QR DDR). This
is not to be confused
with the internal
burst length setting
in the PHY.
TESTER_PREAMBLE_MODE ONE_CYCLE Refer to Read Test

section for a visual
illustration.
TESTER_IS_LAST_IN_CHAIN 1 Whether this tester is

the last one in the
daisy-chain. This will
mean that in
simulation it calls
$finish() after
reaching the end of
its testing.
PHYLite Interface PHYLITE_USE_DYNAMIC_RECONF 0 0 – without dynamic

IGURATION reconfiguration
1 – with dynamic
reconfiguration
PHYLITE_MEMCLK_PERIOD_PS 1667 Period of the

interface frequency in
picoseconds
PHYLITE_IN_RATE 4 Rate conversion

factor
PHYLITE_READ_LATENCY 8 Latency from

rddata_en to DQS
ungate
PHYLITE_WRITE_STROBE_ALIGN CENTER_ALIGNED Either

MENT "CENTER_ALIGNED"
or "EDGE_ALIGNED"
- Alignment of data
output by PHYLite
PHYLITE_READ_STROBE_ALIGNM CENTER_ALIGNED Either

ENT "CENTER_ALIGNED"
or "EDGE_ALIGNED"
- Alignment of data
input to PHYLite
Group GROUP_PIN_WIDTH 8 1-22
GROUP_PIN_TYPE BIDIRECTIONAL INPUT, OUTPUT or

BIDIRECTIONAL
GROUP_DDR_SDR_MODE DDR SDR or DDR
GROUP_DATA_CONFIG SINGLE_ENDED SINGLE_ENDED or

DIFFERENTIAL
GROUP_STROBE_CONFIG DIFFERENTIAL SINGLE_ENDED or

DIFFERENTIAL
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2.5.2.1. PHY Lite Interface
This module models the core logic. Apart from the ports listed in PHY Lite IP Instance
and Tester Port Connections table, additional ports for this module are shown in the
following table.
Table 30. PHY Lite Interface Module Ports

Port Type Description
reset_n Input —
core_clk Input —
repeat_count Input Tester repeat count
pl_wrdata_en Input Write enable from core
pl_rddata_en Input Read enable from core
pl_rddata_pass Output Read pass
pl_rddata_fail Output Read fail
In the write test, this module provides the enable signals for data and strobe, the
strobe pattern, and random data generated by the PRBS channel.
In the read test, it provides the read enable signal from core, receives the data and
strobe and performs a check using a PRBS channel, and provides the corresponding
read pass or read fail signal. There is also reframing logic to find the frame offset in
LINK mode.
2.5.2.2. I/O Model
This module models the I/O pins. The write path is running a state machine to
implement the preamble mode, explained in more details in Read test section. In the
I/O model, mem_clk is generated from the core clock. Apart from the ports listed in
Table 28 on page 51 table, additional ports for this module are shown in the following
table.
Table 31. I/O Model Module Ports

reset_n Input —
core_clk Input —
repeat_count Input Tester repeat count
io_wrdata_en Input Write enable from tester
io_rddata_en Input Read enable from tester
io_rddata_pass Output Read pass
io_rddata_fail Output Read fail
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2.5.2.3. IOSSM Tester
The IOSSM tester provides an example of how the core logic should drive the AXI4-
Lite interface of the Calibration IP to perform read and write operations to the Avalon
memory-mapped calibration addresses. It connects to the AXI4-Lite interface of the
Calibration IP through the ports in Table 14 on page 18. Additional ports of this
module are listed in the following table.
Table 32. IOSSM Tester Ports

reset_n Input —
core_clk Input —
iossm_test_start Input Enable the Calbus test
pl_calbus_pass Output Calbus test pass
pl_calbus_fail Output Calbus test fail
This module creates the base address of the Avalon memory-mapped register that
contains the TX delay. The base address is created using the instance ID and lane ID.
The full address is derived by adding the offset address of the said register, and it is
used as both the write address and read address. This module uses an FSM to go
through different stages of read/write operation through AXI4-Lite interface.
2.5.2.4. Write Test
When the tester is in the STATE_TEST_WRITE, it asserts the wrdata_en which drives
the pl_wrdata_en. The PHY Lite Interface module delays the enable by one cycle to
allow for the preamble. A burst counter counts until reaching TESTER_NUM_BURSTS.
While outputting data, we also advance the PRBS to generate new random data. After
the burst counter finishes counting, wrdata_finish is asserted. In the write test,
handshaking happens in the I/O model. The relevant signals are shown in the
following figure.
Figure 33. Write Test Signals
2.5.2.5. Read Test
The receiver is tested using one cycle of preamble and 0x1, 0x0 strobe pattern.
PHYLITE_READ_LATENCY must exactly match the internal rddata_en to RcvEn
latency of the PHY. The phase shift of RcvEn may need to be adjusted to maximize
margin. This test is shown in the following figure.
Figure 34. Read Test Using One Cycle of Preamble

This figure shows the read test performed using one cycle of preamble.
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Figure 35. Handshaking Signals in Read Test

This figure shows Handshaking signals in the read test.
2.5.2.6. Calbus Test
If dynamic reconfiguration is enabled, the tester goes to the STATE_TEST_CALBUS

before starting write/read tests. At this state, the IOSSM tester reads the output delay
on pin 0, adds it by 2 and writes it to the same register and reads it back to confirm
the write operation was successful.
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Send Feedback

7 M-Series Devices

Intel FPGA IP versions match the Quartus Prime Design Suite software versions until
v19.1. Starting in Quartus Prime Design Suite software version 19.2, Intel FPGA IP
has a new versioning scheme.
The Intel FPGA IP version (X.Y.Z) number can change with each Quartus Prime
software version. A change in:
features.
changes.
Table 33. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 M-Series Devices
Release Information
Item Description
IP Version 5.0.0
Quartus Prime Version 24.1
Related Information
PHY Lite for Parallel Interfaces Intel FPGA IP Core Release Notes
Provides a list of changes made in each release of the PHY Lite for Parallel
Interfaces Intel FPGA IP.

The PHY Lite for Parallel Interfaces Intel FPGA IP utilizes the I/O banks in Agilex 7 M-
Series devices. Each I/O bank has eight I/O lanes with 12 pins in each lane, providing
a total of 96 pins per bank. Each bank contains pins that you can use for data and pins
that are reserved for strobe, reference clock, and RZQ.
3. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 M-Series Devices
683716 | 2024.04.01
Figure 36. M-Series I/O Bank Structure (Die Top View)

This figure shows the I/O bank structure of the M-Series device. The figure shows the view of the die as shown
in the Quartus Prime Chip Planner. In the Pin Planner, this corresponds to the "Bottom View". Different
device packages have different number of I/O banks. Refer to the device pin-out files for available I/O banks
and the locations of the SDM and HPS shared I/O banks for each device package.
Applicable to Banks 2A, 3A, and 3B
Bottom Index Sub-Bank Top Index Sub-Bank
0 Index: #0-#47 47 48 Index: #48-95 95
Applicable to Banks 2B, 2C, 2D, 3C, and 3D
Top Index Sub-Bank Bottom Index Sub-Bank
Index: #48-#95 Index: #0-47
I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane 3A 3B 3C 3D HPS 95 48 47 0
Top I/O Bank Row

I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane
Bottom Index Top Index

I/O PLL I/O PLL
Bottom I/O Bank Row
HMC Fabric Clock HMC
OCT SDM 2A 2B 2C 2D Top Index Bottom Index
Slim PLL Network Wide
I/O PLL I/O PLL
I/O Center
HMC Clock Fabric HMC
OCT
HPS I/O Bank HPS Shared GPIO-B Bank Wide Network PLL Slim
SERDES & DPA
I/O Center
Differential I/O buffer pair SDM I/O Bank SDM Shared GPIO-B Bank GPIO-B Bank
Related Information
Design Guidelines on page 78
For more information about placement restrictions
3.2.1. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 M-Series
Devices Top Level Interfaces
For M-Series devices, the PHY Lite for Parallel Interfaces Intel FPGA IP consists of the
following modules:
• Clocks and reset
• Fabric
• PHY data and control
• I/O
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Figure 37. Diagram of the PHY Lite for Parallel Interfaces Intel FPGA IP for M-Series
Devices
Top-level PHY Lite
Clocks PHY Data and

Control
Ref PHY
Clk IOPLL CPA Clk Lane
Lane
Fabric Lane
data_to_core Lane
I/O
data_from_core Lane
strobe_from_core data_in/out/io
Lane
oe_from_core
strobe_out_en Lane strobe_in/out/io
rdata_en Lane
rdata_valid
Related Information
• Output Path on page 60
• Input Path on page 62
• Signals on page 74
Provides more information about the IP data, control, and I/O interfaces.
3.2.1.1. Clocks
The PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 M-Series devices sources
the reference clock from a dedicated clock pin to the PLL inside the IP. This PLL
provides four clock domains for the output and input paths.
Table 34. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 M-Series Devices
Clock Domains
Core clock The IP generates this clock internally and uses it for all transfers between the FPGA core
fabric and I/O banks. The clock phase alignment (CPA) circuitry keeps the clock in phase
with the PHY clock for transfers between the core and the periphery.
PHY clock The IP uses this clock internally for PHY circuitry.
VCO clock The PLL generates this clock internally. The input and output paths use the VCO clock to
generate interpolator delays that compensate for PVT variations.
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FPGA IP for Agilex 7 M-Series Devices
Interface Core Clock Rate VCO Frequency VCO Clock PHY Clock (MHz) Core Clock
Frequency (MHz) (PHYLITE_IN_RA Multiplier Factor Frequency (MHz) Frequency (MHz)
TE) (PHYLITE_OUT_R
ATE)
600-1250 4 1 600-1250 300-625 150-312.5
300-600 2 2 600-1200 300-600 150-300
150-300 1 4 600-1200 300-600 150-300
Note: The core clock rate of the PHY Lite for Parallel Interfaces Intel FPGA IP is fixed based
on selected interface frequency.
3.2.1.1.1. Clock Frequency Relationships
Equation 2. Relationships Between Clock Domains in the PHY Lite for Parallel Interfaces
Intel FPGA IP
Core Clock Rate Interface Clock Frequency

=
(PHYLITE_IN_RATE) Core Clock Frequency
VCO Frequency Multiplier Factor VCO Clock Frequency
=
(PHYLITE_OUT_RATE) Interface Clock Frequency

The simplified output path consists of pipeline registers, TX FIFO, shift register, and
phase shift blocks. The following figure shows strobe and data coming from the core,
together with the related enable signals, go through the pipeline stages before the TX
FIFO.
Figure 38. Simplified Output Path

This figure shows the simplified output path for the PHY Lite for Parallel Interfaces Intel FPGA IP.
Pipeline
Phase Shift
Registers
group_<n>_data_from_core group_<n>_data_out/
TX FIFO Phase Shift
Pipeline group_<n>_strobe_out/
Registers
group_<n>_strobe_from_core group_<n>_strobe_out_n
Inherent Delay TxDqDelay
Pipeline
Registers Shift Register
group_<n>_oe_from_core
Pipeline
Registers Shift Register
group_<n>_strobe_ out_en
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Table 36. Components in Simplified Output Path

Pipeline Registers Represent pipeline stages in the output path.
TX FIFO Stores the data to be transmitted out.
Shift Register Delays the enable signal at the read side of the TX FIFO at VCO cycle increment.
Phase Shift Delays TX data and strobe at 1/128 of a VCO cycle increments.
There are two types of delays in the output path, namely inherent latency and output
delay, TxDqDelay.
Table 37. Types of Delay in Output Path

Inherent latency Static Captured in the pipeline stages from the assertion of the output enable
in the core (group_<n>_oe_from_core[]) until the data go into TX
FIFO.
The parameter Additional Write Latency in the IP Parameter Editor
is added to the inherent latency.
TxDqDelay delay (output Dynamic You can configure this 11-bit wide register in the control registers. The
delay) TxDqDelay register consists of two parts, as described in the next
table. The integer part of the delay uses a shift register to delay the
enable signal that goes to the read side of TX FIFO.
Table 38. Output Path Reconfigurable Delays Description

This table describes the reconfigurable output path delay.
Feature Description Min Max
TxDqDelay Integer number of VCO clock cycles. The integer portion of the delay is 0 15
[10:7] accomplished using a shift register to delay the enable signal that goes to
the read side of the TX FIFO.
TxDqDelay Additional phase shift measured in 1/128 of VCO clock period. 0 127
[6:0]
Figure 39. Output Operation

This figure shows the output operation for the PHY Lite for Parallel Interfaces Intel FPGA IP.
core_clk
data_from_core ABCDEFGH IJKLMNOP
strobe_from_core 55
oe_from_core 0 F 0
strobe_out_en 8 F 0
data_out H G F E D C B A P O NM L K J I
strobe_out
strobe_out_n
= Signals Truncated
The preceding figure shows an example of TX data transfer in QR DDR. The

data_from_core for each pin is 8 bits wide. To enable one extra preamble cycle
before the data starts, wait for strobe_out_en to transition from 0 to h8 in one core
clock cycle before the oe_from_core signal, as shown in the figure. Setting Output
strobe phase to 90 degrees causes the PHY Lite IP to send the data center aligned.
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Related Information
Output Path Signals on page 75
Provides more information about output path signals.
3.2.1.3. Input Path

The simplified input path of the IP consists of the pipeline registers, receiver FIFO,
shift registers, and phase shift logics.
Figure 40. Simplified Input Path

This figure shows the input path for the PHY Lite for Parallel Interfaces Intel FPGA IP.
Inherent Delay RxRcvEnPi
Pipeline RcvEn
Shift Register Phase Shift
Registers
group_<n>_rdata_en
Pipeline Clock
Registers Shift Register Gate group_<n>_strobe_in/
group_<n>_rdata_valid
read_enable_offset
Per group
Per pin RxDqsNDelayPi/
fifo_read_enable RxDqsPDelayPi
Phase Shift
RX FIFO
Pipeline
Registers
group_<n>_data_to_core group_<n>_data_in
Table 39. Components in the Simplified Input Path of the PHY Lite for Parallel
Pipeline Registers Represent pipeline stages in the input path
Two RX FIFOs Perform 2:1 rate conversion on the RX data

• At positive edge of strobe_in signal
• At negative edge of strobe_in signal
Shift Registers Perform the following functions:

• Delay the RcvEn signal in VCO cycle increments
• The read_enable_offset shift register delays the rdata_valid signal
Phase Shift Logics Perform the following functions:

• Delay RcvEn signal in 1/128 VCO cycle increments
• Delay RxDqsNDelayPi/RxDqsPDelayPi signal
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There are five types of delay in the input path. The following table describes the
delays:
Table 40. Types of Delay in the Input Path

Inherent latency Static Captured in pipeline stages from the assertion of rdata_en signal in
core until internal signal, RcvEn, is asserted.
RcvEn delay (internal signal Dynamic You can reconfigure these delays in the control registers. You can
generated from input signal program the RcvEn delay statically or dynamically through the
rdata_en) Additional Receiver Enable Latency settings in the IP Parameter
Editor.
Positive-edge strobe_in delay Dynamic
Negative-edge strobe_in delay Dynamic
read_enable_offset delay Dynamic
Table 41. Input Path Reconfigurable Delays Description

This table lists the reconfigurable input path delays for the PHY Lite for Parallel Interfaces Intel FPGA IP.
Feature Description Bit-field Description Min Max
RxRcvEnPiRank0 • RcvEn delay Bit 10 to bit 7 represents integer 0 15

[10:7] • There are two RxRcvEnPiRank0 number of VCO clock cycles to
registers per lane. One controls the delay RcvEn signal.
lower nibble (6 pins) and the other
RxRcvEnPiRank0 controls the upper nibble of the lane. Bit 6 to bit 0 represents additional 0 127
[6:0] phase shift in RcvEn signal
• In PHY Lite IP, the nibbles cannot be measured in 1/128 of VCO clock
used independently. Both control period.
signals must be programmed to the
same value.
RxDqsNDelayPi • strobe_in delay Phase shift in the negative edge of 0 127

[6:0] • There are two RxDqsNDelayPi and the DQS for each pin measured in
RxDqsPDelayPi for each pin. Each 1/128 of VCO clock period.
pin receives a copy of the DQS and
RxDqsPDelayPi Phase shift in the positive edge of 0 127
can phase-shift each edge of the
[6:0] the DQS for each pin measured in
DQS independently of other pins.
1/128 of VCO clock period.
• Usually both edges should be set to
the same delay value, but different
values can be used to correct
uneven duty cycle.
• The effective range of this delay
setting is up to 1 VCO clock cycle.
read_enable_offset • rdata_valid delay Delay before reading from the RX 0 15

[3:0] • An adjustable setting that changes FIFO measured in number of PHY
the delay before starting to read clock cycles.
from the RX FIFO, effectively
delaying the rdata_valid signal.
• This delay setting is downstream
from the integer portion of the
RcvEn delay, so any additional
RcvEn delay applies to the
rdata_valid signal as well.
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Figure 41. PHY Lite for Parallel Interfaces Intel FPGA IP Input Operation
core_clk
rdata_en 0 F 0 0
data_in H G F E D C B A P O NM L K J I
strobe_in
strobe_in_n
rdata_valid 0 0 0 F 0
data_to_core ABCDEFGH IJKLMNOP
= Signals Truncated
The preceding figure shows an example of RX data transfer in QR DDR. The

data_to_core signal for each pin is eight bits wide. The PHY Lite for Parallel
Interfaces IP uses DDR4 preamble settings, and expects one cycle of preamble by
default. To set the PHY Lite for Parallel Interfaces IP to accept edge-aligned data,
select 90 degrees in the Capture strobe phase shift parameter setting.
To ensure that the IP uses only clock edges associated with valid input data, gate the
receiver off when PHY Lite for Parallel Interfaces IP is not accepting input data. If
there are extra toggling signals or noise on the DQS port, use a refined version of the
received strobe. The gating signal, RcvEn (receiver enable), is derived internally from
the rdata_en signal. Use the RcvEn signal to ungate the DQS gate window by
asserting RcvEn up to one cycle before the first rising edge of DQS, as shown in the
following figure. You require no more than one cycle preamble in the strobe signal.
Figure 42. Ungating DQS Gate Window

This figure shows the ungating of the DQS window by internally asserting the RcvEn signal.
data_in H G
strobe_in
strobe_in_n
RcvEn to be
Asserted
Figure 43. Shutting Off the DQS Gate Window

The following figure shows how disabling RcvEn shuts off the DQS gate.
strobe_in
strobe_in_n
RcvEnPiMod
RcvEnPre
burst counter 0 1 0 1 0 1 0 1 0
In the input path, program the on die termination (ODT) and sense amplifier (SA)
when you dynamically reconfigure the RcvEn delay.
To save power in idle mode, gate off the ODT and SA using two enable signals tapped
from the same shift register as RcvEn.
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Whenever you reconfigure the RcvEn delay, reconfigure the following ODT and SA
settings to ensure that all parts of the receiver circuitry turns on at the correct time:
• DqsSenseAmpDelay
• DqsSenseAmpDuration
• DqSenseAmpDuration
• DqSenseAmpDelay
• DqOdtDuration
• DqOdtDelay
• DqsOdtDuration
• DqsOdtDelay
Adjust these settings for both upper and lower nibbles in the lane according to the
following table.
Table 42. Settings for DQ/DQS ODT/SA Delays

This table lists the settings adjustments for both the upper and lower nibbles in the lane.
RxRcvEnPi[10:7]>>Gear4 (3) DqsOdtDelay DqOdtDelay Dq/Dqs SenseAmpDelay
0 2 3 3
1 3 4 4
2 4 5 5
3 5 6 6
4 6 7 7
5 7 8 8
6 8 9 9
7 9 10 10
When changing the RcvEn coarse delay or RxRcvEnPiRank0[10:7], Intel

recommends that you update read_enable_offset to avoid receiving misaligned
data in the core. The small values of read_enable_offset can cause RX FIFO
underflow, while large values may cause an overflow.
Table 43. Allowed values for read_enable_offset based on RcvEn coarse delay
This table lists the allowed values for read_enable_offset according to the RcvEn coarse delay.
RxRcvEnPiRank0[10:7] Allowed values for read_enable_offset
0, 1, 4, 5, 8, 9, 12, 13 3, 5, 7, 9, 11
2, 3, 6, 7, 10, 11, 14, 15 4, 6, 8, 10, 12
Related Information
Input Path Signals on page 76
For more information about input path signals.
(3) This value is the shifted value of RxRcvEnPi[10:7]. The Gear4 value is always 1.
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If you enable dynamic reconfiguration, you can use an Avalon memory-mapped
interface to reconfigure the input and output delays in the PHY and calibrate the
delays. Through calibration, you can optimize the delay settings to maximize the
capture window. You can access the Avalon memory-mapped interface through the
Calibration Intel FPGA IP. The IP provides an ARM AMBA* AXI4 Lite Interface. You can
connect the Calibration IP to two PHY Lite for Parallel Interfaces IP instances in an I/O
bank.
For differential data, program the output delay settings for both pins in a differential
pair, and the input settings only for the even pin.
You can only reset the PHY by enabling dynamic reconfiguration and writing to the
TrainReset bit. The reset port in PHY Lite for Parallel Interfaces IP is only for power-up
reset.
Figure 44. Connection of the Calibration IP to the PHY Lite for Parallel Interfaces IP
AXI-Lite Interface
Calibration IP
AVMM
Interface
Core Interface IO Interface

PHYLite_ph2
3.2.2.1. Calibration IP
The Calibration IP provides access to the IOPLL and PHY registers through the AXI4-
Lite IP interface. You can connect the Calibration IP to up to two periphery interfaces
and three PLLs.
You must connect PHY Lite IP instances in different I/O banks to different Calibration
IPs.
Connect PHY Lite IP instances in the same I/O bank to the same Calibration IP, but
assign different Instance ID in the IP Parameter Editor to differentiate the base
address of the instances (Rev B only).
Table 44. ARM AMBA* AXI4-Lite IP Interface Signals

This table describes the ARM AMBA* AXI4-Lite IP interface signals.
fbr_axil_clk Input 1 Clock
fbr_axil_rst_n Input 1 Reset
fbr_axil_awaddr Input 27 Write address

continued...
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fbr_axil_awvalid Input 1 Write address valid
fbr_axil_awready Output 1 Write address ready
fbr_axil_wdata Input 32 Write data
fbr_axil_wstrb Input 4 Write strobes
fbr_axil_wvalid Input 1 Write valid
fbr_axil_wready Output 1 Write ready
fbr_axil_bresp Output 2 Write response
fbr_axil_bvalid Output 1 Write response valid
fbr_axil_bready Input 1 Response ready
fbr_axil_araddr Input 27 Read address
fbr_axil_arvalid Input 1 Read address valid
fbr_axil_arready Output 1 Read address ready
fbr_axil_rdata Output 32 Read data
fbr_axil_rresp Output 2 Read response
fbr_axil_rvalid Output 1 Read valid
fbr_axil_rready Input 1 Read Ready
fbr_axil_awprot Input 3 Write protection type
fbr_axil_arprot Input 3 Read protection type
3.2.2.2. Dynamic Reconfigurable Delays
Table 45. Dynamic Reconfigurable Delays

This table lists the delays that you can reconfigure only when the corresponding read or write path is unused.
TxDqDelay 11 Output delay for data and strobe 1/128 of VCO cycle per pin
RxDqsNDelayPi 7 Phase shift in negative edge of DQS 1/128 of VCO cycle per pin
RxDqsPDelayPi 7 Phase shift in positive edge of DQS 1/128 of VCO cycle per pin
RxRcvEnPiRank0 11 RcvEn delay 1/128 of VCO cycle per nibble
DqsSenseAmpDelay 5 DQS sense amplifier delay PHY clock cycle per nibble
DqSenseAmpDuration 4 DQ sense amplifier duration PHY clock cycle per nibble
DqSenseAmpDelay 5 DQ sense amplifier delay PHY clock cycle per nibble
DqOdtDuration 4 DQ ODT duration PHY clock cycle per nibble
DqOdtDelay 5 DQ ODT delay PHY clock cycle per nibble
DqsOdtDuration 4 DQS ODT duration PHY clock cycle per nibble
DqsOdtDelay 5 DQS ODT delay PHY clock cycle per nibble
read_enable_offset 4 Delay before reading from the RX FIFO PHY clock cycle per lane
RxDataVrefL 9 I/O reference voltage lower nibble 1/512 of VCCN per nibble
continued...
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RxDataVrefU 9 I/O reference voltage upper nibble 1/512 of VCCN per nibble
TrainReset 1 Reset the training to clear non-permanent — per lane

states - self clearing
RLTrainingMode 1 Enables read leveling training mode — per lane
DataTrainFeedback_N0 12 Provides feedback for different training steps. — per nibble

In RL Training mode it is simply a counter.
For differential data, program the output delay settings for both pins in a differential
pair, and the input settings only for the even pin.
Before adjusting any delays with dynamic reconfiguration, set the InternalClocksOn
and reset the training. After calibration, set InternalClocksOn back to zero to save
power. Follow these steps:
1. Set InternalClocksOn = 1.
2. Apply Train Reset by setting TrainReset from 0 to 1 and back to 0.
3. Perform calibration.
4. Set InternalClocksOn = 0.
Related Information
Provides the Input Path Signals table that lists the registers address map.
3.2.2.3. Register Map

When you generate the IP, the IP automatically creates the address register map file
(addr_map.vh) and the corresponding C header file. It contains the Avalon memory-
mapped interface registers that you can read and write to use the AXI4-Lite IP
interface of the Calibration IP.
Since these registers include multiple fields for different settings, only change them
with a read-modify-write cycle to preserve the other fields in the register. The address
of a register is 24 bits, consists of an 11-bit base address right-padded with 13’b0,
and a 13-bit offset address left-padded with 11’b0. The padding is done to make the
base address and offset address 24 bits.
In the hardware, the addresses are automatically right-shifted by 2 bits. In the

software view, the 24 bits addresses are padded by two zeros at the right. In the
hardware view, the zero paddings are discarded and the address width gets reduced
to 22 bits.
The base address is calculated as:
Base address = {3’b011, 3 bits instance ID, 2 bits atom ID, 3 bits lane ID},
where atom ID is 2’b00 for Byte control and 2’b01 for Byte. All the reconfigurable PHY
Lite for Parallel Interfaces IP settings are in Byte control. The offset voltage for
different registers in the address map, as well as bit-field description of the registers,
is provided in the table below. As an example, suppose that the PHY Lite for Parallel
Interfaces Instance ID is 0 and group 0 is assigned to lane 0. To change the output
delay of pin 0, you need to modify the
INSTANCE_0_GROUP_0_PIN_00_DDRCRTIMINGCONTROL register.
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The base and offset addresses are derived as:
Base address = {3’b011, 3’b000, 2’b00, 3’b000, 13’b0} = 24’h600000
Offset address = {11’b0, 0x100} = 24’h000100
Full address = Base address + Offset address = 24’h0060_0100
Do not attempt to write to an invalid memory address as it leads to data corruption in

other registers. For guidance, refer to the following table of Avalon memory-mapped
interface address registers. The Avalon memory-mapped interface registers are 32-bit
wide.
Table 46. Address Register Map

This table shows the relevant bit-fields in the registers as they appear in the generated address map.
Register Name Offset Description Bit Field Bit Field Description

Address
(11 bit)
INSTANCE_<n>_GROUP_<n>_PIN_00_DDRCRTIMI 0x100 DQ and DQS [31:21] TxDqDelay

NGCONTROL timing
INSTANCE_<n>_GROUP_<n>_PIN_01_DDRCRTIMI 0xfc
NGCONTROL
INSTANCE_<n>_GROUP_<n>_PIN_02_DDRCRTIMI 0xf8
NGCONTROL
INSTANCE_<n>_GROUP_<n>_PIN_03_DDRCRTIMI 0xf4
NGCONTROL
INSTANCE_<n>_GROUP_<n>_PIN_04_DDRCRTIMI 0xf0 [13:7] RxDqsNDelayPi

NGCONTROL
INSTANCE_<n>_GROUP_<n>_PIN_05_DDRCRTIMI 0xec
NGCONTROL
INSTANCE_<n>_GROUP_<n>_PIN_06_DDRCRTIMI 0xe8
NGCONTROL
INSTANCE_<n>_GROUP_<n>_PIN_07_DDRCRTIMI 0xe4
NGCONTROL
INSTANCE_<n>_GROUP_<n>_PIN_08_DDRCRTIMI 0xe0 [6:0] RxDqsPDelayPi

NGCONTROL
INSTANCE_<n>_GROUP_<n>_PIN_09_DDRCRTIMI 0xdc
NGCONTROL
INSTANCE_<n>_GROUP_<n>_PIN_10_DDRCRTIMI 0xd8
NGCONTROL
INSTANCE_<n>_GROUP_<n>_PIN_11_DDRCRTIMI 0xd4
NGCONTROL
INSTANCE_<n>_PHY_LANE_<n>_UPPER_NIBBLE_ 0x114 RcvEn delay for [10:0] RxRcvEnPiRank0

RCVEN upper nibble
INSTANCE_<n>_PHY_LANE_<n>_LOWER_NIBBLE_ 0x11c RcvEn delay for [10:0] RxRcvEnPiRank0

RCVEN lower nibble
INSTANCE_<n>_PHY_LANE_<n>_UPPER_NIBBLE_ 0x10c DQ/DQS ODT, [31:27] DqsSenseAmpDelay

DATACONTROL2 DQ sense amp
duration upper
continued...
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Register Name Offset Description Bit Field Bit Field Description

Address
(11 bit)
[13:9] DqOdtDelay
[4:0] DqsOdtDelay
INSTANCE_<n>_PHY_LANE_<n>_LOWER_NIBBLE_ 0x110 DQ/DQS ODT, [31:27] DqsSenseAmpDelay

DATACONTROL2 DQ sense amp
duration lower
[13:9] DqOdtDelay
[4:0] DqsOdtDelay
INSTANCE_<n>_PHY_LANE_<n>_UPPER_NIBBLE_ 0x124 Dqs sense amp [29:26] DqsSenseAmpDuration

DQSSENSEAMPDURATION duration upper
nibble
INSTANCE_<n>_PHY_LANE_<n>_LOWER_NIBBLE_ 0x128 ovrd_val for RX [31] rx_ana_ovrd_val

DQSSENSEAMPDURATION path
ovrd_en for RX [30] rx_ana_ovrd_en

path
Dqs sense amp [29:26] DqsSenseAmpDuration

duration lower
nibble
INSTANCE_<n>_PHY_LANE_<n>_RXFIFO 0x13c Read enable [3:0] read_enable_offset

offset change
read valid
delay
INSTANCE_<n>_PHY_LANE_<n>_DATATRAINFEED 0x160 Train reset and [14] TrainReset

BACK training mode
[9] RLTrainingMode
INSTANCE_<n>_PHY_LANE_<n>_TRAINFEEDBACK 0x1f4 Train feedback [23:12] DataTrainFeedback_N1
[11:0] DataTrainFeedback_N0
INSTANCE_<n>_PHY_LANE_<n>_DATACONTROL0 0x104 Internal Clocks [11] InternalClocksOn
INSTANCE_<n>_PHY_LANE_<n>_DATACONTROL6 0x130 VRef I/O [29:21] RxDataVrefL

Voltage
[20:12] RxDataVrefU
3.2.3. I/O Timing

Intel recommends that you design your system for the worst case losses for the PHY
Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 devices.
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Table 47. Worst Case Losses for PHY Lite for Parallel Interfaces Intel FPGA IP for
Agilex 7 Devices
In the following table, assume that the PHY Lite for Parallel Interfaces IP instance communicates with another
PHY Lite for Parallel Interfaces IP instance.
Data Flow Direction Applies to PHY Lite for Parallel Worst Case Losses
Interfaces Intel FPGA IP Mode
Driving (PHY Lite for Parallel Interfaces Output or bi-directional 40% UI

Intel FPGA IP is driving the I/Os)
Receiving (PHY Lite for Parallel Input or bi-directional 35% UI

Interfaces Intel FPGA IP is sampling
the I/Os)
Minimum Receiving Eye Height (PHY Input or bi-directional 100 mV

Lite for Parallel Interfaces Intel FPGA IP
is sampling the I/Os)

You can instantiate the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 M-
Series devices from the Quartus Prime IP Catalog. Intel provides an integrated
parameter editor that allows you to customize this IP to support a wide variety of
applications.
In the IP catalog, access the IP in Libraries ➤ Basic Functions ➤ I/O.
Related Information
• Introduction to Intel FPGA IP Cores
Provides general information about all Intel FPGA IP cores, including
parameterizing, generating, upgrading, and simulating IP cores.
• Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP
version upgrades.
• Project Management Best Practices
Guidelines for efficient management and portability of your project and IP files.

Table 48. Parameter Settings for PHY Lite for Parallel Interfaces Intel FPGA IP
Parameter Values Default Values Description
Parameter
Number of groups 1-8 1 Number of data and strobe groups in the

I/O Instance ID 0-7 0 Use to assign different base addresses to two

instances in the same bank. You must assign
two PHY Lites in the same bank with different
instance IDs using the IP GUI to avoid
overlapping base addresses of the PLL and CPA.
(4)
continued...
(4) The limitation of one PHY Lite instance per I/O bank only in ES device (with OPNs ending R0/
R1).
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Clocks
Interface clock frequency 150 MHz - 1250 533.0 MHz External interface clock frequency.
MHz
Use recommended PLL On, Off On Turn on to calculate the PLL reference clock
reference clock frequency frequency automatically for the best
performance.
Turn off to specify your own PLL reference clock
frequency.
PLL reference clock Dependent on 266.5 MHz PLL reference clock frequency. Feed a clock of
frequency interface clock this frequency to the PLL reference clock input
frequency of the memory interface.
Select the desired PLL reference clock
frequency. The values available depend on the
interface clock frequency or the user clock rate
logic.
VCO clock frequency Calculated 1066.0 MHz The PLL calculates the VCO clock frequency
internally by PLL automatically based on the interface clock and
the core clock rate.
Core clock frequency Calculated 266.5 MHz The PLL calculates the core clock frequency
internally by PLL automatically based on clock rate of user logic.
Use dynamic On, Off Off Enables an Avalon memory-mapped interface

reconfiguration that allows you to dynamically reconfigure the
PHY Lite for Parallel Interfaces IP settings.
I/O Settings
1.2-V POD strobe and data pins written.
1.1-V POD
1.2-V HSTL
1.2-V HSUL
1.1-V LVSTL
1.05-V LVSTL
Reference clock I/O Single-ended, Single-ended Specifies the reference clock I/O configuration.
with on-chip
termination,
True Differential
without on-chip
termination
Group<x> - these parameters are set on a per group basis
Group<x> Pin Settings
Pin type Input, Output, Bidirectional Direction of data pins.

Bidirectional
Pin width 1 to 22 8 Number of pins in this data/strobe group. The

pin width includes the number of strobe pins.
DDR/SDR DDR, SDR DDR Double/single data rate.
Data Configuration Differential, Differential Selects the type of data.

Single-ended
continued...
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Group<x> Input Path Settings
Additional receiver enable 0 to 15 0 The number of external interface clock cycles to

latency delay the internal receiver enable signal in
addition to the inherent latency in the receiver
enable path. The valid range depends on the
user clock rate and memory interface frequency
set in the General tab.
Capture strobe phase 0, 45, 90 90 Internally phase-shift the input strobe relative
shift to the input data.
Group<x> Output Path Settings
Additional write latency 0 to 15 0 The number of external interface clock cycles to

delay the output data in addition to the inherent
write latency. The valid range is the set of sub
core clock cycles, which is dependent on the
user clock rate set in the General tab. To delay
by a larger amount, register the data in the
core.
Output strobe phase 0, 45, 90, 135, 90 Phase shift of the output strobe relative to the
180 output data.
Group<x> General Strobe Settings

Strobe configuration Differential, Differential Selects the type of strobe.

Single-ended For a list of supported I/O standards, refer to
the related information..
Group<x> OCT Settings
50 ohm with Disables the Use Default OCT Values
calibration, parameter to select the desired input OCT value.
50 ohm without
calibration,
60 ohm with
calibration
Output OCT Value 34 ohm with 40 ohm with Specifies the group's data and strobe output
34 ohm without Disable the Use Default OCT Values
calibration, parameter to select the desired output OCT
40 ohm with value.
calibration,
40 ohm without
calibration
Pin Placement
continued...
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RZQ Index 38, 62 38 Specifies the RZQ pin index in the I/O bank. It
should be reserved at pin 38 or pin 62.
Pin Parameter Settings On, Off Off By default, all the data pins are placed in an
Enable manual location of ordered-dense format i.e., no gap pins. Enable
data pins this option if data pins are required to be spaced
out i.e. with gap-pins. Adhere to all restrictions
in the user guide.
Pin Placement Settings Comma separated — Provides a CSV list of pin locations one per each
values data pin. For example, a value of 0, 1, 8, 9
places data[0], data[1], data[2], data[3] on
pin0, pin1, pin8, pin9 of IO48 Tile respectively,
leaving pin2-7 not used for data. These unused
pins may be used for PLL Reference Clocks, RZQ
Pin or Strobes (subject to the constraints
mentioned in the User Guide).
Related Information
For more information about the supported I/O standards in Agilex 7 M-Series
devices.
• Pin Placement Restrictions on page 78
For guidelines on pin placement in Agilex 7 M-Series devices.
For more information about the supported I/O standards in Intel Agilex
devices.
• Agilex 7 F-Series and I-Series I/O Sub-bank Interconnects on page 88
Provides the physical sub-bank ID for pin placement.
• Guidelines: Group Pin Placement on page 123
For more information about pin placement guidelines in Agilex 7 devices.
3.3.2. Signals

synchronous with group_strobe_in to ensure that the
reset_n Input 1 Resets the interface during power-up reset. To reset the PHY, you
must enable dynamic reconfiguration and write to the TrainReset
bit.
interface_locked Output 1 The interface_locked signal from the PHY Lite for Parallel
Interfaces IP to the core logic. This signal indicates that the PLL
and PHY circuitry are locked.
continued...
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Data transfer should start after the assertion of this signal and
control signals should be kept at zero before interface_locked
is asserted.
rzq Input 1 This pin is visible if you select an I/O standard with on-chip
termination (OCT) in the IP parameter editor.
core_clk_out Output 1 Use this core clock in the core-to-periphery transfer of soft logic
data and control signals.
frequency and clock rate of user logic parameters.

Output path signals are signals that are available when you set Pin Type to either Output or Bidirectional.
The <n> in the signal names in the following table represents the group number in the IP
group_<n>_data_from_core Input Quarter rate- Data signal from the Intel FPGA core.
DDR: 8 x Synchronous to the core_clk_out output
PIN_WIDTH from the IP.
Half rate-DDR: 4
x PIN_WIDTH
Full rate-DDR: 2 x
PIN_WIDTH
Quarter-rateSDR:
4 x PIN_WIDTH
Half rate-SDR: 2
x PIN_WIDTH
Full rate-SDR: 1 x
PIN_WIDTH
group_oe_from_core Input Quarter-rate: 4 Output enable signal from the FPGA core.
Half-rate: 2 Synchronous to the core_clk_out output
Full-rate: 1 from the IP.
Each group has a separate output enable.
group_strobe_out_en Input Quarter-rate: 4 Strobe output enable from FPGA core.

Half-rate: 2 Synchronous to the core_clk_out output
Full-rate: 1 from the IP.
Each group has separate strobe enable.
group_strobe_from_core Input Quarter-rate:8 Strobe pattern from core. Simple strobe

Half-rate:4 pattern can be generated by this signal
with 8’h55 values.
Full-rate:2
group_<n>_data_out Output/ 1 to 22 Data output from the IP. Synchronous to

/group_<n>_data_io Bidirectional the group_<n>_strobe_out or
group_<n>_strobe_io output from the
IP.
If Pin Type is set to Output, the
group_<n>_data_out signals are used.
If Pin Type is set to Bidirectional, the
group_<n>_data_io signals are used.
continued...
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group_<n>_data_out_n Output/ 1 to 22 Differential data output from IP.

/group_<n>_data_io_n Bidirectional Synchronous to the
group_<n>_strobe_out_n or
group_<n>_strobe_io_n output from
the IP.
group_<n>_strobe_out/ Output/ 1 Positive output strobe from the IP. If the

group_strobe_io/ Bidirectional Pin Type is set to Output, the
group_<n>_strobe_io group_<n>_strobe_out signal is used.
If the Pin Type is set to Bidirectional,
the group_<n>_strobe_io signal is
used.
group_<n>_strobe_out_n / Output/ 1 Negative output strobe from the IP.

group_<n>_strobe_io_n Bidirectional This is used if Strobe Configuration is
set to Differential.
group_<n>_strobe_out_n signal is
used. If the Pin Type is set to
Bidirectional, the

Input path signals are signals that are available when you set Pin Type to Input or Bidirectional. The <n> in
the signal names in the following table represent the group number in the IP.
group_<n>_data_to_core Output Quarter rate-DDR: 8 Output data to the core logic. Valid on
x PIN_WIDTH group_<n>_rdata_valid. Synchronous to the
Half rate-DDR:4 x core_clk_out output from the IP.
PIN_WIDTH
Full rate-DDR: 2 x
PIN_WIDTH
Quarter-rateSDR: 4
x PIN_WIDTH
Half rate-SDR: 2 x
PIN_WIDTH
Full rate-SDR: 1 x
PIN_WIDTH
group_rdata_en Input Quarter-rate: 4 Read enable signal.

Half-rate: 2 This signal is set to high after a read command is
Full-rate: 1 issued. Synchronous to the core_clk_out output
from the IP.
When using the IP as a receiver, assert this signal
after interface_locked signal is asserted and
group_strobe_in is stable.
Each group has separate read enable.
group_<n>_rdata_valid Output Quarter-rate: 4 Read valid signal

Half-rate: 2 This signal determines which data are valid when
Full-rate: 1 reading from RX FIFO.
Synchronous to the core_clk_out output from
the IP.
group_<n>_data_in/ Input/ 1 to 22 Input data from external device. Synchronous to

group_<n>_data_io Bidirectional the group_<n>_strobe_in or
group_<n>_strobe_io input. The first data_in
continued...
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must be associated with positive edge of

group_<n>_strobe_in/
group_<n>_data_in ports are used. If the pin
type is set to Bidirectional, the
group_<n>_data_io ports are used.
group_<n>_data_in_n/ Input/ 1 to 22 Differential input data from external device.

group_<n>_data_io_n Bidirectional Synchronous to the group_<n>_strobe_in_n or
group_<n>_strobe_io_n output from the IP,
group_<n>_strobe Input/ 1 Input strobe from external device. If the pin type is
_in/ group_<n>_strobe Bidirectional set to Input, the group_<n>_strobe_in signal
is used. If the pin type is set to Bidirectional, the
_io group_<n>_strobe_io signal is used.
group_<n>_strobe Input/ 1 Negative strobe from external device. This is used

_in_n/ group_<n>_strobe Bidirectional if Strobe Configuration is set to Differential. If
the pin type is set to Input, the
_io_n group_<n>_strobe_in_n signal is used. If the
pin type is set to Bidirectional, the
3.4. I/O Standards

The PHY Lite for Parallel Interfaces Intel FPGA IP allows you to set I/O standards on
the pins associated with the generated configuration. The I/O standard controls the
available strobe configurations and OCT settings for all groups. One RZQ group
supports up to two different output terminations and one input termination. RZQ pin
cannot be used as data pin.
Table 52. I/O Standards and Termination Values for Agilex 7 M-Series Devices
I/O Standard Valid Input Input Terminations Valid Output Output Terminations RZQ
Terminations (Ω) without Calibration (Ω) Terminations (Ω) without Calibration (Ω) (Ω)
SSTL-12 50, 60 50 34, 40 34, 40 240
1.2-V POD 40, 50, 60 50 34, 40 34, 40 240
1.1-V POD 40, 50, 60 50 34, 40 34, 40 240
1.2-V HSTL 50, 60 50 34, 40 34, 40 240
1.2-V HSUL — — 34, 40 34, 40 240
1.1-V LVSTL 40, 50, 60 50 34, 40 34, 40 240
1.05-V LVSTL 40, 50, 60 50 34, 40 34, 40 240
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3.4.1. Design Guidelines
3.4.1.1. DQS Trees
The PHY Lite for Parallel Interfaces Intel FPGA IP supports two DQS trees, namely an
x8 tree that span over one lane and an x16 tree that spans over two adjacent lanes,
as described in the following table:
Table 53. DQS Trees in Agilex 7 M-Series Devices

DQS Tree Lane Used Group Size Strobe Pins
X8 Any lane 1-10 Pins 4, 5
X16 [0,1] 1-22 Pins 4, 5 of the even lane

[2,3]
[4,5]
[6,7]
For single-ended strobe, only pin 4 is used as DQS. The remaining strobe pin (pin 5)
cannot be used as data.
3.4.1.2. Pin Placement Restrictions
Follow these guidelines to place the PHY Lite for Parallel Interfaces Intel FPGA IP group
pins:
1. Assign each lane to only one group. Each group is either mapped to one lane (x8
mode) or two lanes (x16 mode). When using x16 DQS tree, the first lane should
be an even lane.
2. If using termination with calibration, reserve pin 38 or 62 for RZQ. RZQ is a 240
ohm resistor that you attach it to a specific pin as an impedance reference to
calibrate driving and termination impedances to avoid signal reflection. One RZQ
group can support up to two different output terminations and one input
termination. RZQ pin cannot be used as data pin.
3. No input or bidirectional pins can be placed in the same lane as RZQ.
4. Place differential data on two adjacent pins. The first pin should be an even pin.
The following shows two differential data pins placed on pins 2 and 12, and
occupying 4 pins in total. This example uses an x16 DQS tree since the data pins
span over two lanes.
5. Differential refclk is not supported in the same lane as PHY Lite IP for the LVSTL
I/O standard.
6. For both auto and manual pin placements, ensure that the ref_clk pins are
reserved only in any of the following eight pins:
• Pins 34, 35 (Lane 2)
• Pins 36, 37 (Lane 3)
• Pins 58, 59 (Lane 4)
• Pins 60, 61 (Lane 5)
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7. PHY Lite IP instances in different I/O banks must be connected to different

Calibration IPs.
8. PHY Lite IP instances in the same I/O bank will be connected to the same
Calibration IP, but different Instance ID must be assigned in the IP Parameter
Editor to differentiate the base address of the instances (Rev B only).
9. In the input-only pins with I/O standard, SSTL-12 or HSTL-12, toggle rddata_en
to benefit from On-Die Termination (ODT) rotation. If RX is enabled 100% of the
time (if rddata_en is not toggled), only 32 data pins are allowed.
Rotation happens when rddata_en goes low. However, if the receiving data in
bursts and the burst sizes are not equal, the maximum imbalance should be 40%
to 60% to get credit for the first row in On-Die Termination (ODT).
To support 100% Activity Factor (AF), toggle rddata_en at least 80% of the time
with a maximum imbalance of 40% to 60%.
Figure 45. Differential Data Pin Placement
Figure 46. On-Die Termination (ODT) Rotation
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Table 54. On-Die Termination (ODT)

Case Maximum Input Pins
90%<AF≤100% 32
80%<AF≤90% 38
70%<AF≤80% 48
60%<AF≤70% 58
0%<AF≤60% 96
3.5. Design Example

The PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 M-Series devices is able
to generate a design example that matches the same configuration chosen for the IP.
The design example is a simple design that does not target any specific application;
however you can use the design example as a reference on how to instantiate the IP
and what behavior to expect in a simulation.
Note: The .qsys files are for internal use during design example generation only. You should
not edit the files.
3.5.1. Generating the Design Example

To generate a design example, click Generating Example Design in the IP
Parameter Editor.
The software generates a user-defined directory in which the design example files
reside.
Intel FPGA IP:
• Without dynamic reconfiguration
• With dynamic reconfiguration
Table 55. PHY Lite for Parallel Interfaces Intel FPGA IP Design Example Variants
Consists of PHY Lite for Parallel Interfaces Intel

ed_synth.qsys (synthesis only)
FPGA IP instance with Calibration IP.
On
ed_sim.qsys (simulation only) FPGA IP instance with Calibration IP, IOSSM Tester,
Dynamic Tester Core, and Tester I/O
Reconfiguration
ed_synth.qsys (synthesis only)
FPGA IP instance.
Off
ed_sim.qsys (simulation only)
FPGA IP instance with Tester Core and Tester I/O.
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Prime software generates a design example of PHY Lite for Parallel Interfaces Intel
FPGA IP without a dynamic reconfiguration module. This design example consists of
simulation and synthesis design files.
3.5.1.1.1. Generating the Synthesis Design Example

generation:

rdata_en data_io
oe_from_core Phylite_ph2 strobe_io
strobe_out_en strobe_io_n
ninit_done Reset Handler
Init
3.5.1.1.2. Generating the Simulation Design Example

simulation tools. Each subdirectory contains the specific scripts to run simulation using
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simple one group PHY Lite for Parallel Interfaces Intel FPGA IP instantiation in the
testbench.
Figure 48. High-Level View of the Simulation Design Example without Dynamic
Reconfiguration
Example Design
Tester
I/O Interface
I/O Model
Pass/Fail
PHYLite_ph2
Core Interface
PHY Lite Interface
3.5.1.2. Dynamic Reconfiguration Design Examples

generation:

for your IP configuration with Calibration IP as the interface for the Avalon memory-
mapped interface calibration addresses.
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Figure 49. High-Level View of the Synthesis Design Example with Dynamic
Reconfiguration
rdata_en data_io
strobe_out_en Phylite_ph2 strobe_io_n
ninit_done Reset Handler calbus_param_table
Init calbus_O
calbus_readdata
AXI-Lite Interface Cal IP

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Figure 50. High-Level View of the Simulation Design Example with Dynamic
Reconfiguration
Example Design
Tester
AXI-Lite Interface
Calibration IP IOSSM Tester
Avalon
Memory-
Mapped
Interface
I/O Interface
I/O Model
Pass/Fail
PHYLite_ph2 Core Interface PHY Lite Interface
3.5.2. Verifying Simulation Design Examples using Tester IP

The design examples, both with dynamic reconfiguration and without dynamic
reconfiguration, use Tester IP to verify PHY Lite for Parallel Interfaces Intel FPGA IP
functionality. The tester exercises read and write operations to the PHY Lite for Parallel
Interfaces Intel FPGA IP to verify its functionality.
At a high level, the tester is a state machine that repeatedly performs read/write
operations. Disabling a test causes the corresponding tester state to be skipped. The
following lists the tester states in the order they are performed:
1. STATE_INIT: Initialization
2. STATE_TEST_CALBUS: Calibration when dynamic reconfiguration is enabled
3. STATE_TEST_WRITE: Enabled only in output and bidir modes
4. STATE_TEST_READ: Enabled only in input and bidir modes
5. STATE_DONE: All bursts of data successfully transmitted
The following table shows the port connections between the PHY Lite for Parallel
Interfaces Intel FPGA IP and tester. Tester ports not shown in the table are pass_out
and fail_out which signal the success or failure of the test. Multiple PHY Lite for
Parallel Interfaces Intel FPGA IP groups can be tested by daisy chaining testers and
connecting pass_out and fail_out of each tester to the pass_in and fail_in ports of the
next tester in chain. The Calbus ports are not shown in the table as well.
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Table 56. PHY Lite for Parallel Interfaces Intel FPGA IP for M-Series Devices and Tester
Port Connections
This table lists the PHY Lite and Tester port connections.
Intel FPGA IP Ports
group_X_data_from_core GROUP_DATA_WIDTH group_data_from_core
group_X_oe_from_core GROUP_CTRL_WIDTH group_oe_from_core
group_X_strobe_from_core GROUP_STROBE_WIDTH group_strobe_from_core

PHY Lite for Parallel Interfaces
Intel FPGA IP interface group_X_strobe_out_en GROUP_CTRL_WIDTH group_strobe_out_en
submodule
group_X_data_to_core GROUP_DATA_WIDTH group_data_to_core
group_X_rdata_en GROUP_CTRL_WIDTH group_rdata_en
group_X_rdata_valid GROUP_CTRL_WIDTH group_rdata_valid
group_X_data_out GROUP_PIN_WIDTH group_data_out
group_X_data_out_n GROUP_PIN_WIDTH group_data_out_n
group_X_data_in GROUP_PIN_WIDTH group_data_in
group_X_data_in_n GROUP_PIN_WIDTH group_data_in_n
group_X_data_io GROUP_PIN_WIDTH group_data_io
group_X_data_io_n GROUP_PIN_WIDTH group_data_io_n

I/O model
group_X_strobe_out group_strobe_out
group_X_strobe_out_n group_strobe_out_n
group_X_strobe_in group_strobe_in
N/A
group_X_strobe_in_n group_strobe_in_n
group_X_strobe_io group_strobe_io
group_X_strobe_io_n group_strobe_io_n
The tester instantiates the following three submodules:

• I/O model: Connects to the PHY Lite for Parallel Interfaces Intel FPGA IP I/O
interface. Includes two instances of prbs channel, one to generate random pattern
for read tests, and one to check the received pattern in the write tests.
• PHY Lite for Parallel Interfaces Intel FPGA IP interface: Connects to the PHY Lite
for Parallel Interfaces Intel FPGA IP core interface. Includes two instances of prbs
channel, one to generate random pattern for write tests, and one to check
received pattern in the read tests. Reframing logic is also included in this module.
• IOSSM tester: Exposes an AXI4-Lite IP Interface and performs reads and writes to
change the TX delay on pin 0. Only available for simulation example design with
dynamic reconfiguration.
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Send Feedback

7 F-Series and I-Series Devices

features.
changes.
Table 57. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-
Series Devices Release Information
Item Description
IP Version 22.3.0
Related Information

The PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 devices utilizes the I/O
banks in Agilex 7 F-Series and I-Series devices. Each I/O bank has two I/O sub-banks
in each device. The top sub-bank is placed near the edge of the die, and the bottom
sub-bank is placed near the FPGA core.
4. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-Series Devices
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Each sub-bank contains the following components:

• Hard memory controller
• I/O PLL and PHY clock trees
• DLL
• Input DQS/strobe trees
• 48 pins, organized into four I/O lanes of 12 pins each
Figure 51. Agilex 7 F-Series and I-Series I/O Bank Structure (Die Top View)
This figure shows the I/O bank structure of the Agilex 7 F-Series and I-Series devices. The figure shows the
view of the die as shown in the Quartus Prime Chip Planner. In the Pin Planner, this corresponds to the
"Bottom View". Different device packages have different number of I/O banks. Refer to the device pin-out files
for available I/O banks and the locations of the SDM and HPS shared I/O banks for each device package.
I/O Center
OCT
Top
I/O Lane I/O Lane I/O PLL I/O VR I/O Lane I/O Lane
Sub-Bank
Hard Memory
Controller
Hard Memory
Controller
Bottom
Sub-Bank I/O Lane I/O Lane I/O PLL I/O VR I/O Lane I/O Lane
OCT
I/O Center
HPS Shared GPIO Bank RX SERDES & DPA

SDM Shared GPIO Bank TX SERDES
3A 3B 3E 3F 3C 3D HPS
GPIO Bank Differential RX buffer pair
Top I/O Bank Row
HPS I/O Bank Differential TX buffer pair
SDM I/O Bank NOTE: If you use SERDES, the differential RX and TX buffer
pairs are unidirectional, as shown in this figure.
Bottom I/O Bank Row If you do not use SERDES, you can configure each
differential I/O buffer as RX or TX, with a maximum
SDM 2A 2B 2E 2F 2C 2D of three differential RX pairs in each lane.
I/O Center
OCT
I/O Lane I/O Lane I/O PLL I/O VR I/O Lane I/O Lane Bottom
Hard Memory Sub-Bank
Controller
Hard Memory
Controller Top
I/O Lane I/O Lane I/O PLL I/O VR I/O Lane I/O Lane Sub-Bank
OCT
I/O Center
Related Information
• Design Guidelines on page 123
• I/O Bank Architecture in Agilex 7 Devices
For more information about Intel Agilex I/O bank architecture
• External Memory Interfaces Agilex 7 FPGA IP User Guide
For more information about PLL reference clock.
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4.2.1. Agilex 7 F-Series and I-Series I/O Sub-bank Interconnects

There are interconnects between the sub-banks which chain the sub-banks into a row.
The following figures show how I/O lanes in various sub-banks are chained together to
form the top and bottom I/O rows in various Agilex 7 device variants. These figures
represent the top view of the silicon die that corresponds to a reverse view of the
device package. Each sub-bank is labeled with an ID number to facilitate pin
placement.
Figure 52. Sub-bank Ordering with ID in Top I/O Row in Agilex 7 AGF006 and AGF008,
Package R16A
1 Bank 3A
Top Sub-bank
2 Bank 3C 4 Bank 3D
Lane 3 Lane 2 Lane 1 Lane 0 Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3
Z
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
Lane 3 Lane 2 Lane 1 Lane 0 E Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
0 Bottom Sub-bank 3 5
Not Bonded
Figure 53. Sub-bank Ordering with ID in Bottom I/O Row in Agilex 7 AGF006 and
AGF008, Package R16A
1 Bank 2B
Bottom Sub-bank
3 Bank 2C 5 Bank 2D
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
Z
I
P
P
E Lane 3 Lane 2 Lane 1 Lane 0 Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3
R
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
0 Top Sub-bank 2 4
Not Bonded
Package R24B
Bank 3A Bank 3B Bank 3C Bank 3D
1 Top Sub-bank 3 4 6
Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3
Z
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
E
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
0 Bottom Sub-bank 2 5 7
88
683716 | 2024.04.01
AGF014, Package R24B
Z
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
I
P
P
E
R
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
Package R24C
1 Bank 3A
Top Sub-bank
2 Bank 3C 4 Bank 3D
Z
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
Lane 3 Lane 2 Lane 1 Lane 0 E Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
AGF008, Package R24C
1 Bank 2B
Bottom Sub-bank
3 Bank 2C 5 Bank 2D
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
Z
I
P
P
R
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
0 Top Sub-bank 2 4
Figure 58. Sub-bank Ordering with ID in Top I/O Row in Agilex 7 AGF014, Package R24C
1 Bank 3A
Top Sub-bank
3 Bank 3B 5 Bank 3E 7 Bank 3F 8 Bank 3C 10 Bank 3D
Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3
Z
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 E Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
0 Bottom Sub-bank 2 4 6 9 11
89
683716 | 2024.04.01
Figure 59. Sub-bank Ordering with ID in Bottom I/O Row in Agilex 7 AGF014, Package
R24C
0 Bank 2A
Bottom Sub-bank
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
Z
I
P
P
Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 E Lane 3 Lane 2 Lane 1 Lane 0 Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3
R
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
1 Top Sub-bank 3 5 6 8 10
Not Bonded
Package R24C
Z
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
E
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
0 Bank 2B
Bottom Sub-bank
2 Bank 2E 5 Bank 2C 7 Bank 2D
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
Z
I
P
P
Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 E Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3
R
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
Not Bonded
Package R24C
Bank 3A Bank 3B
0 Top Sub-bank 2
Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3
Z
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
E
R
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
1 Bottom Sub-bank 3
90
683716 | 2024.04.01
1 Bank 2F
Bottom Sub-bank
3 Bank 2C 5 Bank 2D
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
Z
I
P
P
R
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
0 Top Sub-bank 2 4
Package R24C
1 Bank 3A
Top Sub-bank
Z
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
0 Bank 2A
Bottom Sub-bank
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
Z
I
P
P
R
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
Not Bonded
Package R25A
0 Bank 3A
Top Sub-bank
2 Bank 3B
Z
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
E Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3
R
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
1 Bottom Sub-bank 3
Not Bonded
91
683716 | 2024.04.01
AGF023, Package R25A
1 Bank 2F
Bottom Sub-bank
3 Bank 2C 5 Bank 2D
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
Z
I
P
P
R
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
0 Top Sub-bank 2 4
Not Bonded
Figure 68. Sub-bank Ordering with ID in Top I/O Row in Agilex 7 AGF022 and AGF027
Devices, Package R25A
1 Bank 3A
Top Sub-bank
Z
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
Not Bonded
AGF027 Devices, Package R25A
0 Bank 2A
Bottom Sub-bank
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
Z
I
P
P
R
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
Not Bonded
Devices, Package R31C
Bank 3A Bank 3B
0 Top Sub-bank 2
Z
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
E
R
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
1 Bottom Sub-bank 3
92
683716 | 2024.04.01
AGF023 Devices, Package R31C
1 Bank 2F
Bottom Sub-bank
3 Bank 2C 5 Bank 2D
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
Z
I
P
P
R
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
0 Top Sub-bank 2 4
Devices, Package R31C
1 Bank 3A
Top Sub-bank 3 Bank 3B
5 Bank 3E
7 Bank 3F
8 Bank 3C
10 Bank 3D
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
Z
I
P
P
E
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
Not Bonded
0 Bank 2A
Bottom Sub-bank 2 Bank 2B
4 Bank 2E
7 Bank 2F
9 Bank 2C
11 Bank 2D
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0 -11
PIN 0 -11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
Z
I
P
P
E
R
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
Not Bonded
Figure 74. Sub-bank Ordering with ID in Top I/O Row in Agilex 7 AGI019 and AGI023,
Package R18A
Bank 3A Bank 3B
0 Top Sub-bank 2
Z
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
E
R
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
1 Bottom Sub-bank 3
93
683716 | 2024.04.01
Figure 75. Sub-bank Ordering with ID in Bottom I/O Row in Agilex 7 AGI019 and
AGI023, Package R18A
1 Bank 2F
Bottom Sub-bank
3 Bank 2C 5 Bank 2D
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
Z
I
P
P
R
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
0 Top Sub-bank 2 4
Figure 76. Sub-bank Ordering with ID in Top I/O Row in Agilex 7 AGI022 and AGI027
1 Bank 3A
5 Bank 3E
7 Bank 3F
8 Bank 3C
10 Bank 3D
Z
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
Not Bonded
AGI027 Devices, Package R29A
0 Bank 2A
4 Bank 2E
7 Bank 2F
9 Bank 2C
11 Bank 2D
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
Z
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
I
P
P
R
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
Not Bonded
Figure 78. Sub-bank Ordering with ID in Top I/O Row in Agilex 7 AGI027 Devices,
Package R29B
1 Bank 3A
5 Bank 3E
7 Bank 3F
8 Bank 3C
10 Bank 3D
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
Z
I
P
Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 Lane 3 Lane 2 Lane 1 Lane 0 P Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3
E
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
R
PIN 0-11
Not Bonded
94
683716 | 2024.04.01
Figure 79. Sub-bank Ordering with ID in Bottom I/O Row in Agilex 7 AGI027 Devices,
Package R29B
0 Bank 2A
4 Bank 2E
7 Bank 2F
9 Bank 2C
11 Bank 2D
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
Z
I
P
P Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3
E
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
R
Not Bonded
Package R29D
Z
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
E
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
Not Bonded
Package R29D
Z
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
I
P
P
E
R
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
Not Bonded
1 Bank 3A
5 Bank 3E
7 Bank 3F
8 Bank 3C
10 Bank 3D
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
Z
I
P
P
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
Not Bonded
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0 Bank 2A
4 Bank 2E
7 Bank 2F
9 Bank 2C
11 Bank 2D
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
Z
I
P
P
R
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
Not Bonded
Devices, Package R31B
Bank 3A Bank 3B
0 Top Sub-bank 2
Z
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
E
R
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
1 Bottom Sub-bank 3
AGI023 Devices, Package R31B
1 Bank 2F
Bottom Sub-bank
3 Bank 2C 5 Bank 2D
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
Z
I
P
P
R
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
0 Top Sub-bank 2 4
1 Bank 3A
5 Bank 3E
7 Bank 3F
8 Bank 3C
10 Bank 3D
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
Z
I
P
P
E
R
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
Not Bonded
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0 Bank 2A
4 Bank 2E
7 Bank 2F
9 Bank 2C
11 Bank 2D
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
Z
I
P
P
E
R
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
Not Bonded
Package R31B
Z
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
E
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
Not Bonded
Package R31B
Z
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
PIN 0-11
I
P
P
E
R
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
Not Bonded
Bank 3A Bank 3B Bank 3C
1 Top Sub-bank 3 4
Z
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
E
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
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Bank 3A Bank 3B Bank 3C
1 Top Sub-bank 3 4
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
E
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 36-47
PIN 24-35
PIN 12-23
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 0-11
PIN 0-11
Related Information
External Memory Interfaces Intel Agilex FPGA IP User Guide.
4.2.2. Agilex 7 F-Series and I-Series Input DQS/Strobe Tree

The input DQS/strobe tree is a balanced clock network that distributes the read
capture strobe (such as DQS/DQS#) from the external device to the read capture
registers inside the I/Os.
The DQS/strobe tree is used for input and bidirectional pin types.
Within every bank, only certain physical pins at specific locations can drive the input
DQS/strobe trees. The pin locations that can drive the input DQS/strobe trees vary,
depending on the size of the group.
Table 58. Pins Usable as Read Capture Clock / Strobe Pair

Sub-bank Lane used by Data Pins Group Size Strobe Pins (5)(6)
0 x8 / x9 Pin 4, 5
1 x8 / x9 Pin 16, 17
2 x8 / x9 Pin 28, 29
3 x8 / x9 Pin 40, 41
0, 1 x18 Pin 4, 5
2, 3 x18 Pin 28, 29
1, 2 x36 Pin 16, 17
0, 1, 2 x36 Pin 16, 17
1, 2, 3 x36 Pin 16, 17
0, 1, 2, 3 x36 Pin 16, 17
To target the lower/upper half of GPIO, use the Physical Sub-Bank ID as shown in
the diagrams in the Agilex 7 for F-Series and I-Series I/O Sub-bank Interconnects
section. For example, if the placement for x18 of sub-bank 0, 1 targets at the top sub-
(5) For strobe pin, use either pin for single-ended and use both pins for differential.
(6) In quarter rate, unused strobe pin cannot be used as data pins.
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bank of bank 2D in Agilex 7 AGF012 and AGF014 devices, package R24B, enter
Physical Sub-Bank ID = 6 at the Pin Placement tab in the PHY Lite IP parameter
editor in the Quartus Prime Pro Edition software.
The PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-Series
devices does not permit QSF-based pin assignment. Instead, the pin placement
automatically occurs based on the information from Data/Strobe Pin Placement
Within Sub-Bank at the Pin Placement tab in the PHY Lite IP parameter editor in
the Intel Quartus Prime software.
Figure 92. Pin Placement Example
In quarter rate mode, the unused strobe pins are always reserved. For example, if you
use lanes 0, 1, 2, and 3, then pins 16 and 17 (pin index 4 and 5 in lane 1) are used
for strobe signals. If you use lanes 2 and 3, then pins 28 and 29 (pin index 4 and 5 in
lane 2) are used for strobe signals. You cannot use the unused strobe pins.
Figure 93. Pin Placement Example in Quarter Rate Mode
In half rate mode, you can assign the unused strobe pins as data pins. For example, if
you use lanes 0, 1, 2, and 3, only pins 16 and 17 (pin index 4 and 5 in lane 1) are
used for strobe signals. If you use lanes 2 and 3, only pins 28 and 29 (pin index 4 and
5 in lane 2) are used for strobe signals.
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Figure 94. Pin Placement Example in Half Rate Mode
4.2.3. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series
and I-Series Devices Top Level Interfaces
devices consists of the following ports:
• Core data and control (divided into input and output paths)
• I/O (divided into input and output paths)
Figure 95. Top-Level Interface

This figure shows the top-level diagram of the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-
Series and I-Series devices interface.
Intel FPGA Device
PHY Lite for Parallel Interfaces Intel FPGA IP Core

Group
phy_clk_phs I/O Lane
ref_clk PLL phy_clk
(From external oscillator) I/O Lane
core_clk_out Tile Control

Intel FPGA Core Logic
}
I/O Lane group_<n>_data_in/out/io
Data to/from Core VCO/Interpolator (From /to external devices)
I/O Lane group_<n>_strobe_in/out/io
Legend
Reference Clock PHY Clock
Core Clock Interface Clock
Related Information
For more information about the IP output path.
For more information about the IP input path.
For more information about the IP data, control, and I/O interfaces.
4.2.3.1. Clocks
The PHY Lite for Parallel Interfaces Intel FPGA IP sources a reference clock from a
dedicated clock pin to the PLL inside the IP. This PLL provides four clock domains for
the output and input paths.
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Table 59. PHY Lite for Parallel Interfaces Intel FPGA IP Clock Domains
Core clock The IP generates this clock internally and uses it for all transfers between the FPGA core fabric
and I/O banks. The clock phase alignment (CPA) circuitry keeps the clock in phase with the PHY
clock for transfers between the core and the periphery.
PHY clock The IP uses this clock internally for PHY circuitry running at the same frequency as the core
clock.
VCO clock The PLL generates this clock internally. The input and output paths use the VCO clock to
generate interpolator delays that compensates for PVT variations.
FPGA IP for Agilex 7 F-Series and I-Series Devices
Core Clock Speed Grade –1 (MHz) Speed Grade –2 (MHz) Speed Grade –3 (MHz)
Rate
Min Max Min Max Min Max
Quarter 100 1,200 100 933 100 933
Half 100 800 100 666 100 600
Full 100 400 100 333 100 300
4.2.3.1.1. Clock Frequency Relationships
The following equations describe the relationships between the clock domains
available in the PHY Lite for Parallel Interfaces Intel FPGA IP.
Core Clock Rate = Interface clock frequency / Core clock frequency
VCO frequency Multiplier Factor = VCO clock frequency(7) / Interface clock frequency
The output path consists of a FIFO and an interpolator. As described in the following
figure, data coming from the core together with relative enable signals are written into
the Write FIFO synchronously with phy_clk. The VCO clock generates the
interpolator_clk which is used to generate the desired output delay.
Table 61. Blocks in Output Path

This table lists the blocks in the output path.
Block Description
Write FIFO Serializes the output data from the core with a serialization factor of up to 8 (in DDR quarter-
rate).
Interpolator Works with the FIFO block to generate the desired output delay.
(7) You can obtain this value from the VCO clock frequency parameter under General Tab in
the IP parameter editor.
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Figure 96. Output Path

This figure shows the output path for the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and
I-Series devices.
From Intel FPGA core To external interface
PHY Lite for Parallel Interfaces Intel FPGA IP
group_<n>_strobe_out_en group_<n>_strobe_out/
group_<n>strobe_io
group_<n>_data_from_core Write FIFO group_<n>_data_io/
group_<n>_oe_from_core group_<n>_data_out
(1)
phy_clk
(1)
interpolator_clk
(1) (2)
VCO clock Interpolator
Legend
Data path
(1)
Internal signal Strobe path
(2)
The Output Strobe Phase and Write Latency parametersin Parameter Editor sets the phase shift in this module.
The group_<n>_strobe_out / group_<n>strobe_io is restricted to the following

patterns:
• Tristate before and after data capture.
• Toggling for data capture.
In a case where group_<n>_strobe_out / group_<n>strobe_io requires

different patterns than the patterns stated above, replace the dedicated strobe pins
with data pins.
Related Information
Output Path Signals on page 118
For more information about output path signals.
4.2.3.3. Input Path
The input path of the IP consists of a data path, a strobe path, and a read enable path
as shown in the following figure.
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Figure 97. Input Path

To Intel FPGA core PHY Lite for Parallel Interfaces Intel FPGA IP To external interface
group_<n>_data_to_core group_<groupnumber>_data_in
Read FIFO DDIO Delay Chain group_<groupnumber>_data_io
6 phy_clk (1) 5 (PVT)
5
group_<n>_strobe_in
(1) group_<n>_strobe_io
read_enable
(1) dqs group_<n>_strobe_io_n
(1) (3)
pstamble_reg dqs_clean Delay Chain
(PVT)
3
4
6
group_<n>_rdata_valid
dqs_enable_out (1)
1 2
group_rdata_en VFIFO
(2) (1)
DQS_EN FIFO
dqs_enable_in
(1)
phy_clk (1)
interpolator_clk
(1)
phy_clk_phs Interpolator
Legend:
Data path
Strobe path
(1)
Internal signals Read and Strobe Enable path
(2)
This module is controlled by Read Latency parameter in the Parameter Editor.
Control signal
(3)
This module is uses the Capture Phase Shift parameter to generate the delay for the incoming strobe. # = sequence number.
# This represent read operation
sequence.
Table 62. Blocks in Data, Strobe, and Read Enable Paths

Path Description
Data Path Receives data from external device to the FPGA core logic.
The data path consists of a PVT compensated delay chain, a DDIO and a read FIFO.
• DDIO and read FIFO—Responsible for deserialization with a factor of up to 8 (in DDR quarter-rate).
The transfer between the DDIO and the read FIFO is a zero-cycle transfer.
Signals used in this path are:
• group_data_in—Input data from external device.
• group_data_io—Input and output data from/to external device.
• group_data_to_core (output)—Output data to the Intel FPGA core.
• phy_clk—This is an internal clock signal that provides clock to the blocks used in this path.
The IP supports SDR input by sending data on single clock cycle from the external device.
Strobe Path Input strobe (dqs) to capture input data from external device.
The strobe path consists of pstamble_reg (a gating component) and a PVT compensated delay chain.
• pstamble_reg—This gating circuitry ensures that only clock edges associated with valid input data are
used.
• PVT compensated delay chain—Provides a phase offset between the strobe and the data (for
example, center aligning edge-aligned inputs).
continued...
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Path Description
• group_strobe_in, group_strobe_in_n (input)—Input strobe from external device. .

• group_strobe_io, group_strobe_io_n(bidirectional)—Input and output strobe from/to external
device. group_strobe_io_n is used when strobe configuration is set to Differential.
• dqs_clean(output)—This internal signal is the refined version of strobe_in signal.
• dqs(input)—This internal signal is an input strobe to DDIO and Read FIFO in the data path, after
phase shift adjustment.
Read and Generates control signals for strobe calibration and reading data from Read FIFO.
Strobe Enable The read and strobe enable path consists of VFIFO, DQS_EN FIFO, and an interpolator.
Path
• VFIFO—Takes the rdata_en signal from the core and delays it separately for two outputs, one for
the read enable on the Read FIFO, and one for the strobe enable. These delays are calculated at
generation time based on the read latency that you provide.
• DQS_EN FIFO and interpolator—Used for the strobe enable delay, the DQS_EN FIFO and interpolator
are identical to the Write FIFO and interpolator circuitry in the output path. The DQS_EN FIFO and
interpolator are configured to match the output delay for a group with no additional output delay
(Write latency = 0).
• group_rdata_valid (output)—This signal determines which data are valid when reading from
Read FIFO. This signal is delayed by the Read latency value set in the parameter editor.
• group_rdata_en (input)—This signal represents the number of expected words to read from the
external device.
• dqs_enable_in (input)—This is an internal signal that provides dqs delay value to the
pstamble_reg module to process a refined dqs signal.
• dqs_enable_out (output)— This is an internal strobe with the delayed value specified by the
dqs_enable_in signal.
• phy_clk—This is an internal clock for VFIFO and Read FIFO modules.
• phy_clk_phs—This is an internal clock for the interpolator.
• interpolator_clk—This is an internal clock for DQS_EN FIFO module.
Table 63. Read Operation Sequence

A read operation is performed as listed in this table.
Read Operation Operation

Sequence Number
1 The core asserts the rdata_en signal to the PHY Lite for Parallel Interfaces Intel FPGA IP and
issues a read command to the external device.
2 VFIFO and DQS_EN FIFO generate the dqs_enable signal to pstamble_reg. This signal is
delayed by the programmed read latency (which should match the latency of the external
device).
3 The pstamble_reg generates dqs_clean signal as valid data enters the read path.
4 The Delay Chain (PVT) adjusts the strobe with phase offset between the strobe and the input
data (for example, 90° phase shift for DDR center-alignment).
5 The dqs signal is then used as strobe to read data from external device into the DDIO and Read
FIFO modules.
6 The VFIFO asserts the read_enable signal to Read FIFO and the rdata_valid signal to the
core simultaneously. The PHY Lite for Parallel Interfaces Intel FPGA IP sends the captured data to
the core with the associated valid signal.
Related Information
For more information about input path signals.
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You must perform calibration to achieve timing closure at a high frequency because of
the asynchronous nature of the PHY. At a high level, calibration involves reconfiguring
input and output delays in the PHY to align data and strobes. With the PHY Lite for
Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-Series devices, you can
perform calibration using the dynamic reconfiguration feature. The dynamic
reconfiguration feature allows you to modify the input and output delays by writing to
a set of control registers using an Avalon memory-mapped interface.
Note: Follow the guidelines described in the Dynamic Reconfiguration Guidelines section
when generating your own dynamic reconfiguration controller.
Related Information
• AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for
Parallel Interfaces IP Cores.
• AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic
Reconfiguration for Intel Stratix 10 Devices
4.2.4.1. Connectivity
The PHY Lite for Parallel Interfaces Intel FPGA IP exposes the Avalon memory-mapped
interface when you enable the dynamic reconfiguration feature. The connectivity of
the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-Series
devices to the Avalon memory-mapped interface must be performed via Calibration IP.
One Calibration IP must be shared across different PHY Lite for Parallel Interfaces Intel
FPGA IPs within the same row. For example, all IPs in the bottom row are connected
to one Calibration IP and all IPs in the top row are connected to another Calibration IP.
This Calibration IP does not perform any calibration for the PHY Lite for Parallel
Interfaces Intel FPGA IP. The Calibration IP only provides an access path (Avalon
memory-mapped interface bus) to all the registers of interest for reconfiguration.
4.2.4.2. Reconfiguration Features and Register Addressing
Each reconfigurable feature of the interface has a set of control registers with an
associated memory address to store the reconfigurable settings; however, this address
is placement dependent.
The following two sets of control registers store the reconfiguration feature settings:
• Control/status registers (CSR)—You can only read the values of these registers.
The values are set through the IP parameters. The CSR registers contain the
default setting in the IP.
• Avalon memory-mapped interface registers—You can read and write to these
registers using Avalon memory-mapped interface. Perform an RTL simulation to
show an accurate timing which correlates to the hardware operation.
4.2.4.2.1. Control Registers Addresses
For the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-Series
devices, the address register map is automatically generated when the IP is
generated. The address register map can be obtained in the ip/ed_synth/<PHY
Lite IP folder>/altera_arch_fm_xxx/synth/addr_map.vh.
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Table 64. Control Register Addresses Description

Feature Bit Description
Pin Output Delay [26:24] The Avalon controller calibration bus base address. Value is fixed to
3’h3.
[23:21] Reserved with value 3’h0.
[20:13] The lane address of an interface.
[12:8] The address for the physical location of a pin within a lane.
[7:0] Reserved with value 8’d0
Pin Input Delay [26:24] The Avalon controller calibration bus base address. Value is fixed to
3’h3.
[12:9] Reserved with value 4’hC.
[8:7] DQ pin sets to access.

• 2'h1: DQ 0 to DQ 5
• 2'h2: DQ 6 to DQ11
[6:4] Specific DQ pin to access.

• 3'h0: DQ 0 and DQ 6
• 3'h1: DQ 1 and DQ 7
• 3'h2: DQ 2 and DQ 8
• 3'h3: DQ 3 and DQ 9
• 3'h4: DQ 4 and DQ 10
• 3'h5: DQ 5 and DQ 11
Strobe Input Delay [26:24] The Avalon controller calibration bus base address. Value is fixed to
3’h3.
[12:0] Reserved with value 13'h18E0.
Strobe Enable Phase [26:24] The Avalon controller calibration bus base address. Value is fixed to
3’h3.
[12:0] Reserved with value 13'h18F0.
Strobe Enable Delay [26:24] The Avalon controller calibration bus base address. Value is fixed to
3’h3.
[12:0] Reserved with value 13'h1808.
Read Valid Delay [26:24] The Avalon controller calibration bus base address. Value is fixed to
3’h3.
continued...
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[12:0] Reserved with value 13'h180C.
4.2.4.2.2. Control Registers
When you generate a read operation to the control registers addresses, the Avalon
interface returns a set of values from the control registers.
Table 65. Control Register Bit Description

This table shows the definition of the bits for each control register.
Pin Output Delay [31:13] Reserved.
[12:0] Phase value.

• Strobe minimum setting: Refer to the Output and Strobe
Enable Minimum and Maximum Phase Settings topic.
• Strobe maximum setting: Refer to the Output and Strobe
• Incremental delay: 1/128th VCO clock period.
The CSR value for DQS is set through the Output Strobe Phase
parameter during IP instantiation.
Note: The pin output delay switches from the CSR register value
to the Avalon register value after the first Avalon write.
The delay is only reset to the CSR register value on a
reset of the interface.
Pin Input Delay [31:13] Reserved.
[12] Enable bit to select access to Avalon register or CSR register.

• 0 = Delay value is 0. CSR register is not available for this
feature.
• 1 = Select delay value from Avalon register.
[11:9] Reserved.
[8:0] Delay value.

• Minimum setting: 0
• Maximum setting: 511 steps
• Incremental delay: 1/256th VCO clock period
Strobe Input Delay [31:13] Reserved.

• 0 = Delay value is 0. CSR register is not available for this
feature.
Modifying these values must be done on all lanes in a group.
[11:10] Reserved.
[9:0] • Minimum setting: 0

• Incremental Delay: 1/256th VCO clock period
Strobe Enable Phase [31:13] Reserved.

continued...
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• 0 = Select delay value from CSR register. The CSR value is set
through the Capture Strobe Phase Shift parameter during
IP instantiation.
[11:10] Reserved.
[9:0] • Minimum setting: 0

• Incremental delay: 1/128th VCO clock period
Strobe Enable Delay [31:16] Reserved.

• 0 = Select delay value from CSR register
• 1 = Select delay value from Avalon register
[14:6] Reserved.
[5:0] Delay value.

• Minimum setting: 0 external clock cycles
• Maximum setting: 63 external memory clock cycles
• Incremental delay: 1 external memory clock cycle
Read Valid Delay [31:16] Reserved

• 0 = Select delay value from CSR register
• 1 = Select delay value from Avalon register
[14:7] Reserved.
[6:0] Delay value.

• Minimum setting: 0 external clock cycles
• Maximum setting: 127 external memory clock cycles
• Incremental delay: 1 external memory clock cycle
Example Structure of Address Map (addr_map.vh)
This example shows the address value, mask value, delay field offset, and delay field
width of an address map (addr_map.vh file). The address value is generated based
on information in the Control Register Addresses Description table. The mask value is
to be masked with the 32-bit data register pin output delay in the Control Data
Register Bit Description table. The delay width of value 13 corresponds to bit 12 to bit
0 for pin output delay in the Control Data Register Bit Description table.
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Figure 98. Example Structure of Address Map

localparam GROUP_0_PIN_0_OUTPUT_DATA_DELAY__ADDR = 27'h30000D0;
localparam GROUP_0_PIN_0_OUTPUT_DATA_DELAY__MASK = 32'h1fff;
localparam GROUP_0_PIN_0_OUTPUT_DATA_DELAY__PHASE_DELAY__FIELD_OFFSET = 0;
localparam GROUP_0_PIN_0_OUTPUT_DATA_DELAY__PHASE_DELAY__FIELD_WIDTH = 13;
Pin DQ4 is skipped to
pin 6 because the strobe
pins are reserved at
pin 4 and pin 5.
Related Information
• Output and Strobe Enable Minimum and Maximum Phase Settings on page 112
Provides the strobe minimum and maximum settings for the control registers
pin output delay feature.
• Control Registers Addresses on page 105
Provides the information to generate address value in the address map.
4.2.4.3. Dynamic Reconfiguration Guidelines
devices allows you to dynamically reconfigure the features of the interface. No traffic
should occur during reconfiguration. Reframing is necessary, particularly in continuous
strobe mode of operation. Intel recommends performing dynamic calibration for
application with core clock frequency of more than 533 MHz. This section provides the
general guidelines for calibrating Agilex 7 F-Series and I-Series I/O architecture.
Note: Follow the guidelines when generating your own dynamic reconfiguration controller.
Related Information
Parallel Interfaces IP Cores
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4.2.4.3.1. Strobe Enable Window Calibration
The main block, pstamble_reg, has a gating circuitry to generate dqs_clean from
strobe_in/strobe_io and dqs_enable_out signals. The pstamble_reg block has
an finite state machine (FSM) to control the gate signal. If dqs_enable_out is high
and strobe_in/strobe_io is at any positive edge, the gate signal is asserted and
dqs_clean is generated. The dqs_enable_out is high if you set the external signal,
rdata_en to high.
An internal counter counts the number of strobe_in/strobe_io toggles until the

internal counter reaches the maximum number of toggles. The maximum number of
toggles depends on the internal counter. In this example, the internal counter counts
eight toggles. In quarter rate and DDR strobe, if all the 4 bits of rdata_en are high in
one core clock cycle,eight strobes are toggled. Strobe edges depend on core clock
cycle and independent on DDR/SDR strobe. Ideally, in normal PHY state, after the
maximum number of toggles is reached, the gate signal is deasserted.
Figure 99. Input Path of PHY Lite for Parallel Interfaces Intel FPGA IP Core for Agilex 7
Devices
PHY Lite for Parallel Interfaces IP Core
To Intel FPGA core To external interface
data_in
data_to_core Delay Chain data_in_n
phy_clk Read FIFO DDIO data_io
(PVT) data_io_n
strobe_in
strobe_in_n
dqs strobe_io
read_enable strobe_io_n
dqs_clean
pstamble_reg Delay Chain
(PVT)
rdata_valid
dqs_enable_out
rdata_en
VFIFO dqs_enable_in DQS_EN FIFO
phy_clk
interpolator_clk
Perform the strobe enable window calibration to capture the correct datain/data_io
on strobe_in/strobe_io signal. You can perform the calibration either by
sweeping the dqs_enable_out through the interpolator or sweeping the
strobe_in/strobe_io or data_in/data_io.
However, during strobe enable window calibration, while finding the end of the
window, an undesired state can happen where the gate signal remains asserted
incorrectly and the wrong datain/data_io (noise) is captured on strobe_in/
strobe_io signal. In this case, you must bring PHY to normal state by adding
dummy pulses on the strobe_in/strobe_io signal with rdata_en deasserted.
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In the following figure, in normal PHY state, the dqs_enable_out is high before the
preamble cycles and first strobe edge. The duration of dqs_enable_out stays high
depends on the duration of rdata_en stays high in the core. Once dqs_enable_out
is high, if a positive edge of strobe_in/strobe_io is observed, the gate signal
goes high (marked by blue marker). An internal counter starts to count at first positive
edge of strobe_in/strobe_io until the maximum number of toggles (in this case,
the maximum number of toggles is eight). The gate signal is deasserted on the last
negative edge of the strobe_in/strobe_io (marked by the green marker). Ideally,
dqs_clean is the same as strobe_in/strobe_io because all eight toggles are
captured by the internal counter.
In the undesirable state, the strobe_io/strobe_in is calibrated to start toggling

earlier. While detecting the correct window margins during calibration, an undesired
state occurs because the internal counter does not finish counting to eight resulting in
the gate signal remains asserted and produces incomplete dqs_clean (marked by
red marker).
Figure 100. dqs_clean Timing Diagram

Normal state: Complete dqs_clean is generated
strobe_in/strobe_io Preamble stage 1 2 3 4 5 6 7 8
rdata_en
dqs_enable_out (internal)
gate (internal)
dqs_clean (internal) 1 2 3 4 5 6 7 8
Undesirable state: Incomplete dqs_clean is generated
rdata_en
gate (internal)
dqs_clean (internal) 1 2 3 4 5 6
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To return the PHY to the normal state, you must force the gate signal to deassert by
adding extra dummy pulses (red strobe_in/strobe_io pulses) while rdata_en is
deasserted as shown in the following figure. By adding these dummy pulses, a
complete dqs_clean is produced (marked by green marker). After the green marker,
although there are few strobe_in/strobe_io toggles, no new dqs_clean is
produced because the gate signal remains low.
Figure 101. Adding Extra Dummy Pulses to Return PHY to Normal State
strobe_io Preamble stage 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
rdata_en
gate (internal)
4.2.4.3.2. Output and Strobe Enable Minimum and Maximum Phase Settings
When dynamically reconfiguring the interpolator phase settings, keep the values
within the ranges in the following table to ensure proper operation of the circuitry.
Table 66. Output and Strobe Enable Minimum and Maximum Phase Settings
VCO Core Rate Minimum Interpolator Phase Maximum
Multiplication Interpolator
Factor Output Bidirectional Bidirectional with Phase
OCT Enabled
1 Full 0x080 0x100 0x100 0xA80
Half 0x080 0x100 0x100 0xBC0
Quarter 0x080 0x100 0x100 0xA00
2 Full 0x080 0x100 0x180 0x1400
Half 0x080 0x100 0x180 0x1400
Quarter 0x080 0x100 0x180 0x1400
4 Full 0x080 0x100 0x280 0x1FFF
Half 0x080 0x100 0x280 0x1FFF
Quarter 0x080 0x100 0x280 0x1FFF
8 Full 0x080 0x100 0x480 0x1FFF
Half 0x080 0x100 0x480 0x1FFF
4.2.4.3.3. Input DQ/DQS Delay Chains Maximum Values
The complete range is from 0 to 511 in steps of T_vco/256, but the whole range is not
always available. Also, only a portion of this range is usable depending on PLL
frequency, temperature, and voltage. To find the usable range, perform the write and
read-back operations to ensure if the value applies or needs to lower.
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Assume the usable range has a maximum value of k and you write a value A. You can
read back the value based on the following conditions:
• If A < k, the value you write is under the upper limit, you read back the same
value (readdata=A).
• If A > k, the value you write is over the upper limit, you read back the upper limit
value. (readdata=k).
Related Information
4.2.5. I/O Timing

You are advised to design the system with the worst case losses for the PHY Lite for
Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-Series devices.
Table 67. Worst Case Losses for PHY Lite for Parallel Interfaces Intel FPGA IP for
Agilex 7 F-Series and I-Series Devices
This table assumes that a PHY Lite for Parallel Interfaces Intel FPGA IP is communicating with another PHY Lite
for Parallel Interfaces Intel FPGA IP.
Data Flow Direction Applies to PHY Lite for Parallel Worst Case Losses(8)
Interfaces Intel FPGA IP Mode
Driving (PHY Lite for Parallel Interfaces Output / bi-directional 45% UI

Intel FPGA IP is driving the I/Os)
Receiving (PHY Lite for Parallel Input / bi-directional POD 1.2 V: 38% UI
Interfaces Intel FPGA IP is sampling SSTL 1.2 V: 49% UI
the I/Os)

You can instantiate the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-
Series and I-Series devices from IP Catalog in Quartus Prime software. Intel provides
an integrated parameter editor that allows you to customize this IP to support a wide
variety of applications.
This IP is located in Libraries ➤ Basic Functions ➤ I/O of the IP catalog.
Related Information
version upgrades.
(8) The losses are denoted for a PHY Lite for Parallel Interfaces Intel FPGA IP operating at 1,200
MHZ at DDR.
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Table 68. PHY Lite for Parallel Interfaces Intel FPGA IP Parameter Settings
GUI Name Values Default Description
Values
Parameter

Clocks
Interface clock frequency 100 MHz - 1200 533.0 MHz External interface clock frequency.
MHz
Use recommended PLL On, Off On If you want to calculate the PLL reference clock
reference clock frequency frequency automatically for best performance,
turn on this option.
If you want to specify your own PLL reference
clock frequency, turn off this option.
PLL reference clock frequency Dependent on 133.25 MHz PLL reference clock frequency. You must feed a
interface clock clock of this frequency to the PLL reference
frequency clock input of the memory interface.
Select the desired PLL reference clock frequency
from the drop-down list. The values in the list
changes when you change the interface clock
frequency or the user clock rate logic.
VCO clock frequency Calculated 1066.0 MHz The frequency of this clock is calculated
internally by PLL internally by the PLL based on the interface
clock and the core clock rate.
Clock rate of user logic Quarter, Half, Full Quarter Determines the clock frequency of user logic in
relation to the memory clock frequency. For
example, if the memory clock sent from the
FPGA to the memory device is toggling at 800
MHz, a "Quarter rate" interface means that the
user logic in the FPGA runs at 200 MHz.
Use dynamic reconfiguration On, Off Off Exposes an Avalon memory-mapped interface,
allowing you to control the configuration of the
settings.
Note: The PHY Lite for Parallel Interfaces Intel
FPGA IP for Agilex 7 devices does not
support dynamic reconfiguration feature
in the Quartus Prime v20.3.
I/O Settings
1.2-V POD strobe and data pins written to the .qip file of
the IP instance.
Reference clock I/O Single-ended, Single-ended Specify the reference clock I/O configuration.
with on-chip
termination,
continued...
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Values
True Differential
without on-chip
termination
Group <x> - these parameters are set on a per group basis
Group <x> Pin Settings
Pin type Input, Output, Bidirectional Direction of data pins. This value is set to
Bidirectional Bidirectional by default.
Pin width 1 to 45 (9) 9 Number of pins in this data/strobe group. The

pin width includes the number of strobe pins.
Group <x> Input Path Settings
Read latency 7 to 63 external 7 Expected read latency of the external device in

interface clock memory clock cycles.
cycles Refer to the Read Latency table for minimum
read latency settings based on FPGA core clock
rate.
Capture strobe phase shift 90 90 Internally phase shift the input strobe relative to
input data.
Group <x> Output Path Settings
Write latency 0 to 3 0 Additional delay added to the output data in

memory clock cycles.
Refer to the Write Latency table for write
latency settings based on FPGA core clock rate.
180 output data.
Group <x> General Strobe Settings

Strobe configuration Differential, Differential Select the type of strobe.

Single-ended Note: The differential strobe configuration uses
a differential input buffer, which
produces a single clock for the capture
DDIO and read FIFO. The output path
functionality is the same.
Refer to the I/O Standards table for a list of
Group <x> OCT Settings
OCT enable size 0 - 15 1 Specifies the delay between the OCT enable
signal assertion and the dqs_enable signal
assertion. You must set a value that is large
enough to ensure that the OCT is turn on before
sampling input data.
continued...
(9) The maximum value varies depending on the configuration, such as number of groups,
Quarter Rate/Half Rate/Full Rate, and single-ended or differential PLL reference clock.
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Values
calibration, 50 calibration termination values to be written to the .qip of
ohm with the IP instance. The list of legal values is
calibration(10) dependent on the I/O standard parameter
setting. Refer to the I/O Standards table.
Disable the Use Default OCT Values
parameter to select the desired input OCT value.
Output OCT Value 34 ohm with 40 ohm with Specifies the group's data and strobe input
calibration, 40 calibration termination values to be written to the .qip of
ohm with the IP instance. The list of legal values is
calibration(10) dependent on the I/O standard parameter
setting. Refer to the I/O Standards table
supported termination values.
Disable the Use Default OCT Values
parameter to select the desired output OCT
value.
Pin Placement
Physical Sub-bank ID 0–15 0 ID of the physical sub-bank to be used for

placement.
Refer to diagrams in the Agilex 7 I/O Sub-bank
Interconnects topic.
Pin Parameter Settings On, Off Off By default, all the data pins are placed adjacent
to each other with no gap between the pins.
Enable this option if require a gap between the
data pins.
Refer to the Guidelines: Group Pin Placement
topic for pin placement guidelines for PHY Lite
for Parallel Interfaces Intel Agilex FPGA IP.
Pin Placement Settings Comma separated — Enter the location list of the data pins.
values Provide the data pins location list in values. For
example, enter value of 0, 1, 8, 9 to place
data[0] on pin 0, data[1] on pin 1, data[2] on
pin 8, and data[3] on pin 9 of the I/O bank. In
this case, pin 2 to pin 7 are not used.
Refer to the Guidelines: Group Pin Placement
topic for pin placement guidelines for PHY Lite
for Parallel Interfaces Intel Agilex FPGA IP.
Related Information
devices.
• Guidelines: Group Pin Placement on page 123
For more information about pin placement guidelines in Agilex 7 devices.
(10) You can select input OCT value based on your design, ideally through analog simulation using
FPGA IBIS modes and specific board.
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4.3.1.1. Read Latency
Table 69. Minimum Read Latency

This table shows the minimum read latency value supported by PHY Lite for Parallel Interfaces Intel FPGA IP for
Agilex 7 devices based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate VCO Multiplier Factor Read Latency (External Memory Clock
Cycle)
1 17
2 16
Quarter Rate
4 15
8 14
1 11
2 10
Half Rate
4 9
8 8
1 8
2 7
Full Rate
4 6
8 5
4.3.1.2. Write Latency
Table 70. Maximum Write Latency

This shows the maximum write latency value supported by PHY Lite for Parallel Interfaces Intel FPGA IP for
Agilex 7 devices based on the core clock rate and VCO multiplier factor settings.
VCO Multiplier Factor Write Latency (External Memory Clock

Core Clock Rate
Cycle)
Quarter 1 17
2 15
4 14
8 14
Half 1 11
2 9
4 7
8 8
Full 1 8
2 6
4 5
8 5
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4.3.2. Signals

synchronous with group_strobe_in to ensure that the
reset_n Input 1 Resets the interface. Deassertion of this signal should be

synchronous to the ref_clk.
interface_locked Output 1 Interface locked signal from the PHY Lite for Parallel Interfaces
IP to the core logic. This signal indicates that the PLL and PHY
circuitry are locked.
Start the data transfer only after the assertion of this signal.
frequency and clock rate of user logic parameters.

Output path signals are signals that are available when you set the Pin Type parameter to either Output or
Bidirectional. The <n> in the signal names below represents the group number in the IP.
group_oe_from_core Input Quarter-rate: 4 Output enable signal from FPGA core.

Synchronous to the core_clk_out
output from the IP.
This signal is shared across all
groups.
Quarter rate-DDR: 8 x PIN_WIDTH Data signal from Intel FPGA core.

group_<n>_data_fro
Input Synchronous to the core_clk_out
m_core Quarter-rate SDR: 4 x PIN_WIDTH output from the IP.
group_strobe_out_e Input Quarter-rate: 4 Strobe output enable from FPGA

n core. Synchronous to the
core_clk_out output from the IP.
groups.
group_<n>_data_out Output/ 1 to 34 Data output from the IP. Synchronous

/group_<n>_data_io Bidirectional to the group_<n>_strobe_out or
group_<n>_strobe_io output from
the IP.
If the Pin Type parameter is set to
Output, the group_<n>_data_out
signals are used. If the Pin Type
continued...
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parameter is set to Bidirectional,

the group_<n>_data_io signals are
used.
group_<n>_strobe_o Output/ 1 Positive output strobe from the IP. If

ut/ Bidirectional the Pin Type is set to Output, the
group_strobe_io/ group_<n>_strobe_out signal is
group_<n>_strobe_i used. If the Pin Type is set to
o Bidirectional the
group_<n>_strobe_io signal is
used.
group_<n>_strobe_o Output/ 1 Negative output strobe fro the IP.

ut_n / Bidirectional This is used if the Strobe
group_<n>_strobe_i Configuration is set to Differential.
o_n If the Pin Type is set to Output, the
Bidirectional, the
group_<n>_strobe_io_n signal is
used.

Input path signals are signals that are available when you set the Pin Type parameter to Input or
group_<n>_data_t Output Quarter-rate DDR: 8 x PIN_WIDTH Output data to the core logic. Valid
o_core Quarter-rate SDR: 4 x PIN_WIDTH on group_<n>_rdata_valid.
output from the IP.
group_rdata_en Input Quarter-rate: 4 This signal represents the number of

expected words to read from the
external device.
This signal is set to high after a read
command is issued. Synchronous to
the core_clk_out output from the
IP.
When using the IP as a receiver,
assert this signal after
interface_locked signal is
asserted and group_strobe_in is
stable.
groups.
group_<n>_rdata_ Output Quarter-rate: 4 This signal determines which data are

valid valid when reading from Read FIFO.
Delayed by READ_LATENCY with
margin and aligned to the core clock
rate. For example, in quarter-rate,
the delay is a multiple of 4 external
clock cycles.
output from the IP.
group_<n>_data_i Input/ 1 to 34 Input and output data from/to

n/ Bidirectional external device. Synchronous to the
group_<n>_strobe_in or
continued...
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group_<n>_data_i group_<n>_strobe_io input. The

o first data_in must be associated with
positive edge of
group_<n>_strobe_in/
group_<n>_data_in ports are
used. If the pin type is set to
bidirectional, the
group_<n>_data_io ports are
used.
group_<n>_strobe Input/ 1 Input and output strobe from/to

_in/ Bidirectional external device. If the pin type is set
group_<n>_strobe to Input, the
_io group_<n>_strobe_in signal is
Bidirectional, the
used.
group_<n>_strobe Input/ 1 Negative strobe from/to external

_in_n/ Bidirectional device. This is used if the Strobe
group_<n>_strobe Configuration parameter is set to
_io_n Differential. If the pin type is set to
Input, the
group_<n>_strobe_in_n signal is
Bidirectional, the
used.
4.4. I/O Standards

The PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 devices allows you to set
I/O standards on the pins associated with the generated configuration. The I/O
standard controls the available strobe configurations and OCT settings for all groups.
For Agilex 7 F-Series and I-Series devices, the PHY Lite for Parallel Interfaces Intel
FPGA IP instances in the same I/O bank should have the same IO standard.
Table 74. I/O Standards and Termination Values for Agilex 7 F-Series and I-Series
Devices
I/O Standard Valid Input Terminations (Ω) Valid Output RZQ (Ω)
Terminations (Ω)
SSTL-12 50, 60 34, 40 240
1.2-V POD 50, 60 34, 40 240
Related Information
I/O Termination in Agilex 7 Devices
4.4.1. Input Buffer Reference Voltage (VREF)

The POD I/O standard allows configurable VREF. VREF range selection via QSF for POD
1.2 V requires the following .qsf assignments:
set_instance_assignment -name VREF_MODE DDR4_CAL -to <pin_names>
set_instance_assignment -name VREF_MODE DDR4_CAL_RANGE2 -to <pin_names>
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The VREF settings are at the lane level, so all pins using a lane must have the same
VREF settings including general-purpose I/Os (GPIO).
Table 75. VREF_MODE Description

VREF Mode Description
EXTERNAL Use the external VREF. This is the default.
DDR4_CAL Use internal VREF generated using code set via dynamic reconfiguration. VREF range is 60%–
92.5%.
DDR4_CAL_RANGE2 Use internal VREF generated using code set via dynamic reconfiguration. VREF range is 45%–
77.5%.
Note: You must select the VREF range for your design using analog simulation.
Figure 102. VREF
Input Buffer
VCCIO
Rt
+
Vref -
VREF Calibration Block External VREF
R
VCCIO
Internal VREF
+
-
Resistor
Ladder R
6 bits calibrated VREF code from Avalon memory-mapped bus

6 bits Static VREF Code
6 bits binary weighted resistors dividor
4.4.2. On-Chip Termination (OCT)

PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-Series devices
provides valid OCT settings for each group (refer to I/O Standards on page 120).
These settings are written to the .qip of the instance during generation. If you select
an I/O standard that supports OCT in the General tab, you can use the OCT blocks
provided in the Agilex 7 devices.
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You can instantiate the OCT block in one of two ways:

• Using RZQ_GROUP assignment in the assignment editor, or
• Manual insertion of OCT block
4.4.2.1. RZQ_GROUP Assignment
The RZQ_GROUP assignment creates the OCT Intel FPGA IP without modifying the RTL.
The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, the
Fitter creates the pin name along with the OCT Intel FPGA IP and its corresponding
connections. This allows you to create a group of pins to be calibrated by an existing
or non-existing OCT and the Fitter ensures the legality of the design. You must
associate the terminated pins of the PHY Lite for Parallel Interfaces Intel FPGA IP for
Agilex 7 F-Series and I-Series devices instance with an RZQ pin at the system level
manually.
Use the following steps to set RZQ pin locations for the IP:
1. Generate the IP or instantiate the IP into your project.
2. You can view the available RZQ pins location in the Pin Planner. Go to Pin
Planner ➤ Tasks ➤ OCT Pins and double click the RZQ. The available RZQ pins
are display in the pin grid diagram.
3. You can modify the qsf in your project to change the default RZQ location using
the following command:
set_location_assignment <rzq_capable_pin_location> –to

<user_defined_rzq_pin_name>
4. Use the following command to associate the terminated pins of the IP with the
RZQ pin:
set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to

<phylite_strobe_pin>

<phylite_data_pin[*]>
where * represents all the data pins within the same group.
This is an example of a qsf file with modified RZQ pin location assignments:
set_location_assignment PIN_AH3 -to octrzq
set_instance_assignment -name IO_STANDARD "1.5 V" -to octrzq
set_instance_assignment -name RZQ_GROUP OCTRZQ -to
group_0_io_interface_conduit_end_io_strobe_io
group_0_io_interface_conduit_end_io_data_io[*]
5. Compile the project.

6. To verify that the Quartus Prime has successfully created and assigned the RZQ
pin to the correct location, go to Pin Planner ➤ Node Name and look for
<user_defined_rzq_pin_name> with the assigned pin location in the list.
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4.5. Design Guidelines
4.5.1. Guidelines: Group Pin Placement

Follow these guidelines to place the PHY Lite for Parallel Interfaces Intel FPGA IP for
Agilex 7 F-Series and I-Series devices group pins.
1. All groups in a PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series
and I-Series devices must be placed across a contiguous set of lanes. The number
of lanes depends on the number of pins used by the group. Refer to the Agilex 7
Input DQS Clock Tree for more information about the number lanes used per pin
width.
2. A PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-Series
devices must fit within one I/O sub-bank and must not span across multiple I/O
sub-banks. One I/O sub-bank can support only one IP instance.
3. Two groups within a PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-
Series and I-Series devices cannot share an I/O lane.
4. When there are multiple groups within an IP instance, the pins must be set to
either bidirectional or unidirectional (can be a mix of input and output groups). Do
not mix bidirectional and unidirectional pin types in the same IP instance.
5. If an input group uses ×36 DQS/strobe tree, another group must be set as an
output group to utilize the remainder I/O lane in the same I/O sub-bank.
6. If a group is set to bidirectional pin type and uses the ×36 DQS/strobe tree, no
other groups are allowed to be in the same IP.
7. Control signals are shared across all groups within an IP instance.
8. Pins that are not used in an I/O sub-bank cannot be used as GPIO pins.
9. You must calibrate the I/Os within the same I/O lane using the same OCT
calibration block. You can associate the terminated pins of the PHY Lite for Parallel
Interfaces Intel FPGA IP for Agilex 7 F-Series and I-Series devices instance with an
RZQ pin through the RZQ_GROUP assignment.
10. You can place the data pin locations either automatically or manually in the Pin
Placement tab. You must enter your desired Physical Sub-Bank ID. Refer to
diagrams in the Agilex 7 I/O Sub-bank Interconnects topic for the physical sub-
bank ID for pin placement.
11. The PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-Series
devices must be placed at the Quartus-IP Generation stage because the pin
placements are not available using QSF Assignments.
12. If all the lanes in a sub-bank are not bonded out, make sure that all the PHY Lite
pins are constrained. Otherwise, the design will fail at compilation.
Note: To target the lower or upper half of I/O bank, use the Physical Sub-Bank ID. Refer to
the Agilex 7 F-Series and I-Series I/O Sub-bank Interconnects topic.
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Table 76. Pin Index Mapping

I/O Bank Pin Index I/O Sub-bank Pin Index Lane Sub-bank Location
0-11 0-11 (pins 4 and 5 are 0 Bottom

reserved for strobes)
12-23 12-23 (pins 16 and 17 are 1

24-35 24-35 (pins 28 and 29 are 2

36-47 36-47 (pins 40 and 41 are 3

48-59 0-11 (pins 4 and 5 are 0 Top

60-71 12-23 (pins 16 and 17 are 1

72-83 24-35 (pins 28 and 29 are 2

84-95 36-47 (pins 40 and 41 are 3

For more information about strobe and clock pin indexes, refer to the device pin-out
files.
Automatic and Manual Pin Placement
Follow these guidelines for automatic and manual pin placements:

1. Go to the Pin Placement tab.
2. To identify the sub-bank:
• Default value = 0.
• Use only bonded sub-banks. The bonded sub-banks are unshaded in the
Example of Pin Placement for a Single Group diagram.
• This example uses sub-bank ID =1 that is located at Bank 3A.
Figure 103. Example of Pin Placement for a Single Group

This example uses the Agilex 7 AGF022 and AGF027 devices, package R25A.
1 Bank 3A
Top Sub-bank
Z
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 84-95
PIN 72-83
PIN 60-71
PIN 48-59
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
PIN 48-59
PIN 60-71
PIN 72-83
PIN 84-95
I
P
P
R
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 36-47
PIN 24-35
PIN 12-23
PIN 0-11
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
PIN 0-11
PIN 12-23
PIN 24-35
PIN 36-47
Not Bonded
3. Each sub-bank has 48 pins.

4. In automatic mode, by default, all pins inside a group are placed in a tightly
packed manner.
5. In manual mode, you can customize the pin placement within the sub-bank
according to your requirement.
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• By default, all data pins are contiguous in sequential order.

• For example, for a pin width of 8, data pins are assigned to Pin 0, 1, 2, and 3
in Lane 1 and Lane 2.
• You can choose to specify the placements manually, by providing a comma-
separated list of pin locations, one for each data pin in Pin Placement Settings.
• The comma-separated list of pin locations is based on the index within an I/O
sub-bank. Refer to the Pin Index Mapping table.
Figure 104. Example Settings for Automatic and Manual Pin Placement
Related Information
• Pin-Out Files for Intel FPGA Devices
For pin index and I/O bank references, refer to the specific device pin-out file.
• Agilex 7 F-Series and I-Series Input DQS/Strobe Tree on page 98
4.5.2. Reference Clock

Intel recommends that you source the reference clock to the PHY Lite for Parallel
Interfaces Intel FPGA IP for Agilex 7 F-Series and I-Series devices from a dedicated
clock pin. Use the clock pin in the I/O sub-bank with the following command:
set_location_assignment <PIN_NUMBER> -to <pll_ref_clock_signal_name>
4.5.3. Reset
You can source the reset to the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex
7 F-Series and I-Series devices from an external pin or from the core. If you source
the reset from an external pin, you must configure the I/O standard of the reset signal
in the .qsf file with the following command:
set_location_assignment <PIN_NUMBER> -to <signal_name>
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4.6. Design Example

devices is able to generate a design example that matches the same configuration
chosen for the IP. The design example is a simple design that does not target any
specific application; however you can use the design example as a reference on how
to instantiate the IP and what behavior to expect in a simulation.
not edit the files.

The software generates a user defined directory in which the design example files
reside.
Intel FPGA IP for Agilex 7 F-Series and I-Series devices:
• Design example for variant without dynamic reconfiguration
• Design example for variant with dynamic reconfiguration
Table 77. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-
Series Devices Design Example Variants
Dynamic On ed_synth.qsys (synthesis Consists of PHY Lite for Parallel Interfaces Intel
Reconfiguration only) FPGA IP instance with Calibration IP.
ed_sim.qsys (simulation only) Consists of PHY Lite for Parallel Interfaces Intel
FPGA IP instance with Calibration IP, IOSSM Tester,
Tester Core, and Tester I/O.
Off ed_synth.qsys (synthesis Consists of PHY Lite for Parallel Interfaces Intel
only) FPGA IP instance.
ed_sim.qsys (simulation only) Consists of PHY Lite for Parallel Interfaces Intel
FPGA IP instance with Tester Core and Tester I/O.
Prime software generates a design example of PHY Lite for Parallel Interfaces Intel
FPGA IP without a dynamic reconfiguration module. This design example consists of
simulation and synthesis design files.

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generation:

This script generates a qii directory containing a project called ed_synth.qpf. You
can open and compile this project using the Quartus Prime software.

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simple one group PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series
and I-Series devices instantiation in the testbench.
Figure 106. High-Level View of the Simulation Design Example with One Group
Core clock
PHY Lite DUT
Read/Write
enable data
data strobe
Core clock DRAM clock
PHY Lite Tester

Tester core Tester io
Related Information
KDB link: Error (Suppressible): ../../ip/ed_sim/ed_sim_tester_0/sim/
ed_sim_tester_0.vhd(93): (vopt-1130) port "channel_strobe_out_in" of entity
"phylite_tester" is not in the component being instantiated

generation:

can open and compile this project using the Quartus Prime software.
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mapped interface calibration addresses. The connection of Calibration IP to PHY Lite
for Parallel Interfaces Intel FPGA IP is limited to one calibration IP per row.
Figure 107. Connection of Calibration IP to PHY Lite for Parallel Interfaces Intel FPGA IP
This figure shows an example of multiple (five in this example) PHY Lite for Parallel Interfaces Intel FPGA IPs
within one I/O row. Thus, only one calibration IP is needed to connect all five PHY Lite for Parallel Interfaces
Intel FPGA IPs to the Calibration IP.
Calibration Bus
Calibration IP
User Control/Data Bus I/O
PHY Lite
Note: Follow the guidelines described in the Dynamic Reconfiguration Guidelines section
when generating your own dynamic reconfiguration controller.

To use your own testbenches and simulation scripts, you must apply the compilation
switch: +define+EMIF_DISABLE_CAL_OPTIMIZATIONS used in the simulation
design example with dynamic reconfiguration to avoid simulation failure.
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The simulation design example provides an example of the core and I/O connectivity
mapped interface calibration addresses. The addresses of all the configurable registers
are saved in the addr_map.vh file. The IOSSM Tester block sends a simple sequence
(write/read to a delay register) as a sample. Functionally, the simulation triggers read
and write operations over each group in your configured IP. The following diagrams
show a simple one group PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-
Series and I-Series devices instantiation in the testbench.
Figure 108. Dynamic Reconfiguration Simulation Design Example
Calibration Bus
Calibration IP
User Control/Data Bus PHY Lite I/Os
Tester
IOSSM Tester Tester

Tester Core I/O
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Figure 109. Write Operation Using Dynamic Reconfiguration
Calibration Bus
Calibration IP
Provides Stimulus Traffic Checks Data

for Tx Path for Tx Path
Tester
IOSSM Tester Tester

Tester Core I/O
Read and Write to One

Output Delay Register
Figure 110. Read Operation Using Dynamic Reconfiguration
Calibration Bus
Calibration IP
Check Data to Core Traffic Provides Stimulus

for Rx Path for Rx Path
Tester
IOSSM Tester Tester

Tester Core I/O
Read and Write to One

Output Delay Register
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Send Feedback
5. PHY Lite for Parallel Interfaces Intel FPGA IP for

Stratix 10 Devices

features.
changes.
Table 78. PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 Devices Release
Information
Item Description
IP Version 19.5.1
Related Information

The PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices utilizes the I/O
subsystem in the Stratix 10 devices. The I/O subsystem is located in the I/O columns
of each Intel FPGA devices. For Stratix 10 devices, each column consists of I/O banks
and IOSSM. The number of I/O banks varies according to device packages. Each bank
is a group of 48 I/O pins, organized into four I/O lanes with 12 pins for each lane.
Each I/O lane contains the DDR-PHY input and output path logic for 12 I/Os as well as
a DQS logic block. All four lanes in a bank can be combined to form a single data/
strobe group or up to four groups in the same interface. Under certain conditions, two
5. PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 Devices
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groups from different interfaces can also be supported in the same bank. Refer to the
Guidelines: Group Pin Placement for more information about the guidelines to
implement multiple interfaces in the same bank.
Important: All Stratix 10 devices have separate LVDS I/O and 3 V I/O banks. The Stratix 10 GX
10M variant has denser LVDS I/O banks with a slightly different I/O bank structure
compared to other Stratix 10 variants. The PHY Lite for Parallel Interfaces Intel FPGA
IP utilizes only the LVDS I/O banks.
Figure 111. Stratix 10 I/O Bank Structure

This figure shows an example of I/O banks in one Stratix 10 device. The I/O banks availability and locations
vary among Stratix 10 devices.
Intel® Stratix® 10 GX 10M FPGA ZZ

2AU1 SDM_U1 3AU1 3LU2 2NU2
2BU1 3BU1 3KU2 2MU2 SDM Shared LVDS I/O
U10 U22
2CU1 3CU1 3JU2 2LU2 LVDS I/O
Pin Naming Orientation

2FU1 3DU1 3IU2 2KU2
3 V I/O
2GU1 3EU1 3HU2 2JU2
2HU1 3FU1 3GU2 2IU2 HPS Shared LVDS I/O
U1 U2
21U1 3GU1 3FU2 2HU2 3.3 V I/O in 1SG040HF35 and 1SX040HF35 only
2JU1 3HU1 3EU2 2GU2 LVDS I/O in all other Intel Stratix 10 FPGAs
2KU1 3IU1 3DU2 2FU2
2LU1 3JU1 3CU2 2CU2
U12 U20
2MU1 3KU1 3BU2 2BU2
2NU1 3LU1 3AU2 SDM_U2 2AU2
AA
SERDES & DPA LVDS I/O Buffer Pair
99 Pin Naming Orientation 1 SERDES & DPA LVDS I/O Buffer Pair
SERDES & DPA I/O Lane LVDS I/O Buffer Pair
SERDES & DPA I/O DLL LVDS I/O Buffer Pair
1 Pin Naming Orientation 99 SERDES & DPA LVDS I/O Buffer Pair
AA SERDES & DPA LVDS I/O Buffer Pair
Other Intel Stratix 10 FPGAs SERDES & DPA I/O Lane LVDS I/O Buffer Pair
2N 3N SERDES & DPA I/O DLL LVDS I/O Buffer Pair
2M 3M I/O Center
2L 3L I/O VR OCT
Clock Network
2K 3K Hard Memory
Pin Naming Orientation
6C 7C Controller
2J 3J I/O PLL
and
2I 3I PHY Sequencer
2H 3H
2G 3G SERDES & DPA LVDS I/O Buffer Pair
6B 7B SERDES & DPA LVDS I/O Buffer Pair
2F 3F I/O Lane
2E 3E SERDES & DPA LVDS I/O Buffer Pair
2D 3D SERDES & DPA I/O DLL LVDS I/O Buffer Pair
2C 3C SERDES & DPA LVDS I/O Buffer Pair
6A 7A SERDES & DPA LVDS I/O Buffer Pair
2B 3B SERDES & DPA LVDS I/O Buffer Pair
SERDES & DPA I/O Lane LVDS I/O Buffer Pair
2A SDM 3A
ZZ SERDES & DPA
SERDES & DPA I/O DLL
LVDS I/O Buffer Pair
LVDS I/O Buffer Pair
Related Information
• I/O Bank Architecture in Stratix 10 Devices
For more information about Intel Stratix 10 I/O bank architecture.
• KDB link: Why does the PHY Lite for Parallel Interfaces Stratix 10 FPGA IP cannot
be assigned to Bank 3A or 3D when using the Stratix 10 10 1ST040* device?
• Constraining Multiple PHY Lite for Parallel Interfaces Intel FPGA IP to One I/O Bank
on page 181
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5.2.1. Top Level Interfaces

The PHY Lite for Parallel Interfaces Intel FPGA IP consists of the following ports:
• Avalon memory-mapped configuration bus (available only when Dynamic
Reconfiguration feature is enabled)

This figure shows the top-level diagram of the PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10
devices interface.
Intel FPGA Device

Group
ref_clk PLL phy_clk

}
Legend
Related Information
For more information about the IP output path.
For more information about the IP input path.
For more information about the IP data, control, and I/O interfaces.
5.2.2. Clocks
The PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices uses a
reference clock that is sourced from a dedicated clock pin to the PLL inside the IP. This
PLL provides four clock domains for the output and input paths.
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Table 79. PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 Devices Clock
Domains
Core clock This clock is generated internally by the IP and it is used for all transfers between the FPGA core
fabric and I/O banks. The clock phase alignment circuitry ensures that this clock is kept in phase
with the PHY clock for core-to-periphery and periphery-to-core transfers.
PHY clock This clock is used internally by the IP for PHY circuitry running at the same frequency as the
core clock.
VCO clock This clock is generated internally by the PLL. It is used by both the input and output paths to
generate PVT compensated delays in the interpolator.
Table 80. PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 Devices
Supported Interface Frequency
Use the Timing Analyzer to perform timing closure to ensure your design fulfilled all timing constraints with the
supported frequencies indicated in the table. Full, half, and quarter core clock rate refers to the ratio of the
core clock and interface clock. For example, an interface clock frequency of 800 MHz has full core clock rate of
800 MHz, half core clock rate of 400 MHz, and quarter core clock rate of 200 MHz.
Rate
Full 100 333 100 300 100 233
Half 100 667 100 600 100 467
Quarter 100 1200 100 1200 100 933
5.2.2.1. Clock Frequency Relationships
available in the PHY Lite for Parallel Interfaces Intel FPGA IP core.
5.2.3. Output Path

The output path consists of a FIFO and an interpolator.

Block Description
rate).
Interpolator Works with the FIFO block to generate the desired output delay. You can dynamically configure
the delay through the Avalon memory-mapped interface. For more information, refer to
Dynamic Reconfiguration section.
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This figure shows the output path for the PHY Lite for Parallel Interfaces Intel FPGA IP.
strobe_out_in
strobe_out_en strobe_out/strobe_io
data_from_core Write FIFO data_io/data_out

oe_from_core
(1)
phy_clk
(1)
interpolator_clk
(1) (2)
Legend
Data path
(1)
(2)
The following figures show the waveform diagrams for the output path. The delays
shown in the waveforms are just estimation based on simulations and these values are
different with different core clock rate and VCO multiplier.
Figure 114. Output Path ─ Write Latency 0

This simulation is based on the following PHY Lite for Parallel Interfaces Intel FPGA IP configurations:
• Interface Frequency: 1000 MHz
• VCO Multiplier Factor: 1
• User logic clock rate: Quarter rate
Intrinsic Delay Write Latency = 0
Indicates the latency from the time the IP issues a write command to the time the external memory
device receives the command.
Signals from core logic

to external memory device OUTPUT_STROBE_PHASE = 90
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Indicates the latency from the time the IP issues a write command to the time the external memory Number of clock cycles set
device receives the command. in Write latency parameter
in Parameter Editor
OUTPUT_STROBE_PHASE = 90
to external memory device
Related Information
• Output Path Signals on page 169
For more information about the IP output path signals.
• Dynamic Reconfiguration on page 141
• How to estimate Intel Arria 10/Intel Stratix 10 PHY Lite Input and Output Path
Latency
How-to video on estimating PHY Lite for Parallel Interfaces IP input and output
path latency in Intel Arria 10 and Intel Stratix 10 devices.
5.2.3.1. Output Path Data Alignment
The data_from_core and oe_from_core signals are arranged in time slices that
are divided into the individual pins in the group. The first time slice is on the LSBs of
the buses, which matches the Intel FPGA PHY interface (AFI) bus ordering of the
External Memory Interfaces IP.
Example of time slices with individual pins correlation:
{time(n),time(n-1),time(n-2),... time(0)}
Where time0 = {pin(n),pin(n-1),pin(n-2),...pin0}
Figure 116. Example Output for Quarter Rate DDR
Related Information
• AFI 3.0 Specification
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5.2.4. Input Path

The input path of the IP consists of a data path, a strobe path, and a read enable
path.

This table lists the information about these paths.
Path Description
• PVT compensated delay chain—Allows per-bit deskew. You can only control the PVT compensated
delay chain over Avalon memory-mapped interface. For more information, refer to the Dynamic
Reconfiguration topic.
• data_in, data_in_n (input)—Input data from external device. data_in_n is used when data
configuration is set to Differential.
• data_io, data_io_n (bidirectional)—Input and output data from/to external device. data_io_n is
used when data configuration is set to Differential.
• data_to_core (output)—Output data to the Intel FPGA core.
used.
• strobe_in, strobe_in_n(input)—Input strobe from external device. strobe_in_n is used when
strobe configuration is set to Differential or Complimentary.
• strobe_io, strobe_io_n(bidirectional)—Input and output strobe from/to external device.
strobe_io_n is used when strobe configuration is set to Differential or Complimentary.
• dqs_clean(output)—This internal signal is the refined version of strobe_in signal.
• dqs(input)—This internal signal is an input strobe to DDIO and Read FIFO in the data path, after
Path
generation time based on the read latency that you provide. Individual control is not necessary, but if
you are modifying these delays you can do so individually using dynamic reconfiguration.
(Write latency = 0). During dynamic reconfiguration, the DQS_EN FIFO and interpolator can be used
for fine grained control of the strobe enable signal. Both of these delays are controlled by the Read
latency parameter for the group.
• rdata_valid(output)—This signal determines which data are valid when reading from Read FIFO.
This signal is delayed by the Read latency value set in the parameter editor.
• rdata_en(input)—This signal represents the number of expected words to read from the external
device.
• dqs_enable_in(input)—This is an internal signal that provides dqs delay value to the pstamble_reg
module to process a refined dqs signal.
continued...
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Path Description
• dqs_enable_out(output)— This is an internal strobe with the delayed value specified by the

This figure shows the input path of the IP.
To Intel FPGA core PHY Lite for Parallel Interfaces Intel FPGA IP Core To external interface
data_to_core data_in
Read FIFO DDIO Delay Chain data_in_n
6 phy_clk (1) 5 (PVT) data_io
5 data_io_n
strobe_in
strobe_in_n
(1) strobe_io
read_enable
(1) dqs strobe_io_n
(1) (3)
(PVT)
3
4
6
rdata_valid
dqs_enable_out (1)
1 2
rdata_en VFIFO
(2) (1)
DQS_EN FIFO
dqs_enable_in
(1)
phy_clk (1)
interpolator_clk
(1)
Legend:
Data path
Strobe path
(1)
(2)
Control signal
(3)
This module is uses the Capture Phase Shift parameter to generate the delay for the incoming strobe. n = sequence number.
n This represent read operation
sequence.
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Sequence Number
device).
FIFO modules.
The following figures show the waveform diagrams for the input path. The delays
Figure 118. Input Path ─ Read Latency 7

Intrinsic Delay Read Latency =7 PHY Lite for Parallel Interfaces Internal Delay
Measured from rdata_en assertion Number of clock cycles set through Latency between read data received to rdata_valid assertion.
to mem_rd assertion, sampling on the Read latency parameter
rising edge of mem_clk. in Parameter Editor
Debug signals are inside the lane wrapper.

Only available for waveform debugging.
CAPTURE_PHASE_SHIFT = 90
Related Information
• Input Path Signals on page 170
For more information about the IP input path signals.
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• How to estimate Intel Arria 10/Intel Stratix 10 PHY Lite Input and Output Path
Latency
How-to video on estimating PHY Lite for Parallel Interfaces IP input and output
path latency in Intel Arria 10 and Intel Stratix 10 devices.
5.2.4.1. Input Path Data Alignment
The bus ordering of data_to_core, rdata_en, and rdata_valid is identical to the

ordering of the output path. That is, the LSBs of the bus hold the first time slice of
data received.
The rdata_valid delay is always set by the IP to match the rdata_en alignment.
For example, quarter-rate delays are multiples of four external memory clock cycles
(one quarter rate clock cycle).
Figure 119. Example Input (Quarter Rate DDR) - Aligned

The waveform shows an example of aligned reads on the input path of the PHY Lite for Parallel Interfaces IP. At
the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows data of 4'hf, which
represents all incoming data are aligned. The group_0_rdata_valid bus shows the data of 4'hf, which
represents all incoming data are valid. Therefore, the incoming read data on the group_0_data_to_core bus
matches the data seen on the group_0_data_io bus.
Reading from an unaligned memory address is called unaligned reads. Unaligned

reads results in unaligned rdata_valid and data_to_core with data and valid
signals packed to the LSBs. This request causes the IP to do two or more read
operations.
Figure 120. Example Input (Quarter Rate DDR) - Unaligned

The waveform shows an example of unaligned reads on the input path of the PHY Lite for Parallel Interfaces IP.
The data from an unaligned read operation comes in two phases. At the first rising edge of the core_clk_out
signal, the group_0_rdata_en bus shows value of 4'he, which shows there are 6 bytes of incoming data from
group_0_data_io bus. On the subsequent clock cycle, the group_0_rdata_en bus shows value of 4'h1,
which shows there are 2 bytes of incoming data from group_0_data_io bus.
The valid data are transfer to the IP through the group_0_data_to_core bus. At first rising edge of the
core_clk_out signal, group_0_rdata_valid bus shows a value of 4'h7, which represents the first 6 bytes
of the data from the group_0_data_to_core bus are valid and the last 2 bytes are invalid. On the
subsequent clock cycle, group_0_rdata_valid bus shows the value of 4'h1, which shows the last 2 bytes of
the data from the group_0_data_to_core bus are valid.

Because of the asynchronous nature of the PHY, you must perform calibration to
achieve timing closure at a high frequency. At a high level, calibration involves
reconfiguring input and output delays in the PHY to align data and strobes. With the
PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices, you can perform
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the calibration by using dynamic reconfiguration feature. The dynamic reconfiguration

feature allows you to modify these delays by writing to a set of control registers using
an Avalon memory-mapped interface.
Important: When the dynamic reconfiguration feature is enabled in Stratix 10 devices, the
maximum Avalon memory-mapped interface speed is 167 MHz.
Related Information
• Calibrated VREF Settings on page 175
• Timing Closure: Dynamic Reconfiguration on page 184
5.2.5.1. RTL Connectivity
interface master and Avalon memory-mapped interface slave interfaces when you
enable the dynamic reconfiguration feature. If the generated IP is the only PHY Lite for
Parallel Interfaces Intel FPGA IP (with dynamic reconfiguration) or External Memory
Interface IP in the I/O column, connect only the Avalon memory-mapped interface
slave interface with a master in the core. Otherwise, connect Avalon memory-mapped
interface master and slave interfaces as described in the following section.
5.2.5.1.1. Daisy Chain
The I/O column provides a single physical Avalon memory-mapped interface. All IPs in
the I/O column that require Avalon memory-mapped interface access the same
physical Avalon memory-mapped interface. The system-level RTL for the column
reflects this resource limitation by using a daisy chain to connect all dynamically
reconfigurable IPs in an I/O column.
The PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices exposes a 31-
bit Avalon memory-mapped interface address, followed by a 4-bit interface ID. These
bits are only required for the daisy chain arbitration in RTL simulation, so they are not
synthesized during compilation. If only one interface is addressed from the IP, it is
sufficient to connect these bits as the interface’s ID.
Important: When using multiple PHY Lite for Parallel Interfaces Intel FPGA IPs, you are required to
specify the IP that is directly connected to the Avalon memory-mapped interface bus
master, using the First PHYLite Instance in the Avalon Chain parameter. Do not
select the parameter if there is an External Memory Interface IP selected as the first
instance in the chain, available in the same column.
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Figure 121. Logical RTL View to Physical Column Placement

This figure shows an example of a daisy chain consisting of the External Memory Interface and PHY Lite for
Parallel Interfaces Intel FPGA IP for Stratix 10 devices before and after placement.
Notice that all core controllers must go through the arbitration logic that you created
in the core logic to connect to an interface on the daisy chain. The end of the daisy
chain should have its master output interface tied to 0.
Note: The Fitter rearranges the Avalon memory-mapped interface address pins during
compilation, therefore use the postfit netlist for proper simulation of the merged I/O
column instead of prefit netlist.
5.2.5.2. Address Lookup
If you do not set the pin locations in the .qsf file, the lane addresses and pin
placement to an interface changes every time you compile your design in Quartus
Prime software. However, the PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix
10 devices is always generated as if the IP core is the only IP in a column, with lane
addresses starting from 0. You need to determine the lane and pin addresses in order
to dynamically reconfigure the calibration settings in the IP.
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Figure 122. Lane and Pin Placement Dependent Addresses

This figure shows two examples of a placed group with two lanes, 16 data pins and a differential strobe.
data_io[11]
Lane Address 8 data_io[10]
data_io[14]
PHY Lite for Parallel Interfaces Intel FPGA IP data_io[13]
strobe_io data_io[3]
Lane Address 0 strobe_io_n data_io[12]
data_io[0] data_io[1]
data_io[4]
data_io[5]
data_io[6] Lane Address 9 strobe_io
data_io[7] strobe_io_n
Lane Address 1 data_io[10] data_io[5]

data_io[11]
data_io[15]
data_io[12]
data_io[13]
data_io[15]
data_io[0]
Example 1 Example 2
To provide a unified way to look up reconfigurable feature addresses for a specific

interface both before and after placement, the address information is stored in
memory in the I/O column. This memory is addressable over the same Avalon
memory-mapped interface used for feature reconfiguration.
You can cache lookups 1 to 4 (8-bytes of information) to have pin and lane
translations in one look-up.
Table 84. Memory Lookup Components

This table lists the two main components of the memory lookup.
Global parameter table Stores pointers to the individual interface parameter tables. The global parameter table
lists all interfaces in the column (both the External Memory Interface and PHY Lite for
Parallel Interfaces Intel FPGA IP for Stratix 10 devices).
Set of individual interface Contain interface specific information. This is where pin-level and lane-level address look-
parameter tables ups are performed.
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Figure 123. Memory Overview in Stratix 10 Devices

32-bits (4 Byte Addresses)
{1’b0,id[3:0],27’h5000000}
Global Parameter Table
(One per column, same as EMIF)
{1’b0,id[3:0],27’h5000000 + 28’h24} Address Offset
{4’b1000,id[3:0], pt_ptr[23:0] 1
A {4'h8,id[3:0],8'h00,interface_table_ptr[15:0]}
B
{1’b0,id[3:0],27’h5000000} + pt_ptr PT_VER[15:0],IP_VER[15:0]
{1’b0,id[3:0],27’h5000000} + pt_ptr 28’d4 Number of Groups 2 group_offset = grp_num -1
{1’b0,id[3:0],27’h5000000} + pt_ptr 28’d8 3 num_lanes[1:0],num_pins[5:0]
Number of Groups
Parameter Table
(PHY Lite Specific) {1’b0,id[3:0],27’h5000000} + pt_ptr + lane_offset[31:16],pin_offset[15:0]
Number of Groups lane_ptr[15:0],pin_ptr[15:0] 4
{18’h0,group_offset[5:2],2’b00} +
{21’d0,num_grps,2’b00} + 28h’C
One per Interface
{1’b0,id[3:0],27’h5000000} + lane_ptr + lane_num Group 0 Lane 0 5

Needed for simplifying
Lane Address Table strobe feature logic
(PHY Lite Specific) address lookups
D
{1’b0,id[3:0],27’h5000000} + pin_ptr + {17’h0,pin_num[5:0],1’b0} Group 0 Pin 1 Group 0 Pin 0 6
Needed for pin
address lookups
Pin Address Table
(PHY Lite Specific)
A The MSB of the interface pointer entry in the global parameter table is 1 for PHY Lite interfaces.
B num_lanes[1:0] starts counting at 0. For example, 0 = 1 lane, 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes
C Lane address table information: Group X Lane Y = lane_addr[7:0]
D Pin address table information: Group X Pin Y = {lane_addr[7:0],0xF,pin[3:0]} for data and
{lane_addr[7:0],0xE,pin[3:0]} for strobe
Below are the steps to determine the lane and pin addresses from the lookup tables
(the sequence corresponds to the sequence in the Memory Overview in Stratix 10
Devices topic):
Table 85. Parameter Table Lookup Operation Sequence

The base address for PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices is 27'h5000000.
Legend in Description
Memory
Overview in
Stratix 10
Devices
1 Search for Interface Parameter Table in Global Parameter Table (cache once per interface)
• {1'b0,id{3:0],27'h5000000} + 28'h24 to {1'b0,id{3:0],27'h5000000} + 28'h3C
• 1 to 11 look-ups
2 Retrieve number of groups in the interface (cache once per interface)

• {1'b0,id[3:0],27'h5000000} + {12'h0,pt_ptr[15:0]} + 28'h4
• You can skip this sequence if the number of groups is saved in the core during compilation (for
example, hard coded in RTL logic)
3 Retrieve group information (cache once per group)

• {1'b0,id[3:0],27'h5000000} + {12'h0,pt_ptr[15:0]} + 28'h8 + grp_num
• Not always necessary
4 Retrieve Lane/Pin Address Offsets for group (cache once per group)
• {1'b0,id[3:0],27'h5000000} + {12'h0,pt_ptr[15:0]} +
{18'h0,group_offset[5:2],2'b00} + {21'd0, grp_num, 2'b00} + 28'hC
5 Perform lane/pin address translation (cache once per pin)

continued...
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Memory
Overview in
Stratix 10
Devices
• {1'b0,id[3:0],27'h5000000} + {12'h000,lane_ptr[15:0]} + lane_num

• {1'b0,id[3:0],27'h5000000} + {12'h000,pin_ptr[15:0]} + {17'h0,pin_num[5:0],
1'b0}
6 Read/Write Avalon Calibration Bus

• {1'b0,id[3:0],27'h5000000} + read_from_step_4 + intra_lane_addr
5.2.5.2.1. Strobes
The first pins listed in the pin address lookup table are the strobes. They are also
identified by bits[7:4] = 0xE. For separate strobes, the input strobe pin placement
always take precedence. For differential and complementary strobes, the positive pin
is the lower index.
Note: You can modify the output phase of differential strobes by writing to either the positive
or negative pin. Only one write is necessary. This is also the case for output-only
complementary strobes.
5.2.5.2.2. Parameter Table Examples
Single PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 Devices
The following figure shows an example of the design containing a single PHY Lite for
Parallel Interfaces Intel FPGA IP for Stratix 10 devices with one bidirectional group
composed of four data bits and one strobe. Refer to the Example of Identifying the
Lane and Pin Addresses from Parameter Table to determine the lane and pin addresses
from the parameter table.
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Figure 124. Parameter Table Example for Stratix 10 Devices
Table 86. Example of Identifying the Lane and Pin Addresses from Parameter Table
Step Address Address Value Data Description
To access the Base address 27’h5000000 — —

parameter table.
To determine the size Base address + 27’h5000000 + 0000007C The size of the
of the parameter table 24’h14 24’h14 = parameter table is 7C
by generating an 27’h5000014 that means the
address information about PHY
Lite is from address
27’h5000000 to
27’h500007C.
To determine the Base address + 27’h5000000 + 8000005C • Bit[1:0]: 5C

address offset of 27’h24 27’h24 = address offset
PHY Lite in parameter 27’h5000024 point to PHY Lite
table. • Bit[6]: PHY Lite
interface ID
• {4’h0,
pt_ptr[23:0]} is
5C
To determine the Base address + 27’h5000000 + 00000001 1 indicates the

number of groups in {12'h0,pt_ptr[15:0]} 27’h000005C + number of groups in
PHY Lite for interfaces + 27'h4 27’h4= 27’h5000060 this PHY Lite.
continued...
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To determine the Base address + 27’h5000000 + 00000005 • Bit[5:0]:

group information {12'h0,pt_ptr[15:0]} 27’h000005C + 27’h8 num_pins[5:0]
that includes the + 28'h8 = 27’h5000064 represents 5 pins
number of lanes and • Bit[7:6]:
number of pins num_lanes[7:6]
represents 1 lane
To determine lane Base address + 27’h5000000 + 006C0070 • Bit[3:0]:

offset and pin offset {12'h0,pt_ptr[15:0]} 27’h500005C + 28’hC pin_off[15:0] =
+ 28'hC = 27’h5000068 pin_off = 070
• Bit[7:4]:
lane_off[31:16],
means lane_off =
06C
• lane_ptr = 06C
and pin_ptr= 070
To determine the lane Base address + + 27’h5000000 + 00000000 Lane address is 0x00
address {12'h000,lane_ptr[15: 28’h6C =
0]} 27’h500006C
To determine the pin Base address + + 27’h5000000 + 23F123E0 • Bit[3:0]: strobe_io

address at {12'h000,pin_ptr[15: 28’h70 = = lane 0x23, pin 0
27’h5000070 to 0]} 27’h5000070 • Bit[7:4]:
27’h500007C data_io[0] = lane
0x23, pin 1
5000074 23F323F2 • Bit[3:0]:

data_io[1] = lane
0x23, pin 2
• Bit[7:4]:
data_io[2] = lane
0x23, pin 3
5000078 000023F4 • Bit[3:0]:

data_io[3] = lane
0x23, pin 4
27’h500007C 00000000 End of the address
Note: {lane_addr[7:0], 0xE, pin[3:0]} for strobe and {lane_addr[7:0], 0xF, pin[3:0]} for
data.
Two PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 Devices
The following figure shows an example of a design containing two PHY Lite for Parallel
Interfaces Intel FPGA IP for Stratix 10 devices, each with one bidirectional group
composed of four data bits and one strobe. Both interfaces are in the same I/O
column, and therefore must merge the tables.
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Figure 125. Parameter Table Example for Stratix 10 Devices

PHY Lite for Parallel Interfaces IP core 0 PHY Lite for Parallel Interfaces IP core 1 Merged Column Parameter Table
Addr Data Addr Data Addr Data
5000000 00000002 5000000 00000002 5000000 00000002
5000004 00000001 5000004 00000001 5000004 00000001
5000008 00000001 5000008 00000001 5000008 00000001
500000C 00000008 500000C 00000008 500000C 00000008
5000010 001312D0 5000010 001312D0 5000010 001312D0
5000014 0000007C 5000014 0000007C 5000014 0000007C
5000018 00000000 5000018 00000000 5000018 00000000
500001C 00000000 500001C 00000000 500001C 00000000
5000020 0000001E 5000020 0000001E 5000020 0000001E
5000024 8000005C 5000024 8100005C Interface 5000024 8000005C
Interface
5000028 00000000 5000028 00000000 pointer 5000028 8100007C
pointer
500002C 00000000 500002C 00000000 500002C 00000000
5000030 00000000 5000030 00000000 5000030 00000000
5000034 00000000 5000034 00000000 5000034 00000000
5000038 00000000 5000038 00000000 5000038 00000000
500003C 00000000 500003C 00000000 500003C 00000000
5000040 00000000 5000040 00000000 5000040 00000000
5000044 00000000 5000044 00000000 5000044 00000000
5000048 00000000 5000048 00000000 5000048 00000000
500004C 00000000 500004C 00000000 500004C 00000000
5000050 00000000 5000050 00000000 5000050 00000000
5000054 00000000 5000054 00000000 5000054 00000000 PHY Lite
5000058 00000000 5000058 00000000 5000058 00000000 for Parallel
1 group with 5 500005C 00014440 500005C 00014440 500005C 00014440 Interfaces
pins and 1 5000060 00000001 5000060 00000001 Number of group 5000060 00000001 IP core 0
lane in the 5000064 00000005 5000064 00000005 Group 0 – 5 pins, 1 lane 5000064 00000005
strobe_io = lane 0x23,pin 4
interface 5000068 006C0070 5000068 006C0070 5000068 006C0070
500006C 00000000 Pin pointer 500006C 00000000 500006C 00000000 data_io [ 0 ] = lane 0x23, pin 10
5000070 23F123E0 5000070 32F132E0 5000070 23FA23E4 data_io [ 1 ] = lane 0x23, pin 3
5000074 23F323F2 5000074 32F332F2 5000074 23F623F3 data_io [ 2 ] = lane 0x23, pin 6
5000078 000023F4 5000078 000032F4 5000078 000023F7 data_io [ 3 ] = lane 0x23, pin 7
500007C 00014440
Lane pointer 5000080 PHY Lite 00000001
5000084 for Parallel 00000005
strobe_io = lane 0x32,pin 0 5000088 Interfaces 008C0090 strobe_io = lane 0x32,pin 4
strobe_io = lane 0x23,pin 0
data_io [ 0 ] = lane 0x32, pin 1 500008C IP core 1 00000000 data_io [ 0 ] = lane 0x32, pin 3
data_io [ 0 ] = lane 0x23, pin 1
data_io [ 1 ] = lane 0x32, pin 2 data_io [ 1 ] = lane 0x32, pin 6
data_io [ 1 ] = lane 0x23, pin 2 5000090 32F332E4
data_io [ 2 ] = lane 0x32, pin 3 5000094 32FA32F6 data_io [ 2 ] = lane 0x32, pin 10
data_io [ 3 ] = lane 0x32, pin 4 5000098 000032F7 data_io [ 3 ] = lane 0x32, pin 7
Important: There is no guarantee of the ordering of the interface parameter tables in the merged
table. You must perform a search to locate a specific interface parameter.
For more information about the contents of the parameter table, refer to the Address
Lookup topic.
Related Information
Address Lookup on page 143
is placement dependent. If PHY Lite for Parallel Interfaces Intel FPGA IPs and the
External Memory Interface IPs share the same I/O column, you must track the
addresses of the interface lanes and the pins.
There are two sets of control registers that store the reconfiguration feature settings:
• Control/Status registers (CSR) - you can only read the values of these registers.
• Avalon memory-mapped interface registers - you can read and write to these
registers using Avalon memory-mapped interface. The time for the the PHY Lite
for Parallel Interfaces Intel FPGA IP delays to change after writing a new value to
the registers via the Avalon memory-mapped interface bus is dependent on the
user's configuration. For example, it takes approximately 50 VCO clock cycles for
the output delay to change value. Perform an RTL simulation to show an accurate
timing which correlates to the hardware operation.
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5.2.5.3.1. PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 Devices Control
Registers Addresses
The following tables show the register bits to construct the control register addresses
for each feature.
Table 87. Control Register Address for Pin Output Delay Feature
Bit Description Avalon MM Register CSR Register
Value Access Type Value Access

Type
[30:27] Specify the PHY Lite for Depending on the RW Depending on the RO
Parallel Interfaces Intel Interface ID Interface ID
FPGA IP interface ID. parameter in the parameter in the
Parameter Editor. Parameter Editor.
[26:24] Specify the Avalon 3'h3 RW 3'h3 RO

controller calibration bus
base address.
[23:21] Reserved 3'h0 RW 3'h0 RO
[20:13] Specify the lane address You can query this RW You can query this RO
of an interface. This value in the Parameter in the Parameter
is depending on the Table Lookup Table Lookup
resource fitting process Operation Sequence Operation Sequence
during compilation. as described in the as described in the
Address Lookup Address Lookup
topic. topic.
[12:8] Specify the address for You can query this RW You can query this RO
the physical location of a in the Parameter in the Parameter
pin within a lane. Table Lookup Table Lookup
Operation Sequence Operation Sequence
as described in the as described in the
topic or based on topic or based on
your pin assignment your pin assignment
setting in the .qsf setting in the .qsf
file. file.
[7:0] Reserved 8'hD0 RW 8'hE8 RO
Table 88. Address Register for Pin Input Delay Feature

Bit Description Avalon Memory-Mapped Interface CSR Register
Register

Type
[30:27] Specify the PHY Lite for Depending on the RW N/A RO

Parallel Interfaces Intel Interface ID
FPGA IP interface ID. parameter in the
Parameter Editor.
[26:24] Specify the Avalon 3'h3 RW N/A RO

base address.
[23:21] Reserved 3'h0 RW N/A RO
[20:13] Specify the lane address You can query this RW N/A RO
of an interface. This value in the Parameter
is depending on the Table Lookup
resource fitting process Operation Sequence
during compilation.
continued...
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Register

Type
as described in the
Address Lookup
topic.
[12:9] Reserved 4'hC RW N/A RO
[8:7] Select DQ pin sets to • 2'h1: DQ 0 to RW N/A RO

access. DQ 5
• 2'h2: DQ 6 to
DQ11
[6:4] Select the specific DQ pin • 3'h0: DQ 0 and RW N/A RO

to access. DQ 6
• 3'h1: DQ 1 and
DQ 7
• 3'h2: DQ 2 and
DQ 8
• 3'h3: DQ 3 and
DQ 9
• 3'h4: DQ 4 and
DQ 10
• 3'h5: DQ 5 and
DQ 11
Table 89. Address Register for Strobe Input Delay Feature

Register

Type

Parameter Editor.

base address.
[20:13] Specify the lane address You can query this RW N/A RO
of an interface. This value in the Parameter
is depending on the Table Lookup
resource fitting process Operation Sequence
during compilation. as described in the
Address Lookup
topic.
[12:0] Reserved 13'h18E0 RW N/A RO
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Table 90. Address Register for Strobe Enable Phase Feature

Bit Description Avalon Memory-Mapped Interface MM CSR Register
Register

Type

base address.
topic. topic.
[12:0] Reserved 13'h18F0 RW 13'h1998 RO
Table 91. Address Register for Strobe Enable Delay Feature

Register

Type

base address.
topic. topic.
[12:0] Reserved 13'h1808 RW 13'h19A8 RO
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Table 92. Address Register for Read Valid Delay Feature

Register

Type

base address.
topic. topic.
[12:0] Reserved 13'h180C RW 13'h19A4 RO
Related Information
5.2.5.3.2. Control Registers Description
memory-mapped interface returns a set of values from the control registers. The
following tables show the definition of the bits for each control register.
Table 93. Control Register Description

Pin Output Delay [31:13] Reserved (12)
[12:0] Phase value

Strobe minimum setting: Refer to the Output and
Strobe Enable Minimum and Maximum Phase
Settings topic.
Strobe maximum setting: Refer to the Output and
Settings topic.
Incremental Delay: 1/128th VCO clock period
The CSR value for DQS is set through the Output
Strobe Phase parameter during IP instantiation.
Note: The pin output delay switches from the CSR
register value to the Avalon register value
after the first Avalon write. It is only reset to
the CSR register value on a reset of the
interface.
Pin Input Delay [31:13] Reserved (12)
continued...
(12) Reserved bit ranges must be zero
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[12] Enable bit to select access to Avalon register or CSR

register.
0 = Delay value is 0. CSR register is not available for
this feature.
1 = Select delay value from Avalon register
[11:9] Reserved (12)
[8:0] Delay value

Minimum Setting: 0
Maximum Setting: 511 VCO clock periods
Strobe Input Delay [31:13] Reserved (12)

register.
this feature.
Modifying these values must be done on all lanes in a
group.
[11:10] Reserved(12)
[9:0] Delay value

Minimum Setting: 0
group.
Strobe Enable Phase [31:16] Reserved (12)

register.
0 = Select delay value from CSR register. The CSR
value is set through the Capture Strobe Phase
Shift parameter during IP instantiation.
group.
[12:0] Bit [12:0]: Phase value

Minimum Setting: Refer to the Output and Strobe
Maximum Setting: Refer to the Output and Strobe
group.
Strobe Enable Delay [31:16] Reserved(12)

register.
0 = Select delay value from CSR register
group.
[14:6] Reserved(12)
continued...
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[5:0] Delay value

Minimum Setting: 0 external clock cycles
Maximum Setting: 63 external memory clock cycles
Incremental Delay: 1 external memory clock cycle
group.
Read Valid Delay [31:16] Reserved(12)

register.
group.
[14:7] Reserved
[6:0] Delay value

group.
Important: For more information about performing various clocking and delay calculations,
depending on the interface frequency and rate, refer to
PHYLite_delay_calculations.xlsx.
Related Information
Output and Strobe Enable Minimum and Maximum Phase Settings on page 160
Example of Accessing Dynamic Reconfiguration Control Registers using Parameter Table
The example shows the steps to access Pin Output Delay CSR control register for a
strobe pin with the following PHY Lite for Parallel Interfaces Intel FPGA IP settings in
Stratix 10 devices:
• Number of groups: 2. The group index is automatically set to 0x00.
• Interface ID: 0x00
• Pin width: 4
• Strobe configuration: Single ended
• Avalon controller calibration bus base address: 0x3000000
After the project compilation, the interface ID, lane address and pin addresses are
stored in the parameter table.
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PHYLite for Parallel Inter faces IP core 0

Addr Data
000 00000002
004 00000001
008 00000001
00C 00000008
010 001312D0
014 0000007C
018 00000000
01C 00000000
020 0000001E
024 8000005C
028 00000000
02C 00000000
PHY Lite Interface ID 030 00000000
034 00000000 Pointer to interfaces
038 00000000
03C 00000000
040 00000000
044 00000000
048 00000000
04C 00000000
050 00000000
054 00000000
058 00000000
05C 00014440
060 00000002 Number of groups:2
Lane number [7:6]: 00 (1 lane)
064 00000505
Pins number [5:0]: 0101 (5 pins)
068 00700074 Pointer to Pin address
06C 0071007e
Pointer to Lane address 070 0000494b Lane address for group 0 = 0x4b
074 4bf64be4 Lane address for group 1=0x49
078 4bf74bf9
07C 49e44bf2
080 49f949f6
084 49f349f8
strobe_io = lane 0x4b, pin address:4

data_io = lane 0x4b, pin address: 6
strobe_io = lane 0x49, pin address:4 data_io = lane 0x4b, pin address: 9
data_io = lane 0x49, pin address: 6 data_io = lane 0x4b, pin address: 7
data_io = lane 0x49, pin address: 9 data_io = lane 0x4b, pin address: 2
data_io = lane 0x49, pin address: 8
data_io = lane 0x49, pin address: 3
The Pin Output Delay CSR control register has the following bit definition:
Bit Description Avalon Memory-Mapped Interface
Register Value
[30:27] Specify the PHY Lite for Parallel Interfaces Intel 0x00 (Interface ID from parameter
FPGA IP interface ID. table)
[26:24] Specify the Avalon controller calibration bus base 0x3

address.
[23:21] Reserved 0x00

continued...
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Bit Description Avalon Memory-Mapped Interface

Register Value
[20:13] Specify the lane address of an interface. This value 0x4b (Lane address from parameter
is depending on the resource fitting process during table)
compilation.
[12:8] Specify the address for the physical location of a pin 0x04 (Strobe pin address from
within a lane. parameter table)
[7:0] Reserved 0xe8
To read the Pin Output Delay CSR control register for a strobe pin, use the command
avl_in_address[30:0] = {interface id[30:27], calibration bus address[26:24],
Reserved[23:21], lanes address[20:13], pin address[12:8], reserved[7:0]}
avl_in_address[30:0] = {0x00, 0x3, 0x00, 0x4B, 0x04, 0xE8}
5.2.5.4. Calibration Guidelines
The PHY Lite for Parallel Interfaces Stratix 10 FPGA IP allows you to dynamically
reconfigure the features of the interface. However, performing calibration is an
application specific process. This section provides some general guidelines for
calibrating Stratix 10 I/O architecture.
Note: Follow the guidelines when generating your own dynamic reconfiguration controller.
Related Information
rdata_en to high.

one core clock cycle,eight strobes are toggled. Ideally, in normal PHY state, after the
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Figure 126. Input Path of PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10
Devices Core
data_in
(PVT) data_io_n
strobe_in
strobe_in_n
dqs strobe_io
dqs_clean
(PVT)
rdata_valid
dqs_enable_out
rdata_en
phy_clk
interpolator_clk

red marker).
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rdata_en
gate (internal)
rdata_en
gate (internal)
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rdata_en
gate (internal)
When dynamically reconfiguring the interpolator phase settings, the values must be
kept within the ranges below to ensure proper operation of the circuitry.
Minimum Interpolator Phase
VCO
Maximum Interpolator
Multiplication Core Rate
Output Bidirectional Bidirectional with Phase
Factor
OCT Enabled
1 Full 0x080 0x100 0x100 0xA80
Half 0x080 0x100 0x100 0xBC0
Quarter 0x080 0x100 0x100 0xA00
2 Full 0x080 0x100 0x180 0x1400
Half 0x080 0x100 0x180 0x1400
Quarter 0x080 0x100 0x180 0x1400
4 Full 0x080 0x100 0x280 0x1FFF
Half 0x080 0x100 0x280 0x1FFF
8 Full 0x080 0x100 0x480 0x1FFF
Half 0x080 0x100 0x480 0x1FFF
For more information about performing various clocking and delay calculations,

You can instantiate the PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10
devices from IP Catalog in Quartus Prime software. Intel provides an integrated
parameter editor that allows you to customize this IP to support a wide variety of
applications.
160
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Related Information
version upgrades.

Table 95. PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 Devices
Parameter Settings
Values
Parameter

Clocks
Interface clock frequency 100 MHz - 1200 533.0 MHz External memory clock frequency.
MHz Note: To achieve timing closure at 534 MHz
and above, use dynamic reconfiguration
to calibrate the interface. Compile your
design with Quartus Prime with accurate
board skew information for final timing
analysis.
desired memory clock of this frequency to the PLL reference
clock frequency clock input of the memory interface.
Note: There is no minimum range, but the
maximum output frequency is 1600 MHz,
limited by the clock network. The
minimum range for the ref_clk signal
is 10 MHz but the maximum is
dependent on the speed grade.
Clock rate of user logic Full, Half, Quarter Quarter Determines the clock frequency of user logic in
Specify additional output On, Off Off Exposes additional output clocks from the
clocks based on existing PLL existing PLL.
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Values
Output Clocks
Note: These parameters are available only if the Specify additional output clocks based on existing PLL parameter
is turned on
Number of additional clocks 0 to 4 0 Specifies the number of additional clocks to be

exposed.
outclk[4:0] (Reserved) — — PLL output clocks with the flag (Reserved) in the
QSYS GUI are reserved for PHY Lite for Parallel
Interfaces Stratix 10 FPGA IP internal
functionality.
Desired Frequency — 133.25 MHz Specifies the output clock frequency of the
corresponding output clock port, outclk[], in
MHz. The minimum and maximum values
depend on the device used. The PLL only reads
the numerals in the first six decimal places.
Actual Frequency — 133.25 MHz Allows you to select the actual output clock
frequency from a list of achievable frequencies.
Phase shift units ps or degrees ps Specifies the phase shift unit for the
picoseconds (ps) or degrees.
Phase shift — 469.0 ps Specifies the requested value for the phase
shift. The default value is 0 ps.
Actual phase shift — 469.0 ps Allows you to select the actual phase shift from
a list of achievable phase shift values. The
default value is the closest achievable phase
shift to the desired phase shift.
Desired duty cycle 0.0–100.0 50.0 % Specifies the requested value for the duty cycle.
Actual duty cycle — 50.0 % Allows you to select the actual duty cycle from a
list of achievable duty cycle values. The default
value is the closest achievable duty cycle to the
desired duty cycle.
PHY Lite for Parallel Interfaces Stratix 10 FPGA
IP settings.
First PHYLite Instance in the On, Off On Select this parameter if this IP instance is the
Avalon Chain first instance in the Avalon chain, connected to
the master.
This parameter is only available when you select
Use dynamic reconfiguration .
Important: Do not select this parameter if
there is an External Memory
Interface IP selected as the first
instance in the chain, available in
the same column.
Interface ID — 0 The ID used to identify this interface in the I/O

column over the Avalon memory-mapped bus.
I/O Settings
I/O standard SSTL-12 SSTL-15 Class Specifies the I/O standard of the interface's
SSTL-125 I strobe and data pins written to the .qip file of
the IP instance. When you choose None, the
SSTL-135
I/O standard is unspecified in the generated IP.
continued...
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Values
SSTL-15
SSTL-15 Class I
SSTL-15 Class II
SSTL-18 Class I
SSTL-18 Class II
1.2-V-HSTL Class
I
1.2-V-HSTL Class
II
1.5-V-HSTL Class
I
1.5-V-HSTL Class
II
1.8-V-HSTL Class
I
1.8-V-HSTL Class
II
1.2-V POD
1.2-V
1.5-V
1.8-V
None
configuration LVDS with on-
chip termination,
LVDS without on-
chip termination
General Settings
Fast simulation model On, Off Off Turn on this option to reduce PHY Lite for
Parallel Interfaces Stratix 10 FPGA IP simulation
time.
Note: This option is preliminarily supported in
Quartus Prime v18.1.
Group <x> Parameter Settings
Copy parameters from another On, Off Off Select this option when you want to copy the
group parameter settings from another group.
Set Number of groups to more than 1 to
enable this option.
Group 1 - 17 1 Choose the group index that you want as the

parameter settings source. The changes made
to the source is updated automatically to all the
target groups.
You can only choose the group index which the
parameter settings are not copied from another
group.
enable this option.

continued...
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Values
Pin width 1 to 48 9 Number of pins in this data/strobe group.

A data width up to 48 is achievable if no strobe
is used in the group. The number of strobes is
controlled by the Use output strobe, Strobe
configuration and Use separate capture
strobe parameters.


cycles For example, a design with an external clock
frequency of 533 MHz in half-rate has a valid
read latency range of 5 to 63 external interface
clock cycles.
Refer to the Read Latency topic for minimum
rate.
Swap capture strobe polarity On, Off Off Internally swap the negative and positive
capture strobe input pins. This feature is only
available for complementary strobe
configurations.
Capture strobe phase shift 0, 45, 90, 135, 90 Internally phase shift the input strobe relative to
180 input data.

Write latency 0 to 3 (maximum 0 Additional delay added to the output data in

value is memory clock cycles.
dependent on the Refer to the Write Latency topic for write latency
rate) settings based on FPGA core clock rate.
Use output strobe On, Off On Use an output strobe.
180 output data.
Group <x> General Data Settings

Data configuration Single ended Single ended Selects the type of data. Single ended data type
uses one pin. Differential data type uses 2 pins.
PHY Lite for Parallel Interfaces Stratix 10 FPGA
IP does not support differential data pins.
Refer to the I/O Standards topic for a list of

Strobe configuration Single ended, Single ended Select the type of strobe. A single ended strobe
Differential, uses one pin, which reduces the maximum
Complementary possible number of data pins in the group to 47.
Differential/complementary strobe types use 2
pins, which reduces the maximum possible
number of data pins in the group to 46.
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Values
Note: The differential strobe configuration uses

DDIO and read FIFO. The
complementary strobe configuration
uses two single-ended input buffers and
clocks the data into the capture DDIO
and read FIFO using both clocks (as
required by protocols such as QDRII).
The output path functionality is the
same.
Use separate strobes On, Off Off Separate the bidirectional strobe into input and
output strobe pins. Use separate strobes is only
available for a bidirectional data group with the
output strobe enabled.

OCT enable size 0 - 15 (Stratix 10 1 Specifies the delay between the OCT enable
devices) signal assertion and the dqs_enable signal
assertion. You must set a value that is large
Expose termination ports On, Off Off Turn on to expose the series and parallel
termination ports to connect separate OCT
block.
To enable this option, turn off Use Default OCT
Values parameter and select a value for Input
OCT Value or Output OCT Value parameters.
Use Default OCT Values — — Use default OCT values based on the I/O
Input OCT Value No termination, No Specifies the group's data and strobe input
<n> ohm with termination termination values to be written to the .qip of
calibration the IP instance. The list of legal values is
dependent on the I/O standard parameter
setting. Refer to the I/O Standards topic.
This option is available when the Use Default
OCT Values option is disabled.
Output OCT Value No termination, No Specifies the group's data and strobe input
calibration, <n> the IP instance. The list of legal values is
with no dependent on the I/O standard parameter
calibration setting. Refer to the I/O Standards topic
Group <x> Timing Settings

Generate Input Delay On, Off On Instructs SDC to generate set_input_delay

Constraints for this group constraints for this group.
Input Strobe Setup Delay Constraint in ns 0.03 ns Specifies the group's input setup delay
Constraint constraint against the input strobe.
Input Strobe Hold Delay Constraint in ns 0.03 ns Specifies the group's input hold delay constraint
Constraint against the input strobe.
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Values
Inter Symbol Interference of Constraint in ns 0.09 ns Specifies the Inter Symbol Interference value
the Read Channel for DQS signal of read channel.
Specify a positive value to decrease the setup
and hold slack by half of the entered value.
Generate Output Delay On, Off On Instructs SDC to generate set_output_delay

Output Strobe Setup Delay Constraint in ns 0.03 ns Specifies the group's output setup delay
Output Strobe Hold Delay Constraint in ns 0.03 ns Specifies the group's output hold delay
the Write Channel for DQS signal of write channel.
Group <x> Dynamic Reconfiguration Timing Settings

Dynamic Reconfiguration Read DQ Per-Bit DQ Per-Bit Specifies the Read Deskew algorithm for Timing
Deskew Algorithm Deskew, DQ Deskew Analyzer to use when performing I/O timing
Group Deskew, analysis:
Custom Deskew • DQ Per-Bit Deskew: Each DQ pin is adjusted
independently to minimize the skew within
the DQ bits. DQS signal is adjusted to center-
align to the de-skewed DQ bus. Each DQ bit
may have different delay chain settings.
• DQ Group Deskew: DQS signal is adjusted
center-align to the DQ bus without de-
skewing individual DQ bits. All DQ bits within
the same group has same delay chain
settings.
• Custom Deskew: DQS is aligned based on
the recoverable setup and hold slack you
defined.
You must select Use dynamic reconfiguration
option to enable this parameter.
Setup Slack Recoverable of Constraint in ns 0.0 ns Specifies the amount of positive setup slack
Custom Read Deskew available based on your custom read deskew
Algorithm algorithm.
This parameter is available with the conditions:
• Use dynamic reconfiguration is turn on
• Pin type is set to Input or Bidirectional
and
• Dynamic Reconfiguration Read Deskew
Algorithm is set to Custom Deskew
Hold Slack Recoverable of Constraint in ns 0.0 ns Specifies the amount of positive hold slack
and
continued...
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Values
Dynamic Reconfiguration DQ Per-Bit DQ Per-Bit Specifies the Write Deskew algorithm for Timing
Write Deskew Algorithm Deskew, DQ Deskew Analyzer to use when performing I/O timing
Custom Deskew • DQ Per-Bit Deskew: DQS signal is centered to
each individual DQ bits. Each DQ bit may
have different delay chain settings.
• DQ Group Deskew: DQS signal is centered to
the DQ bus group. All DQ bits within the
same group has same delay chain settings.
defined.
Custom Write Deskew available based on your custom write deskew
• Pin type is set to Output or Bidirectional
and
• Dynamic Reconfiguration Write Deskew
and
Related Information
• Read Latency on page 167
• Write Latency on page 168
devices.

This table shows the minimum read latency value supported by PHY Lite for Parallel Interfaces Intel FPGA IP
based on the core clock rate and VCO multiplier factor settings.
Cycle)
Full rate 1 4
2 4
continued...
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Cycle)
4 3
8 3
Half rate 1 5
2 5
4 4
8 4
Quarter rate 1 7
2 7
4 7
8 7

This shows the maximum write latency value supported by PHY Lite for Parallel Interfaces Intel FPGA IP based
on the core clock rate and VCO multiplier factor settings.

Core Clock Rate
Cycle)
Full rate 1 0
2 0
4 0
8 0
Half rate 1 1
2 1
4 1
8 1
Quarter rate 1 3
2 3
4 3
8 2
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5.3.2. Signals

synchronous with strobe_in to ensure the dqs_enable signal
is in-sync with strobe_in.
reset_n Input 1 Resets the interface. This signal is asynchronous.
interface_locked Output 1 Interface locked signal from PHY Lite for Parallel Interfaces Intel
FPGA IP for Stratix 10 devices to core logic. This signal indicates
that the PLL and PHY circuitry are locked.
Data transfer should starts after the assertion of this signal.
pll_extra_clock[0..3] Output 4 These are the additional output clock signals generated by PHY
Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices
when you enable Specify additional output clocks based on
existing PLL parameter.
pll_locked Output 1 This is the locked signal for the additional output clocks generated
by the IP.

Output path signals are signals that are available when you set the Pin Types parameter to either Output or
group_<n>_oe_from_ Input Quarter-rate: 4 x PIN_WIDTH Output enable signal from core logic.
core Half-rate: 2 x PIN_WIDTH Synchronous to the core_clk_out
output from the IP.
Full-rate: 1 x PIN_WIDTH
Quarter rate-DDR: 8 x PIN_WIDTH

Half-rate DDR: 4 x PIN_WIDTH
Full-rate DDR: 2 x PIN_WIDTH Data signal from core logic.
group_<n>_data_fro
Input Synchronous to the core_clk_out
m_core Quarter-rate SDR: 4 x PIN_WIDTH output from the IP.
Half-rate SDR: 2 x PIN_WIDTH
Full-rate SDR: 1 x PIN_WIDTH
group_<n>_strobe_o Input Quarter-rate: 8 Strobe signal from core logic.

ut_in Half-rate: 4 Synchronous to the core_clk_out
Full-rate: 2 output from the IP.
Note: This path is always DDR.
group_<n>_strobe_o Input Quarter-rate: 4 Strobe output enable from core logic.

ut_en Half-rate: 2 Synchronous to the core_clk_out
group_<n>_data_out Output/ 1 to 48 if data configuration is Single Data output from PHY Lite for Parallel
/group_<n>_data_io Bidirectional Ended Interfaces Stratix 10 FPGA IP.
Synchronous to the
continued...
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group_<n>_strobe_out or
group_<n>_strobe_io output from
the IP.
Output, the group_<n>_data_out
signals are used. If the Pin Type
parameter is set to Bidirectional,
the group_<n>_data_io signals are
used.
Note: PHY Lite for Parallel Interfaces
Intel FPGA IP for Stratix 10
devices does not support
differential data pins.
group_<n>_strobe_o Output/ 1 Positive output strobe fromPHY Lite

ut / Bidirectional for Parallel Interfaces Intel FPGA IP
group_<n>_strobe_i for Stratix 10 devices. If the Pin Type
o is set to Output, the
group_<n>_strobe_out signal is
Bidirectional the
used. The Use Separate Strobes
parameter forces the use of the
group_<n>_strobe_out signal with
a Bidirectional Pin Type.
group_<n>_strobe_o Output/ 1 Negative output strobe from PHY Lite

ut_n / Bidirectional for Parallel Interfaces Intel FPGA IP
group_<n>_strobe_i for Stratix 10 devices.
o_n This is used if the Strobe
Configuration is set to Differential
or Complementary.
Bidirectional, the
used. The Use Separate Strobes
parameter forces the use of the
group_<n>_strobe_out_n signal
with a Bidirectional Pin Type.

group_<n>_data_t Output Quarter-rate DDR: 8 x PIN_WIDTH Output data to the core logic. Valid
o_core Half-rate DDR: 4 x PIN_WIDTH on rdata_valid. Synchronous to
the core_clk output from the PHY
Full-rate DDR: 2 x PIN_WIDTH
Lite for Parallel Interfaces Intel FPGA
Quarter-rate SDR: 4 x PIN_WIDTH IP for Stratix 10 devices.
group_<n>_rdata_ Input Quarter-rate: 4 This signal represents the number of

en Half-rate: 2 expected words to read from the
external device.
Full-rate: 1
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IP for Stratix 10 devices.
asserted and strobe_in is stable.
group_<n>_rdata_ Output Quarter-rate: 4 This signal determines which data are

valid Half-rate: 2 valid when reading from Read FIFO.
Full-rate: 1 Delayed by READ_LATENCY with
clock cycles.
Synchronous to the core_clk
output from the PHY Lite for Parallel
Interfaces Intel FPGA IP for Stratix
10 devices.
group_<n>_data_i Input/ 1 to 48 if data configuration is Single Input and output data from/to
n/ Bidirectional Ended external device. Synchronous to the
group_<n>_data_i group_<n>_strobe_in or
o group_<n>_strobe_io input. The
first data_in must be associated with
positive edge of strobe_in/
strobe_io.
data_in ports are used. If the pin
type is set to bidirectional, the
data_io ports are used.
Note: PHY Lite for Parallel Interfaces
Intel FPGA IP for Stratix 10
devices does not support
differential data pins.
group_<n>_strobe Input/ 1 Input and output strobe from/to

_in/ Bidirectional external device. If the pin type is set
group_<n>_strobe to Input, the
_io group_<n>_strobe_in signal is
Bidirection, the
used.
group_<n>_strobe Input/ 1 Negative strobe from/to external

_in_n Bidirectional device. This is used if the Strobe
group_<n>_strobe Configuration parameter is set to
_io_n Differential or Complementary. If
strobe_in_n signal is used. If the
strobe_io_n signal is used.
5.3.2.4. Avalon Configuration Bus Interface Signals
The PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices exposes the
Avalon memory-mapped interface slave and Avalon memory-mapped interface master
interfaces when you perform dynamic reconfiguration. Connect the Avalon memory-
mapped interface slave to either a master in the core or the master interface of either
an PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices or the External
Memory Interface IP to be placed in the same column. You can only connect the
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master interface to the slave interface of a PHY Lite for Parallel Interfaces Intel FPGA
IP for Stratix 10 devices or External Memory Interface IP to be placed in the same
column.
Table 101. Avalon Memory-Mapped Interface Master Interface Signals

avl_clk Input 1 Avalon interface clock.

Maximum Avalon memory-mapped interface clock for PHY
Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices
is 167 MHz.
avl_reset_n Input 1 Reset input synchronous to avl_clk.
avl_read Input 1 Read request from io_aux. This signal is synchronous to the
avl_clk input.
avl_write Input 1 Write request from io_aux. This signal is synchronous to the
avl_clk input.
avl_byteenable Input 4 Controls which bytes should be written on avl_writedata.
avl_address Input 31 Address from io_aux. This signal is synchronous to the

avl_clk input.
avl_readdata Output 32 Read data to io_aux. This signal is synchronous to the

avl_clk input.
avl_writedata Input 32 Write data from io_aux. This signal is synchronous to the
avl_clk input.
avl_readdata_valid Output 1 Indicates that read data has returned.
avl_waitrequest Output 1 Stalls upstream logic when it is asserted.
Table 102. Avalon Memory-Mapped Interface Slave Interface Signals

avl_out_clk Output 1 Connect this signal to the input Avalon interface of another
PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10
devices or the External Memory Interfaces IP.
avl_out_reset_n Output 1 Connect this signal to the input Avalon interface of another
PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10
devices or the External Memory Interfaces IP.
avl_out_read Output 1 Indicates read transaction.
avl_out_write Output 1 Indicates write transaction.
avl_out_byteenable Output 4 Controls which bytes should be written on

avl_out_writedata.
avl_out_writedata Output 32 The data packet associated with the write transaction.
avl_out_address Output 31 Avalon address (in byte granularity). Value is identical to

avl_address but with zeroes padded on the LSBs.
avl_out_readdata Input 32 The data packet associated with

avl_out_readdata_valid.
avl_out_readdata_val Input 1 Indicates that read data has returned.

id
avl_out_waitrequest Input 1 Stalls upstream logic when it is asserted.
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5.3.2.5. Termination Signals
Table 103. Termination Signals

The termination signals are signals that are available when you enable the Expose termination ports
parameter. The <n> in the signal names below represents the group number in the IP.
group_<n>_serieste Input 16 Connect this signal to the series

rminationcontrol termination control signal of the OCT
Intel FPGA IP to receive series
termination code to calibrate Rs.
Connect this signal to the parallel

group_<n>_parallel termination control signal of the OCT
Input 16
terminationcontrol Intel FPGA IP to receive parallel
termination code to calibrate Rt.
5.4. I/O Standards

The PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices allows you to
set I/O standards on the pins associated with the generated configuration. The I/O
standard controls the available strobe configurations and OCT settings for all groups.
However, even though most I/O standards support differential or complementary I/Os,
such as SSTL, HSTL, and POD, the PHY Lite for Parallel Interfaces Intel FPGA IP for
Stratix 10 can only be configured to use single-ended I/O data pins.
Table 104. I/O Standards and Termination Values

I/O Standard Valid Input Valid Output RZQ Differential/Complementary I/O
Terminations (Ω) Terminations (Ω) Support
(Ω) Important:
PHY Lite for Parallel Interfaces Intel
FPGA IP for Stratix 10 devices does
not support differential data pins.
SSTL-12 60, 120 40, 60,240 240 Yes
SSTL-125 40, 60, 120 34, 40 240 Yes
SSTL-135 40, 60, 120 34, 40 240 Yes
SSTL-15 40, 60, 120 34, 40 240 Yes
SSTL-15 Class I 50 50 100 Yes
SSTL-15 Class II 50 25 100 Yes
SSTL-18 Class I 50 50 100 Yes
SSTL-18 Class II 50 25 100 Yes
1.2-V HSTL Class I 50 50 100 Yes
1.2-V HSTL Class II 50 25 100 Yes

continued...
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Terminations (Ω) Terminations (Ω) Support
(Ω) Important:
PHY Lite for Parallel Interfaces Intel
FPGA IP for Stratix 10 devices does
not support differential data pins.
1.2-V POD 34, 40, 48, 60, 80, 34, 40, 48, 240 Yes
120, 240 60
1.2-V — — — No
1.5-V — — — No
1.8-V — — — No
Related Information
On-Chip I/O Termination in Stratix 10 Devices

The POD I/O standard allows configurable VREF. By default, the externally provided
VREF is used and using an internal VREF requires the following .qsf assignments:
set_instance_assignment -name VREF_MODE <mode> -to <pin_name>
Note: The VREF settings are at the lane level, so all pins using a lane must have the same
VREF settings (including GPIOs).

CALIBRATED Use internal VREF generated using VREF codes from the Avalon memory-mapped interface
reconfiguration bus.
VCCIO_45 Use internal VREF generated using static VREF code. VREF is 45% of VCCIO,
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Figure 129. VREF
Input Buffer
VCCIO
Rt
+
Vref -
R
VCCIO
Internal VREF
+
-
Resistor
Ladder R

Note: You must select the VREF range for your design using analog simulation.
5.4.1.1. Calibrated VREF Settings
Table 106. Calibrated VREF Settings

This table lists the calibrated VREF settings that you can set over the Avalon memory-mapped interface
calibration bus. This table is applicable to all Intel FPGA devices.
avl_writedata[5:0] % of VCCIO
000000 60.00%
000001 60.64%
000010 61.28%
000011 61.92%
000100 62.56%
000101 63.20%
000110 63.84%
000111 64.48%
001000 65.12%
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001001 65.76%
001010 66.40%
001011 67.04%
001100 67.68%
001101 68.32%
001110 68.96%
001111 69.60%
010000 70.24%
010001 70.88%
010010 71.52%
010011 72.16%
010100 72.80%
010101 73.44%
010110 74.08%
010111 74.72%
011000 75.36%
011001 76.00%
011010 76.64%
011011 77.28%
011100 77.92%
011101 78.56%
011110 79.20%
011111 79.84%
100000 80.48%
100001 81.12%
100010 81.76%
100011 82.40%
100100 83.04%
100101 83.68%
100110 84.32%
100111 84.96%
101000 85.60%
101001 86.24%
101010 86.88%
101011 87.52%
101100 88.16%
continued...
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101101 88.80%
101110 89.44%
101111 90.08%
110000 90.72%
110001 91.36%
110010 92.00%
110011 -> 111111 Reserved
Related Information
Dynamic Reconfiguration on page 141

PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices provides valid OCT
settings for each group (refer to the I/O Standards topic). These settings are written
to the .qip of the instance during generation. If you select an I/O standard that
supports OCT in the General tab, you can use the OCT blocks provided in Stratix 10
devices.

Related Information
• KDB link: How can the PHYLite IP RZQ pin location be assigned?
associate the terminated pins of the PHY Lite for Parallel Interfaces Intel FPGA IP for
Stratix 10 devices instance with an RZQ pin at the system level manually.
Use the following steps to set RZQ pin locations for the PHY Lite for Parallel Interfaces
Intel FPGA IP for Stratix 10 devices:
1. In the Group <x> OCT Settings tab, disable Use Default OCT Values and
Expose termination ports.
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Figure 130. Group <x> OCT Settings Parameter Settings


RZQ pin:

<altera_phylite_strobe_pin>

<altera_phylite_data_pin[*]>

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5.4.2.2. Manual Insertion of OCT Block
You may also instantiate the OCT Intel FPGA IP separately in your project and connect
the termination ports to the PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10
devices.
1. Expose the PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices
termination ports by disable Use Default OCT Values.
2. Select the available OCT values in the Input OCT Value parameter. This displays
the Expose termination ports parameter.
Note: For supported input and output OCT values, refer to the I/O Standards
topic.
3. Select Expose termination ports to expose the termination ports in the IP.
4. Connect the termination ports to a OCT Intel FPGA IP either in power-up or user
mode.
Figure 131. RTL View of PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10
Devices Interfacing with OCT Intel FPGA IP in User Mode
group_0_data_in[3:0] phylite_test_ip
group_0_data_in[3:0]
oct_0_parallel_termination_control[15:0] group_0_parallelterminationcontrol[15:0]
calibration_request oct_test_ip
cal_request 4’h0group_0_rdata_en[3:0]
clock
refclk oct_0_series_termination_control[15:0] group_0_seriesterminationcontrol[15:0]
reset group_1_data_out[3:0]
rstn group_0_strobe_in
rzqin group_1_strobe_out
octrzqin0 32’h0group_1_data_from_core[31:0]
u1
16’h0group_1_oe_from_core[15:0] interface_locked
group_0_strobe_in
group_1_parallelterminationcontrol[15:0]
group_1_seriesterminationcontrol[15:0]
4’h0group_1_strobe_out_en[3:0]
ref_clk
reset_n
u0
Related Information
I/O Standards on page 173

Follow these guidelines to place the PHY Lite for Parallel Interfaces Intel FPGA IP for
Stratix 10 devices group pins.
1. All groups in a PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices
must be placed across a contiguous set of lanes. The number of lanes depends on
the number of pins used by the group.
2. Two groups, from either the same or different PHY Lite for Parallel Interfaces Intel
FPGA IP for Stratix 10 devices, cannot share an I/O lane.
3. For PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices instance
that spans more than one I/O bank, all groups in the interface must be placed
across a contiguous set of banks within an I/O column. The number of I/O banks
required depends on the memory interface width.
4. Pins that are not used in an I/O bank are available as general purpose I/O (GPIO)
pins.
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5. To constrain groups from separate PHY Lite for Parallel Interfaces Intel FPGA IP for
Stratix 10 devices instances into the same I/O bank, the instances must share the
same reference clock and reset sources, the same external memory frequencies,
and the same voltage settings.
6. A reference clock network can only span across maximum of 6 I/O banks.
7. You cannot share the OCT termination block across the I/O column. You can
associate the terminated pins of the PHY Lite for Parallel Interfaces Intel FPGA IP
for Stratix 10 devices instance with an RZQ pin through RZQ_GROUP assignment.
Table 107. Group Pin Placement

PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices does not support DQS for X4.
Number of Pins in Group Valid DQS Group in a Bank Valid Index in a Bank
1-12 DQS for X8/X9 {0-11}/{12-23}/{24-35}/{36-47}
13-24 DQS for X16/X18 {0-23}/{24-47}
25-48 DQS for X32/X36 {0-47}
Related Information
Pin-Out Files for Intel FPGA Devices
For pin index and I/O bank references, refer to the specific device pin-out file.

Interfaces Intel FPGA IP from a dedicated clock pin. Use the clock pin in one of the I/O
banks used by the PHY Lite for Parallel Interfaces Intel FPGA IP. You must use
contiguous I/O banks to implement multiple interfaces (consisting of a combination of
External Memory Interface and PHY Lite for Parallel Interfaces Intel FPGA IPs). If you
use the same reference clock for these interfaces, place the reference clock in any of
the contiguous I/O banks.
Note: For Quartus Prime software version 18.1 or later, you may see error warning message
for design with encrypted IOPLL IP. The auto-generated .sdc files of the IOPLL IP are
not supported if you use encryption. You must manually create the .sdc file using
create_clock and create_generated_clock to replace the auto-generated .sdc
file in the design for refclk and output clocks.
Related Information
Stratix 10 Clocking and PLL User Guide: IP Core Constraints
5.5.3. Reset
You can source the reset to the PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix
10 devices from an external pin or from the core. If you source the reset from an
external pin, you must configure the I/O standard of the reset signal in the .qsf file
with the following command:
set_location_asignment <PIN_NUMBER> -to <signal_name>
Related Information
• Functional Description on page 132
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• KDB Link: Error(14566): The Fitter cannot place 1 periphery component(s) due to
conflicts with existing constraints (1 PHYLITE_GROUP(s)).
5.5.4. Constraining Multiple PHY Lite for Parallel Interfaces Intel FPGA IP
to One I/O Bank
You can instantiate multiple PHY Lite for Parallel Interfaces Intel FPGA IPs within an
I/O column. To constrain groups from separate PHY Lite for Parallel Interfaces Intel
FPGA IP instances into the same I/O bank, the instances must share the same
reference clock and reset sources, the same external memory frequencies and the
same voltage settings.

Dynamic reconfiguration reconfigures the input and output delays in the PHY Lite for
Parallel Interfaces Intel FPGA IP for Stratix 10 devices core.
You can perform real-time configuration on the delay of DQS/strobe or DQ/data

signals. This feature maximizes the data valid window, allowing the design to achieve
timing closure at high frequency. You can turn on Use dynamic reconfiguration in
the parameter editor of the PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10
devices core in the Quartus Prime Pro Edition software.
The reconfiguration is performed via the Avalon memory-mapped interface. Multiple IP

cores requiring Avalon core access require daisy chain connectivity.
Related Information
• Daisy Chain on page 142
Reconfiguration for Stratix 10 Devices
5.5.6. Timing
The Quartus Prime software generates the required timing constraints to analyze the
timing of the PHY Lite for Parallel Interfaces Intel FPGA IP on the all Intel FPGA
devices.
5.5.6.1. Timing Components
Table 108. Timing Components

Circuit Category Timing Paths Source Destination Description
Source synchronous Read Path Memory DQ Capture Source synchronous timing paths—paths where
and optionally Device Register clock and data signals are passed from the
calibrated (13) transmitting devices to the receiving devices.
Optionally calibrated paths—paths with delay
Source synchronous Write Path FPGA Memory elements that are dynamically reconfigurable to
and optionally DQ/DQS Device achieve timing closure, especially at higher
calibrated (13) frequency, and to maximize the timing margins.
You can calibrate these paths by implementing
an algorithm and turning on the optional
dynamic reconfiguration feature. An example of
continued...
(13) Can be optionally calibrated by using dynamic reconfiguration.
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the calibrated path is the FPGA to memory

device write path, in which you can dynamically
reconfigure the delay elements to, for instance,
compensate the skew due to process voltage
temperature variation.
Internal FPGA Core to PHY Core Write FIFO The internal FPGA paths are paths in the FPGA
Lite for Registers fabric. The Timing Analyzer reports the
Parallel corresponding timing margins.
Interfaces
Intel FPGA IP
Path
Internal FPGA PHY Lite for Read FIFO Core Registers

Parallel
Interfaces
Intel FPGA IP
to Core
5.5.6.2. Timing Constraints and Files
To successfully constrain the timing for PHY Lite for Parallel Interfaces Intel FPGA IP,
the IP generates a set of timing files. You can locate these timing files in the
<variation_name> directory:
• <variation_name> .sdc
• <variation_name> _ip_parameters.tcl
• <variation_name> _pin_map.tcl
• <variation_name>_parameters.tcl
• <variation_name>_report_timing.tcl
• <variation_name>_report_timing_core.tcl
5.5.6.2.1. <variation_name>.sdc
You can find the location of the <variation_name>.sdc file in the .qip or .qsys,
which is generated during the IP generation. The <variation_name> .sdc allows the
Fitter to optimize timing margins with timing driven compilation and allows the Timing
Analyzer to analyze the timing of your design.
The IP uses <variation_name>.sdc for the following operations:

• Creating clocks on PLL inputs
• Creating generated clocks
• Calling derive_clock_uncertainty
• Creating set_output_delay and set_input_delay constraints to analyze the
timing of the read and write paths
5.5.6.2.2. <variation_name>_parameter.tcl
The <variation_name>_parameters.tcl file is a script that lists the following PHY

Lite for Parallel Interfaces Intel FPGA IP parameters used in the .sdc file and report
timing scripts:
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• Jitter
• Simultaneous switching noise
• Calibration uncertainties
5.5.6.2.3. <variation_name>_ip_parameters.tcl
The <variation_name>_ip_parameters.tcl file lists the PHY Lite for Parallel

Interfaces Intel FPGA IP parameters and is read by the <variation_name>.sdc.
5.5.6.2.4. <variation_name>_pin_map.tcl
The <variation_name>_pin_map.tcl is a TCL library of functions and procedures

that <variation_name>.sdc uses.
5.5.6.2.5. <variation_name>_report_timing.tcl
The <variation_name>_report_timing.tcl file is a script that contains timing

analysis flow and reports the timing slack for your variation. This script runs
automatically during calibration (during static timing analysis) by sourcing the
following files:
• <variation_name>_ip_parameters.tcl
• <variation_name>_pin_map.tcl
You can also run <variation_name>_report_timing.tcl with the Report DDR
function in the Timing Analyzer. This script runs for every instance of the same
variation.
Note: You can only use the Report DDR function if you enable the dynamic reconfiguration
feature.
5.5.6.2.6. <variation_name>_report_timing_core.tcl
The <variation_name>_report_timing_core.tcl file is a script that

<variation_name>_report_timing.tcl uses to calculate the timing slack for
your variation. <variation_name>_report_timing_core.tcl runs automatically
during compilation.
5.5.6.3. Timing Analysis
Table 109. Timing Analysis

This table lists the timing analysis performed in the I/O and FPGA for the PHY Lite for Parallel Interfaces Intel
FPGA IP.
Location Description
I/O The PHY Lite for Parallel Interfaces Intel FPGA IP generation creates the appropriate generated clock
settings for the read strobe on the read path and the write strobe of the write path, according to their
strobe type (singled-ended, complementary, or differential) and their interface type (SDR or DDR) in the
following format:
continued...
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• Clock name for read strobe—<pin_name>_IN.

• Clock name for the write path—<pin_name> for positive strobe.
• Clock name for the write path—<pin_name>_neg for negative strobe.
The set_false_path, set_input_delay and set_output_delay constraints are also generated to
ensure proper timing analysis of the PHY Lite for Parallel Interfaces Intel FPGA IP.
FPGA The PHY Lite for Parallel Interfaces Intel FPGA IP generation creates the clock settings for the user core
clock and the periphery clock in the following formats:
• user core clock—<variation_name>_usr_clk
• periphery clock— <variation_name>_phy_clk*
The user core clock is for user core logic and the periphery clock is the clock for the PHY Lite for Parallel
Interfaces Intel FPGA IP periphery hardware. With these clock settings, the Timing Analyzer analyzes the
timing of this IP interface transfer and within core transfer correctly.
5.5.6.4. Timing Closure Guidelines
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
You can dynamically reconfigure the delay elements in the I/O to optimize process,
voltage, temperature variations by implementing a calibration algorithm that modifies
the input and output delays.
Related Information
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
The Input Strobe Setup Delay Constraint and Input Strobe Hold Delay
Constraint parameters ensure that an input to the FPGA from the an external device
meets the internal FPGA setup and hold time requirements. The value of these
constraints are calculated from various timing parameters such as setup and hold
timing of the external device, board trace delay and clock skew.
The following figure shows the considerations required to determine the Input Strobe
Setup Delay Constraint and Input Strobe Hold Delay Constraint values. The
external device sends data and clock to the FPGA through interconnect on the board.
The FPGA uses the clock signal from the external device to latch input data to the
FPGA. The maximum and minimum values of the output clock TCO are values available
in the external device data sheet.
Figure 132. Input Strobe Setup and Hold Delay Constraints Considerations
External FPGA
Device
Data Data input to FPGA
data_trace (max/min) PHY Lite
for Parallel
tCO
Interface
Input clock Input clock to FPGA Intel FPGA IP
Clock
PLL
clock_trace (max/min)
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The following is the derivation for Input Strobe Setup Delay Constraint and Input
Strobe Hold Delay Constraint:
Input strobe setup delay constraint = Maximum board skew + maximum TCO
Input strobe hold delay constraint = Minimum board skew + minimum TCO
where maximum board skew = maximum data trace - minimum clock trace
minimum board skew = minimum data trace - maximum clock trace
maximum TCO = DQS to DQ skew (tDQSQ)
minimum TCO = Data hold skew (tQHS)
Figure 133. Input Data Cycle Timing Diagram

t CH
t CL
t QH tQHS
t DQSQ
Data valid window
DQ_skew_min DQ_skew_max DQ_skew_min DQ_skew_max
t CL = Clock cycle low

t CH = Clock cycle high
t DQSQ = DQS-DQ skew
t QH = DQ-DQS hold
tQHS = Data hold skew
The following is an example of Input Strobe Setup Delay Constraint and Input
Strobe Hold Delay Constraint calculations with:
• Input clock frequency = 100 MHz
• Board skew estimation = ± 0.03 ns
• Maximum TCO = 0.6 ns
• Minimum TCO = -0.6 ns
Input Strobe Setup Delay Constraint = 0.03 + 0.6= 0.63 ns
Input Strobe Hold Delay Constraint = -0.03 + (-0.6) = -0.63 ns
Insert these values into the Input Strobe Setup Delay Constraint and Input
Strobe Hold Delay Constraint parameters and run timing analysis with the Timing
Analyzer tool. The following is an example of delay result from the Timing Analyzer
tool.
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Figure 134. Example of Input Strobe Delay Value from Timing Analyzer
iEXT=Input Strobe Delay Constraint + (0.5*Inter Symbol Interference of Read Channel)
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
The Output Strobe Setup Delay Constraint and Output Strobe Hold Delay
Constraint ensure that the data output from the FPGA to the external device meets
the setup and hold requirements of the external device. The value of these constraints
are calculated from various timing parameters such as setup and hold timing of the
external device, board trace delay and clock skew.
The following figure shows the considerations required to determine the Output
Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint
values. These constraints are depending on the clock and data traces, and setup and
hold requirements of the external device. With system-centric delays, you can obtain
the setup and hold requirements, clock delay, and data trace delay values for the
external device through the device data sheet.
Figure 135. Output Strobe Setup and Hold Delay Constraints Considerations
FPGA External Device
PHY Lite for Parallel Data output to external device

Interface Intel FPGA IP Data Data
data_trace (max/min) (tSU ,t H)
Input clock PLL Output clock to external device

Clock Clock
The following is the derivation for Output Strobe Setup Delay Constraint and
Output Strobe Hold Delay Constraint:
Output strobe setup delay constraint = Maximum board skew + maximum tSU
Output strobe hold delay constraint = Minimum board skew + minimum tH
maximum tSU = clock setup time
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minimum tH = clock hold time
Figure 136. DDR Output Cycle Timing Diagram
t SUdq
DQ bit time
t SUdq
SU margin Hold margin
The following is an example of Output Strobe Setup Delay Constraint and Output
• Maximum tSU = 0.75 ns
• Minimum tH = 0.75 ns
Output Strobe Setup Delay Constraint = 0.03 + 0.75= 0.78 ns
Output Strobe Hold Delay Constraint = -0.03 - 0.75 = -0.78 ns
Insert these values into the Output Strobe Setup Delay Constraint and Output
tool.
Figure 137. Example of Output Strobe Delay Value from Timing Analyzer
oEXT= Output Strobe Setup delay constraint + (0.5 * Inter Symbol Interference of the Write Channel)
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5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
If the input data is not edge-aligned, use the following equation to calculate the new
Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint
values:
New Input Strobe Setup Delay Constraint Value = Clock to data skew - Input
Strobe Phase Shift (nanosecond)
New Input Strobe Hold Delay Constraint Value = Clock to data skew + Input
For example, if the memory speed is 800 MHz and the clock to data skew value is 0.1
with input data phase shift of 90°:
New Input Strobe Setup Delay Constraint value = 0.1-1.25*(90/360) =

-0.2125ns.
New Input Strobe Hold Delay Constraint value = 0.1 + 1.25*(90/360) = 0.4125ns
Important: Ensure that you make the changes in the Input Strobe Setup Delay Constraint and
Input Strobe Hold Delay Constraint parameters.
5.5.6.4.5. I/O Timing Violation
It can be difficult to achieve timing closure for I/O paths at high frequency. Use the
dynamic reconfiguration feature to calibrate the I/O path.
Related Information
5.5.6.4.6. Internal FPGA Path Timing Violation
If timing violations are reported at the internal FPGA paths (such as

<instance_name>_usr_clk or <instance_name>_phy_clk_*), consider the
following guidelines:
If setup time violation is reported, lower the clock rate of the user logic from full-rate
to half-rate, or from half-rate to quarter-rate. This reduces the frequency requirement
of the IP core-to-core data transfer.
If hold time violation is observed, you may increase hold uncertainty value to equal or
higher than the violation amount in the .sdc file. This will provide a more stringent
constraint during design fitting. Following is an example to increase the hold
uncertainty.
If {$::quartus(nameofexecutable) != “quartus_sta”}{
set_clock_uncertainty -from [<instance_name>_phy_clk_*] -to

[<instance_name>_phy_clk_*] -hold 0.3 -add
set_clock_uncertainty -from [<instance_name>_usr_clk] -to

[<instance_name>_usr_clk] -hold 0.3 -add
However, increasing the hold uncertainty value may cause setup timing violation at
slow corner.
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5.6. Design Example

The PHY Lite for Parallel Interfaces Intel FPGA IP is able to generate a design example
that matches the same configuration chosen for the IP. The design example is a simple
design that does not target any specific application; however you can use the design
example as a reference on how to instantiate the IP and what behavior to expect in a
simulation.
not edit the files.

reside.
Intel FPGA IP:
• Variant without dynamic reconfiguration design example
• Variant with dynamic reconfiguration design example
Design Example Variant Design Files Description
Dynamic Reconfiguration OFF ed_synth.qsys (synthesis Consists of configurablePHY Lite for

only) Parallel Interfaces Intel FPGA IP
instance.
ed_sim.qsys (simulation Consists of sim_ctrl, agent, addr/cmd

only) and PHY Lite for Parallel Interfaces
Intel FPGA IP instances.
Perform read and write transaction
verification.
ON ed_sim.qsys (simulation Consists of sim_ctrl, agent, addr/

only) cmd, cfg_ctrl, avl_ctrl and PHY Lite
for Parallel Interfaces Intel FPGA IP
instances.
This design example demonstrates
dynamic reconfiguration and uses
FSM to perform calibration.
When the Enable dynamic reconfiguration option is not selected, Quartus Prime
software generates a design example of PHY Lite for Parallel Interfaces Intel FPGA IP
without a dynamic reconfiguration module.
This design example consists of simulation and synthesis design files.
5.6.1.1.1. Generating the Hardware Design Example
The make_qii_design.tcl generates a synthesizable hardware design example

along with a Quartus project, ready for compilation.
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generation:

can open and compile this project with the Quartus Prime software.
The make_sim_design.tcl generates a simulation design example along with tool-

specific scripts to compile and elaborate the necessary files.
simulation tools. Each subdirectory contains the specific scripts to run simulation with
connectivity for your IP configuration. Functionally, the simulation iterates over each
group in your configured IP and performs basic reads/writes to an associated agent
(one per group) in the testbench. A simple one group PHY Lite for Parallel Interfaces
Intel FPGA IP instantiation in the testbench is used for basic address and command
outputs to the agent. A side bus between the sim_ctrl and the agents is used to
check that the reads and writes are valid.
sim_ctrl Side read/write command Agent (one per group

Side read/write data in DUT)
DRAM clock
Core clock Read/Write
PHY Lite DRAM clock
command ADDR/CMD Write command
Read command Latency Delays
Core clock DRAM clock Agent select
Core clock
PHY Lite DUT
Read/Write
enable data
data strobe DRAM clock

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Example Design, Quartus Prime software generates the dynamic reconfiguration with
configuration control module design examples:
5.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine
This design example is a simulation design example that is capable to perform

dynamic calibration for PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10
devices.
Features
• Perform dynamic reconfiguration using Avalon controller

• Read and write transactions monitoring
• Delay values monitoring
Software Requirements
• Quartus Prime software
• Active-HDL, ModelSim* - Intel FPGA Edition, or VCS Simulator
Functional Description
This design example introduces the cfg_ctrl and avl_ctrl blocks, which work with
the sim_ctrl module to demonstrate the basic functionality of the PHY Lite for
Parallel Interfaces Intel FPGA IP for Stratix 10 devices Avalon memory-mapped
interface based reconfiguration. The agent is also modified to insert delays on the data
and clocks, which the new modules will compensate for.
Note: The cfg_ctrl module performs a simplistic reconfiguration of the interface that stops
at the first working delay values. The design example only support simulation. A
robust calibration algorithm should sweep over the entire valid range of delays to
choose the correct value for the application.
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Figure 139. Dynamic Reconfiguration Using Finite State Machine Design Example
This figure shows a high-level view of the simulation design example with one group.

in DUT)
Side read/write data
ref_clk_gen ref_clk reset_gen
DRAM clock PHY Lite ADDR/CMD reset_n

ref_clk DRAM clock
Core clock
Read/Write
Write command
command Read command Latency Delays
ref_clk
Core clock Driver PHY Lite DUT reset_n
Core clock
Lock Read/Write
enable Data DRAM clock
Data
strobe
Data Core clock DRAM clock
Strobe
Lock
Reconfiguration
Flow Control
Dynamic Reconfiguration Only
cfg_ctrl Avalon avl_ctrl Avalon Memory-mapped Bus

Memoy-mapped
Bus
Table 111. Design Components Description

ref_clk_gen Generates clock to reset_gen, PHY Lite for Parallel Interfaces Intel FPGA IP for
Stratix 10 devices ADDR/CMD (ref_clk), and PHY Lite for Parallel Interfaces Intel
FPGA IP for Stratix 10 devices (ref_clk) blocks.
reset_gen Generates reset to PHY Lite for Parallel Interfaces Intel FPGA IP ADDR/CMD and
PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 devices blocks.
sim_ctrl • Generates read/write commands to PHY Lite for Parallel Interfaces Intel FPGA
IP ADDR/CMD block.
• Generates side read/write commands and data to Agent block.
• Generates strobe and data to Driver block.
Driver Generates strobe and data for each group and to PHY Lite for Parallel Interfaces
Intel FPGA IP for Stratix 10 devices block.
PHY Lite for Parallel Interfaces Intel Passing read/write commands and command clock from sim_ctrl to Agent.
FPGA IP ADDR/CMD
Agent FIFO to store data from PHY Lite for Parallel Interfaces Intel FPGA IP DUT and
side read/write data from sim_ctrl block.
cfg_ctrl This is configuration control block which performs read and write delay calibration
before test begin.
The calibration results is passed to the PHY Lite for Parallel Interfaces Intel FPGA
IP for Stratix 10 devices through Avalon Controller.
Contains 4 FSMs:
1. Main FSM – cfg_ctrl state
2. Write Strobe FSM – Calibration state for Output Strobe
3. Read Strobe FSM – Calibration state for Input Strobe
4. Read Enable FSM – Calibration state for Strobe Enable and Input Data
avl_ctrl The Avalon controller is used to perform address translation to store delay
settings from the calibration done by cfg_ctrl block.
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Figure 140. Design Example Functional Flow

Start
Reset cfg_ctrl module
Dynamically reconfigure
data group's settings
Function name: reconfigure_grp
Pin Type?
Output Input
Bidirectional
Dynamically reconfigure write strobe setting Dynamically reconfigure write strobe setting
Function name: reconfigure_grp_write Function name: reconfigure_grp_write
a) Read from Pin Output Delay CSR register a) Read from Pin Output Delay CSR register
b) Write to DUT and read back b) Write to DUT and read back
c) If fail, update Pin Output Delay c) If fail, update Pin Output Delay Avalon register
Avalon register d) Repeat step b) and c) until pass
d) Repeat step b) and c) until pass e) Done
e) Done
Write data to DUT

Write data to DUT and read back to verify data is correct
and read back to verify data is correct
Dynamically reconfigure read strobe setting

Simulation ends
Function name: reconfigure_grp_read
a) Read from Strobe PVT Compensated Input Delay
CSR register
b) Write to Agent and read back
c) If fail, update Strobe PVT Compensated Input Delay
Avalon register
d) Repeat step b) and c) until pass
e) Done
Dynamically reconfigure read enable and

input data settings
Function name: reconfigure_grp_read_en_and_data
a) Read from Strobe Enable Phase CSR register
c) If data[0] is mismatched,
update Strobe Enable Phase Avalon register
d) Repeat step b) and c) until data[0] is matched
e) Get number of data pin
f) Write to Agent and read back
g) If fail, update Pin PVT Compensated Input Delay
Avalon register
h) Repeat f) and g) until pass
i) Done
Write data to Agent

Simulation ends
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Generating the Dynamic Reconfiguration with Configuration Control Module Design

Example
1. In Quartus Prime software, instantiate PHY Lite for Parallel Interfaces Intel FPGA
IP core.
2. Customize parameter settings per your requirement and turn on the Use
dynamic reconfiguration option.
3. Click Generate Example Design. Specify a directory name to generate the
design example.
4. To generate Verilog or mixed-language simulation files, go to the design example
directory and run the following script in Nios® II Command Shell.
5. To generate VHDL simulation files, go to the design example directory and run the
following script in Nios II Command Shell.
Running the Dynamic Reconfiguration with Configuration Control Design Example

1. Change the working directory to <Example Design>\sim\ed_sim\sim
\<Simulator>.
2. Run the simulation script for the simulator of your choice. Refer to the table below.
Modelsim <Example Design>\sim\ed_sim a. do msim_setup.tcl

\sim\mentor b. ld_debug
c. Add desired signals into the
waveform window.
d. run -all
VCS <Example Design>\sim\ed_sim a. sh vcs_setup.sh

\sim\synopsys\vcs
VCSMX <Example Design>\sim\ed_sim a. sh vcsmx_setup.sh

\sim\synopsys\vcsmx
Aldec Example Design\sim\ed_sim\sim a. do rivierapro_setup.tcl

\aldec b. ld_debug
waveform window.
d. run -all
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Figure 141. Sample Simulation Output
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Send Feedback
6. PHY Lite for Parallel Interfaces Intel FPGA IP for Arria

10 and Cyclone 10 GX Devices

features.
changes.
Table 112. PHY Lite for Parallel Interfaces Intel FPGA IP for Arria 10 Devices Release
Information
Item Description
IP Version 19.5.0
Table 113. PHY Lite for Parallel Interfaces Intel FPGA IP for Cyclone 10 GX Devices
Release Information
Item Description
IP Version 19.4.0
Related Information
6. PHY Lite for Parallel Interfaces Intel FPGA IP for Arria 10 and Cyclone 10 GX Devices
683716 | 2024.04.01

The PHY Lite for Parallel Interfaces Intel FPGA IP utilizes the I/O subsystem in the
Arria 10 and Cyclone 10 GX devices. The I/O subsystem is located in the I/O columns
of each Intel FPGA devices. For Arria 10 and Cyclone 10 GX devices, each column
consists of I/O banks and I/O aux. The number of I/O banks varies according to
device packages. Each bank is a group of 48 I/O pins, organized into four I/O lanes
with 12 pins for each lane. Each I/O lane contains the DDR-PHY input and output path
logic for 12 I/Os as well as a DQS logic block. All four lanes in a bank can be combined
to form a single data/strobe group or up to four groups in the same interface. Under
certain conditions, two groups from different interfaces can also be supported in the
same bank.
Figure 142. Arria 10 I/O Bank Structure
LVDS I/O Buffer Pair SERDES & DPA

Individual LVDS I/O Buffer Pair SERDES & DPA
I/O Banks I/O Lane
2L 3H
2K 3G I/O Lane
2J 3F
I/O Center
I/O DLL I/O CLK
2I 3E OCT VR
Bank
Transceiver Block
Transceiver Block
I/O PLL Hard Memory Controller Control
2H 3D and
PHY Sequencer

2G 3C
I/O Lane
2F 3B
2A 3A LVDS I/O Buffer Pair SERDES & DPA

I/O Lane
Transceiver I/O I/O LVDS I/O Buffer Pair SERDES & DPA
Block Column Column LVDS I/O Buffer Pair SERDES & DPA
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Figure 143. Cyclone 10 GX I/O Bank Structure

I/O Lane
I/O Lane
I/O Center
2L I/O DLL I/O CLK
OCT VR
2K I/O PLL
Transceiver Block
Hard Memory Controller

and
PHY Sequencer
2J 3B
3A LVDS I/O Buffer Pair SERDES & DPA
3 V I/O
I/O Lane
2A LVDS I/O Buffer Pair SERDES & DPA
LVDS I/O LVDS I/O Buffer Pair SERDES & DPA
I/O Lane
Related Information
Provides more information about placement restrictions.
• I/O Resources in Arria 10 Devices
For more information about Arria 10 I/O bank architecture
• I/O Resources in Cyclone 10 GX Devices
For more information about Cyclone 10 GX I/O bank architecture
• Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank on page 247
6.2.1. Top Level Interfaces

The PHY Lite for Parallel Interfaces Intel FPGA IP consists of the following ports:
• Avalon memory-mapped interface configuration bus (available only when Dynamic
Reconfiguration feature is enabled)
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This figure shows the top-level diagram of the PHY Lite for Parallel Interfaces Intel FPGA IP interface.
Intel FPGA Device

Group
ref_clk PLL phy_clk

}
Legend
Related Information
For more information about the output path
For more information about the input path
For more information about core data, control, and I/O interfaces signals
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6.2.2. Clocks
The PHY Lite for Parallel Interfaces Intel FPGA IP uses a reference clock that is sourced
from a dedicated clock pin to the PLL inside the IP. This PLL provides four clock
domains for the output and input paths.
Table 114. PHY Lite for Parallel Interfaces Intel FPGA IP Clock Domains
Core clock This clock is generated internally by the IP and it is used for all transfers between the FPGA core
fabric and I/O banks. The clock phase alignment circuitry ensures that this clock is kept in phase
with the PHY clock for core-to-periphery and periphery-to-core transfers.
PHY clock This clock is used internally by the IP for PHY circuitry running at the same frequency as the
core clock.
VCO clock This clock is generated internally by the PLL. It is used by both the input and output paths to
generate PVT compensated delays in the interpolator.
Table 115. PHY Lite for Parallel Interfaces Intel FPGA IP for Arria 10 Devices Supported
Interface Frequency
Rate
Full 100 333 100 266 100 233
Half 100 667 100 533 100 466
Quarter 100 1200 100 1067 100 933
Table 116. PHY Lite for Parallel Interfaces Intel FPGA IP for Cyclone 10 GX Devices
Supported Interface Frequency
Core Clock Rate Speed Grade –5 (MHz) Speed Grade –6 (MHz)
Min Max Min Max
Full 100 266 100 233
Half 100 533 100 466
Quarter 100 1067 100 933
Related Information
KDB link: Can the Intel Arria 10 and Intel Cyclone 10 GX I/O PLL have a VCO
frequency below the minimum value shown in the device datasheets?
6.2.2.1. Clock Frequency Relationships
available in the PHY Lite for Parallel Interfaces Intel FPGA IP core.
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Related Information
KDB link: Can the Intel Arria 10 and Intel Cyclone 10 GX I/O PLL have a VCO
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6.2.3. Output Path

The output path consists of a FIFO and an interpolator.

Block Description
rate).
Interpolator Works with the FIFO block to generate the desired output delay. You can dynamically configure
the delay through the Avalon memory-mapped interface. For more information, refer to
Dynamic Reconfiguration section.

This figure shows the output path for the PHY Lite for Parallel Interfaces Intel FPGA IP.
strobe_out_in
strobe_out_en strobe_out/strobe_io
data_from_core Write FIFO data_io/data_out

oe_from_core
(1)
phy_clk
(1)
interpolator_clk
(1) (2)
Legend
Data path
(1)
(2)
The following figures show the waveform diagrams for the output path. The delays
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Indicates the latency from the time the IP issues a write command to the time the external memory
device receives the command.

to external memory device OUTPUT_STROBE_PHASE = 90

Indicates the latency from the time the IP issues a write command to the time the external memory Number of clock cycles set
device receives the command. in Write latency parameter
in Parameter Editor
OUTPUT_STROBE_PHASE = 90
Related Information
• Output Path Signals on page 234
For more information about output path signals
• How to Estimate Arria 10/Stratix 10 PHY Lite Input and Output Path Latency
How-to video on estimating PHY Lite Input and Output Path Latency in Arria 10
and Stratix 10 devices.
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6.2.3.1. Output Path Data Alignment
The data_from_core and oe_from_core signals are arranged in time slices that
are divided into the individual pins in the group. The first time slice is on the LSBs of
the buses, which matches the Intel FPGA PHY interface (AFI) bus ordering of the
External Memory Interfaces IP.
Example of time slices with individual pins correlation:
{time(n),time(n-1),time(n-2),... time(0)}
Where time0 = {pin(n),pin(n-1),pin(n-2),...pin0}
Figure 148. Example Output for Quarter Rate DDR
Related Information
• External Memory Interface Handbook Volume 3: Reference Material (AFI 3.0
Specification)
6.2.4. Input Path

The input path of the IP consists of a data path, a strobe path, and a read enable
path.

This table lists the information about these paths.
Path Description
• PVT compensated delay chain—Allows per-bit deskew. You can only control the PVT compensated
delay chain over Avalon memory-mapped interface. For more information, refer to Dynamic
Reconfiguration.
• group_data_in (input)—Input data from external device.
• group_data_io (bidirectional)—Input and output data from/to external device.
• group_data_to_core (output)—Output data to the core logic.
used.
continued...
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Path Description
• group_strobe_in, group_strobe_in_n (input)—Input strobe from external device.

group_strobe_in_n is used when strobe configuration is set to Differential.
• group_strobe_io, group_strobe_io_n (bidirectional)—Input and output strobe from/to external
device. strobe_io_n is used when strobe configuration is set to Differential.
• dqs_clean(output)—This internal signal is the refined version of group_strobe_in signal.
• dqs (input)—This internal signal is an input strobe to DDIO and Read FIFO in the data path, after
Path
generation time based on the read latency that you provide. Individual control is not necessary, but if
you are modifying these delays you can do so individually using dynamic reconfiguration.
(Write latency = 0). During dynamic reconfiguration, the DQS_EN FIFO and interpolator can be used
for fine grained control of the strobe enable signal. Both of these delays are controlled by the Read
latency parameter for the group.
• rdata_valid(output)—This signal determines which data are valid when reading from Read FIFO.
This signal is delayed by the Read latency value set in the parameter editor.
• group_rdata_en (input)—This signal represents the number of expected words to read from the
external device.
• dqs_enable_in (input)—This is an internal signal that provides dqs delay value to the
pstamble_reg module to process a refined dqs signal.
• dqs_enable_out (output)— This is an internal strobe with the delayed value specified by the
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This figure shows the input path of the IP.
To Intel FPGA core PHY Lite for Parallel Interfaces Intel FPGA IP Core To external interface
data_to_core data_in
Read FIFO DDIO Delay Chain data_in_n
6 phy_clk (1) 5 (PVT) data_io
5 data_io_n
strobe_in
strobe_in_n
(1) strobe_io
read_enable
(1) dqs strobe_io_n
(1) (3)
(PVT)
3
4
6
rdata_valid
dqs_enable_out (1)
1 2
rdata_en VFIFO
(2) (1)
DQS_EN FIFO
dqs_enable_in
(1)
phy_clk (1)
interpolator_clk
(1)
Legend:
Data path
Strobe path
(1)
(2)
Control signal
(3)
This module is uses the Capture Phase Shift parameter to generate the delay for the incoming strobe. n = sequence number.
n This represent read operation
sequence.


Sequence Number
device).
FIFO modules.
The following figures show the waveform diagrams for the input path. The delays
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Figure 150. Input Path ─ Read Latency 7

Intrinsic Delay Read Latency =7 PHY Lite for Parallel Interfaces Internal Delay
Measured from rdata_en assertion Number of clock cycles set through Latency between read data received to rdata_valid assertion.
to mem_rd assertion, sampling on the Read latency parameter
rising edge of mem_clk. in Parameter Editor
Debug signals are inside the lane wrapper.

Only available for waveform debugging.
CAPTURE_PHASE_SHIFT = 90
Related Information
• Input Path Signals on page 235
For more information about input path signals
• How to Estimate Arria 10/Stratix 10 PHY Lite Input and Output Path Latency
How-to video on estimating PHY Lite Input and Output Path Latency in Arria 10
and Stratix 10 devices.
6.2.4.1. Input Path Data Alignment
The bus ordering of data_to_core, rdata_en, and rdata_valid is identical to the

ordering of the output path. That is, the LSBs of the bus hold the first time slice of
data received.
The rdata_valid delay is always set by the IP to match the rdata_en alignment.
For example, quarter-rate delays are multiples of four external memory clock cycles
(one quarter rate clock cycle).
Figure 151. Example Input (Quarter Rate DDR) - Aligned

The waveform shows an example of aligned reads on the input path of the PHY Lite for Parallel Interfaces Intel
FPGA IP. At the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows data of 4'hf,
which represents all incoming data are aligned. The group_0_rdata_valid bus shows the data of 4'hf, which
represents all incoming data are valid. Therefore, the incoming read data on the group_0_data_to_core bus
matches the data seen on the group_0_data_io bus.
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Reading from an unaligned memory address is called unaligned reads. Unaligned

reads results in unaligned rdata_valid and data_to_core with data and valid
signals packed to the LSBs. This request causes the IP to do two or more read
operations.
Figure 152. Example Input (Quarter Rate DDR) - Unaligned

The waveform shows an example of unaligned reads on the input path of the PHY Lite for Parallel Interfaces
Intel FPGA IP.
The data from an unaligned read operation comes in two phases. At the first rising edge of the core_clk_out
signal, the group_0_rdata_en bus shows value of 4'he, which shows there are 6 bytes of incoming data from
group_0_data_io bus. On the subsequent clock cycle, the group_0_rdata_en bus shows value of 4'h1,
which shows there are 2 bytes of incoming data from group_0_data_io bus.
The valid data are transfer to the IP through the group_0_data_to_core bus. At first rising edge of the
core_clk_out signal, group_0_rdata_valid bus shows a value of 4'h7, which represents the first 6 bytes
of the data from the group_0_data_to_core bus are valid and the last 2 bytes are invalid. On the
subsequent clock cycle, group_0_rdata_valid bus shows the value of 4'h1, which shows the last 2 bytes of
the data from the group_0_data_to_core bus are valid.

Because of the asynchronous nature of the PHY, you must perform calibration to
achieve timing closure at a high frequency. At a high level, calibration involves
reconfiguring input and output delays in the PHY to align data and strobes. With the
PHY Lite for Parallel Interfaces Intel FPGA IP, you can perform the calibration by using
dynamic reconfiguration feature. The dynamic reconfiguration feature allows you to
modify these delays by writing to a set of control registers using an Avalon memory-
mapped interface.
Related Information
• Calibrated VREF Settings on page 241
• Timing Closure: Dynamic Reconfiguration on page 250
• KDB link: Why is the read data value incorrect for the DQS input delay when using
the Dynamic Reconfiguration mode in the Intel Arria 10 PHYLite IP?
6.2.5.1. RTL Connectivity
interface master and Avalon memory-mapped interface slave interfaces when you
enable the dynamic reconfiguration feature. If the generated IP is the only PHY Lite for
Parallel Interfaces Intel FPGA IP (with dynamic reconfiguration) or External Memory
Interface IP in the I/O column, connect only the Avalon memory-mapped interface
slave interface with a master in the core. Otherwise, connect Avalon memory-mapped
interface master and slave interfaces as described in the following section.
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6.2.5.1.1. Daisy Chain
The I/O column provides a single physical Avalon memory-mapped interface. All IP in
the I/O column that require Avalon memory-mapped interface access the same
physical Avalon memory-mapped interface. The system-level RTL for the column
reflects this resource limitation by using a daisy chain to connect all dynamically
reconfigurable IPs in an I/O column.
For PHY Lite for Parallel Interfaces Intel FPGA IP for Arria 10 devices and PHY Lite for
Parallel Interfaces Intel FPGA IP for Cyclone 10 GX devices, the Avalon memory-
mapped interface address is 28 bits where the top 4-bits are the ID of the interface to
be addressed in the daisy chain. These bits are only required for the daisy chain
arbitration in RTL simulation, so they are not synthesized during compilation. If only
one interface is addressed from the IP, it is sufficient to connect these bits as the
interface’s ID.
Figure 153. Logical RTL View to Physical Column Placement

This figure shows an example of a daisy chain consisting of the External Memory Interface and PHY Lite for
Parallel Interfaces Intel FPGA IP before and after placement.
Notice that all core controllers must go through the arbitration logic that you created
in the FPGA core logic to connect to an interface on the daisy chain. The end of the
daisy chain should have its master output interface tied to 0.
Note: The Fitter rearranges the Avalon address pins during compilation, therefore use the
postfit netlist for proper simulation of the merged I/O column instead of prefit netlist.
6.2.5.2. Address Lookup
If you do not set the pin locations in the .qsf file, the lane addresses and pin
placement to an interface changes every time you compile your design in Quartus
Prime software. However, the PHY Lite for Parallel Interfaces Intel FPGA IP is always
generated as if the IP is the only IP in a column, with lane addresses starting from 0.
You need to determine the lane and pin addresses in order to dynamically reconfigure
the calibration settings in the IP core.
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Figure 154. Lane and Pin Placement Dependent Addresses

This figure shows two examples of a placed group with two lanes, 16 data pins and a differential strobe.
data_io[11]
Lane Address 8 data_io[10]
data_io[14]
PHY Lite for Parallel Interfaces Intel FPGA IP data_io[13]
strobe_io data_io[3]
Lane Address 0 strobe_io_n data_io[12]
data_io[4]
data_io[5]
data_io[6] Lane Address 9 strobe_io
data_io[7] strobe_io_n
Lane Address 1 data_io[10] data_io[5]

data_io[11]
data_io[15]
data_io[12]
data_io[13]
data_io[15]
data_io[0]
Example 1 Example 2
To provide a unified way to look up reconfigurable feature addresses for a specific

interface both before and after placement, the address information is stored in
memory in the I/O column. This memory is addressable over the same Avalon
memory-mapped interface used for feature reconfiguration.
You can cache lookups 1 to 4 (8-bytes of information) to have pin and lane
translations in one look-up.
Table 120. Memory Lookup Components

This table lists the two main components of the memory lookup.
Global parameter table Stores pointers to the individual interface parameter tables. The global parameter table
lists all interfaces in the column (both the External Memory Interfaces and PHY Lite for
Parallel Interfaces Intel FPGA IP).
Set of individual interface Contain interface specific information. This is where pin-level and lane-level address look-
parameter tables ups are performed.
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Figure 155. Memory Overview in Arria 10 and Cyclone 10 GX Devices

32-bits (4 Byte Addresses)
{id[3:0],24’h00E000}
Global Parameter Table
(One per column, same as EMIF)
{id[3:0],24'00E018} {4’b1000,id[3:0], pt_ptr[23:0] 1
A {4'h8,id[3:0],8'h00,interface_table_ptr[15:0]}
{id[3:0],24’h00E000} + pt_ptr PT_VER[15:0],IP_VER[15:0]

{id[3:0],24’h00E000} + pt_ptr 28’d4 Number of Groups 2 B
3 num_lanes[1:0],num_pins[5:0]
Number of Groups
Parameter Table
(PHY Lite Specific)
{id[3:0],24’h00E000} + pt_ptr + Number of Groups lane_ptr[15:0],pin_ptr[15:0] 4
{22’d0,num_grps[7:2],2’b00} + 28 d8
One per Interface
{id[3:0],24’h00E000} + lane_ptr Group 0 Lane 0 5

Needed for simplifying
Lane Address Table strobe feature logic
(PHY Lite Specific) address lookups
D
{id[3:0],24’h00E000} + pin_ptr Group 0 Pin 1 Group 0 Pin 0 6
Needed for pin
address lookups
Pin Address Table
(PHY Lite Specific)
A The MSB of the interface pointer entry in the global parameter table is 1 for PHY Lite interfaces.
B num_lanes[1:0] starts counting at 0. For example, 0 = 1 lane, 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes
C Lane address table information: Group X Lane Y = lane_addr[7:0]
D Pin address table information: Group X Pin Y = {lane_addr[7:0],0xF,pin[3:0]} for data and
{lane_addr[7:0],0xE,pin[3:0]} for strobe
Below are the steps to determine the lane and pin addresses from the lookup tables
(the sequence corresponds to the sequence in the preceding figure. ):
Table 121. Parameter Table Lookup Operation Sequence

The base address for PHY Lite for Parallel Interfaces Intel FPGA IP for Arria 10 devices and PHY Lite for Parallel
Interfaces Intel FPGA IP for Cyclone 10 GX devices are 24'h00E000.
Memory
Overview in
Arria 10 and
Cyclone 10 GX
Devices
1 Search for Interface Parameter Table in Global Parameter Table (cache once per interface)
• {id{3:0],24'h00E000} + 28'h18 to {id{3:0],24'h00E0000} + 28'h2C
• 1 to 11 look-ups
2 Retrieve number of groups in the interface (cache once per interface)

• {id[3:0],24'h00E000} + {4'h0,pt_ptr[23:0]} + 4'h4
• You can skip this sequence if the number of groups is saved in the core during compilation (for
example, hard coded in RTL logic)
3 Retrieve group information (cache once per group)

• {id[3:0],24'h00E000} + {4'h0,pt_ptr[23:0]} + 24'h4 + grp_num
• Not always necessary
continued...
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Memory
Overview in
Arria 10 and
Cyclone 10 GX
Devices
4 Retrieve Lane/Pin Address Offsets for group (cache once per group)
• {id[3:0],24'h00E000} + pt_ptr + {22'd0,num_grps[7:2],2'b00} + 28'd8
5 Perform lane/pin address translation (cache once per pin)

• {id[3:0],24'h00E000} + {12'h000,lane_ptr[15:0]} + lane_num
• {id[3:0],24'h00E000} + {12'h000,pin_ptr[15:0]} + {17'h0,pin_num[5:0], 1'b0}
6 Read/Write Avalon Calibration Bus

• {id[3:0],24'h800000} + read_from_step_4 + intra_lane_addr
6.2.5.2.1. Strobes
The first pins listed in the pin address lookup table are the strobes. They are also
identified by bits[7:4] = 0xE. For separate strobes, the input strobe pin placement
always take precedence. For differential and complementary strobes, the positive pin
is the lower index.
Note: You can modify the output phase of differential strobes by writing to either the positive
or negative pin. Only one write is necessary. This is also the case for output-only
complementary strobes.
6.2.5.2.2. Parameter Table Examples
Single PHY Lite for Parallel Interfaces Intel FPGA IP for Arria 10 and Cyclone
10 GX Devices
The following figure shows an example of the design containing a single PHY Lite for
Parallel Interfaces Intel FPGA IP for Arria 10 and Cyclone 10 GX devices with one
bidirectional group composed of four data bits and one strobe. Refer to the Example of
Identifying the Lane and Pin Addresses from Parameter Table to determine the lane
and pin addresses from the parameter table.
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Figure 156. Parameter Table Example for Single PHY Lite IP Core 0
Table 122. Example of Lane and Pin Addresses Identification from Parameter Table
To access the Base address 24’hE000 — —

parameter table.
To determine the size Base address + 24’hE000 + 24’h014= 00000064 The size of the
of the parameter table 24’h014 24’hE014 parameter table is 7C
by generating an that means the
address. information about PHY
Lite is from address
24’hE000 to 24’hE064.
To determine the Base address + 24’hE000 + 24h’018 = 80000044 • Bit[1:0]: 44

address offset of 24h’018 24h’018 address offset
PHY Lite in the point to PHY Lite IP
parameter table. • {4’h0,
pt_ptr[23:0]} is
044
• Bit[6]: PHY Lite
interface ID
To determine the Base address + 24’hE000 + 24’h044 + 00000001 1 indicates the

number of groups in {4’h0, 4’h4 = 24’hE048 number of groups in
PHY Lite for pt_ptr[23:0]} + this PHY Lite.
interfaces. 4’h4
continued...
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To determine the Base address + 24’hE000 + 24’h044 + 00000005 • Bit[5:0]:

group information {4’h0, 4’h8 = 24’hE04C num_pins[5:0]
that the number of pt_ptr[23:0]} + represents 5 pins
lanes and number of 4’h8 • Bit[7:6]:
pins. num_lanes[7:6]
represents 1 lane
To determine lane Base address + 24’hE000 + 24’h048 + 00540058 • Bit[3:0]:

offset and pin 24’h048 + 24’h08 24’h08 = 24’h E050 pin_off[15:0] =
offset. pin_off = 058
• Bit[7:4]:
lane_off[31:16] =
lane_off = 054
• Lane_ptr = 054
and pin_ptr = 058
To determine the lane Base address + 24’hE000 +24’h054 = 00000000 Lane address is 0x00
address. {12'h000lane_ptr[1 24’hE054
5:0]}
To determine the pin Base address 24’hE000 + 24’h058 = 00F100E0 • Bit[3:0]: strobe_io
address at 24’hE058 +{12'h000,pin_ptr[ 24’hE058 = lane 0x00, pin 0
to 24’hE064. 15:0]} • Bit[7:4]:
data_io[0] = lane
0x00, pin 1
24’hE05C 00F300F2 • Bit[3:0]:

data_io[1] = lane
0x00, pin 2
• Bit[7:4]:
data_io[2] = lane
0x00, pin 3
24’hE060 000000F4 Bit[3:0]: data_io[3] =

lane 0x00, pin 4
24’hE064 00000000 End of the address
Note: {lane_addr[7:0], 0xE, pin[3:0]} for strobe and {lane_addr[7:0], 0xF, pin[3:0]} for
data.
Two PHY Lite for Parallel Interfaces Intel FPGA IP for Arria 10 and Cyclone 10
GX Devices
The following figure shows an example of a design containing two PHY Lite for Parallel
Interfaces Intel FPGA IP for Arria 10 and Cyclone 10 GX devices, each with one
bidirectional group composed of four data bits and one strobe. Both interfaces are in
the same I/O column, and therefore must merge the tables.
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Figure 157. Parameter Table Example for Arria 10 and Cyclone 10 GX Devices
PHY Lite for Parallel Interfaces IP core 0 PHY Lite for Parallel Interfaces IP core 1 Merged Column Parameter Table
Addr Data Addr Data Addr Data
E000 00000001 E000 00000001 E000 00000001
E004 00000001 E004 00000001 E004 00000001
E008 00000001 E008 00000001 E008 00000001
E00C 00000008 E00C 00000008 E00C 00000008
E010 0003D090 E010 0003D090 E010 0003D090
E014 00000064 E014 00000064 E014 00000084
E018 80000044 E018 81000044 E018 81000044
E01C 00000000 E01C 00000000 E01C 80000064
E020 00000000 E020 00000000 E020 00000000
E024 00000000 E024 8100005C Interface E024 8000005C
E028 00000000 E028 00000000 pointer E028 8100007C PHY Lite
E02C 00000000 E02C 00000000 E02C 00000000 for Parallel
E030 00000000 E030 00000000 E030 00000000 Interfaces
E034 00000000 E034 00000000 E034 00000000 IP core 1
E038 00000000 E038 00000000 E038 00000000 strobe_io = lane 0x39,pin 4
E03C 00000000 E03C 00000000 E03C 00000000 data_io [ 0 ] = lane 0x39, pin 3
E040 00000000 E040 00000000 E040 00000000 data_io [ 1 ] = lane 0x39, pin 11
1 group with 5 E044 00013800 E044 00013800 E044 00013800 data_io [ 2 ] = lane 0x39, pin 7
pins and 1 E048 00000001 E048 00000001 E048 00000001 data_io [ 3 ] = lane 0x39, pin 10
lane in the E04C 00000005 E04C 00000005 E04C 00000005
interface E050 00540058 E050 00540058 E050 00540058
E054 00000000 Pin pointer E054 00000000 E054 00000039
E058 00F100E0 E058 00F100E0 E058 39F339E4
E05C 00F300F2 E05C 00F300F2 Number of group E05C 39F739FB
E060 000000F4 E060 000000F4 Group 0 – 5 pins, 1 lane E060 000039FA
E064 00013800 PHY Lite
E068 00000001 for Parallel
Lane pointer E06C 00000005 Interfaces
strobe_io = lane 0x00,pin 0 E070 00740078
data_io [ 0 ] = lane 0x00, pin 1 IP core 0
strobe_io = lane 0x00,pin 0 E074 0000003A
data_io [ 0 ] = lane 0x00, pin 1 data_io [ 1 ] = lane 0x00, pin 2 E078 3AF13AE4 strobe_io = lane 0x3A, pin 4
data_io [ 1 ] = lane 0x00, pin 2 data_io [ 2 ] = lane 0x00, pin 3 E07C 3AFA3AF9 data_io [ 0 ] = lane 0x3A, pin 1
data_io [ 2 ] = lane 0x00, pin 3 data_io [ 3 ] = lane 0x00, pin 4 E080 00003AF8 data_io [ 1 ] = lane 0x3A, pin 9
data_io [ 3 ] = lane 0x00, pin 4 data_io [ 2 ] = lane 0x3A, pin 10
data_io [ 3 ] = lane 0x3A, pin 8
Important: There is no guarantee of ordering the interface parameter tables in the merged table.
You must perform a search to locate a specific interface parameter.
For more information about the contents of the parameter table, refer to the Address
Lookup topic.
is placement dependent. If PHY Lite for Parallel Interfaces Intel FPGA IPs and the
External Memory Interface IPs share the same I/O column, you must track the
addresses of the interface lanes and the pins.
There are two sets of control registers that store the reconfiguration feature settings:
• Control/Status registers (CSR) - you can only read the values of these registers.
• Avalon memory-mapped interface registers - you can read and write to these
registers using the Avalon interface. The time for the the PHY Lite for Parallel
Interfaces Intel FPGA IP delays to change after writing a new value to the
registers via the Avalon bus is dependent on the user's configuration. For example,
it takes approximately 50 VCO clock cycles for the output delay to change value.
Perform an RTL simulation to show an accurate timing which correlates to the
hardware operation.
6.2.5.3.1. PHY Lite for Parallel Interfaces Intel FPGA IP for Arria 10 and Cyclone 10 GX
Address Registers
The following tables show the register bits to construct the control register addresses
for each feature.
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Table 123. Address Register for Pin Output Delay Feature

Register
Value Access Type Value Access Type
Parallel Interfaces IP Interface ID Interface ID
interface ID. parameter in the parameter in the

base address.
[20:13] Specify the lane address of You can query this in RW You can query this in RO
an interface. This value is the Parameter Table the Parameter Table
depending on the resource Lookup Operation Lookup Operation
fitting process during Sequence as Sequence as
compilation. described in the described in the
Address Lookup topic. Address Lookup topic.
[12:8] Specify the address for the You can query this in RW You can query this in RO
physical location of a pin the Parameter Table the Parameter Table
within a lane. Lookup Operation Lookup Operation
Sequence as Sequence as
described in the described in the
Address Lookup topic Address Lookup topic
or based on your pin or based on your pin
assignment setting in assignment setting in
the .qsf file. the .qsf file.
[7:0] Reserved 8'hD0 RW 8'hE8 RO
Table 124. Address Register for Pin Input Delay Feature

Register

Parameter Editor.

base address.
[20:13] Specify the lane address of You can query this in RW N/A RO
an interface. This value is the Parameter Table
depending on the resource Lookup Operation
fitting process during Sequence as
compilation. described in the
Address Lookup topic.
[12:9] Reserved 4'hC RW N/A RO

continued...
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Register
[8:7] Select DQ pin sets to • 2'h1: DQ 0 to DQ RW N/A RO

access. 5
• 2'h2: DQ 6 to
DQ11
[6:4] Select the specific DQ pin to • 3'h0: DQ 0 and RW N/A RO

access. DQ 6
• 3'h1: DQ 1 and
DQ 7
• 3'h2: DQ 2 and
DQ 8
• 3'h3: DQ 3 and
DQ 9
• 3'h4: DQ 4 and
DQ 10
• 3'h5: DQ 5 and
DQ 11
Table 125. Address Register for Strobe Input Delay Feature

Register

Parameter Editor.

base address.
[20:13] Specify the lane address of You can query this in RW N/A RO
an interface. This value is the Parameter Table
depending on the resource Lookup Operation
fitting process during Sequence as
compilation. described in the
Address Lookup topic.
[12:0] Reserved 13'18E0 RW N/A RO
Table 126. Address Register for Strobe Enable Phase Feature

Register
continued...
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Register

base address.
[12:0] Reserved 13h'18F0 RW 13'h1998 RO
Table 127. Address Register for Strobe Enable Delay Feature

Register

base address.
[12:0] Reserved 13'h1808 RW 13'h19A8 RO
Table 128. Address Register for Read Valid Delay Feature

Register
[27:24] Specify the PHY Lite for Depending on the RW Depending RO

Parallel Interfaces Intel FPGA Interface ID on the
IP interface ID. parameter in the Interface
Parameter Editor. ID
parameter in
the
Parameter
Editor.
continued...
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Register
[23:21] Specify the Avalon controller 3'h4 RW 3'h4 RO

calibration bus base address.
[20:13] Specify the lane address of You can query this in RW You can RO
an interface. This value is the Parameter Table query this in
depending on the resource Lookup Operation the
fitting process during Sequence as Parameter
compilation. described in the Table Lookup
Address Lookup Operation
topic. Sequence as
described in
the Address
Lookup
topic.
[12:0] Reserved 13'h180C RW 13'h19A4 RO
Related Information
6.2.5.3.2. Control Registers Description
interface returns a set of values from the control registers. The following tables show
the definition of the bits for each control register.
Table 129. Control Register Description

Pin Output Delay [31:13] Reserved (15)
[12:0] Phase value

Strobe minimum setting: Refer to the Output and
Settings topic.
Strobe maximum setting: Refer to the Output and
Settings topic.
The CSR value for DQS is set through the Output
Strobe Phase parameter during IP instantiation.
Note: The pin output delay switches from the CSR
register value to the Avalon register value
after the first Avalon write. It is only reset to
the CSR register value on a reset of the
interface.
Pin Input Delay [31:13] Reserved (15)

register.
this feature.
continued...
(15) Reserved bit ranges must be zero
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[11:9] Reserved (15)
[8:0] Delay value

Minimum Setting: 0
Strobe Input Delay [31:13] Reserved (15)

register.
this feature.
group.
[9:0] Delay value

Minimum Setting: 0
group.
Strobe Enable Phase [31:16] Reserved (15)

register.
0 = Select delay value from CSR register. The CSR
value is set through the Capture Strobe Phase
Shift parameter during IP instantiation.
group.
[12:0] Bit [12:0]: Phase value

Minimum Setting: Refer to the Output and Strobe
Maximum Setting: Refer to the Output and Strobe
group.
Strobe Enable Delay [31:16] Reserved(15)

register.
group.
[14:6] Reserved(15)
[5:0] Delay value

continued...
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group.
Read Valid Delay [31:16] Reserved(15)

register.
group.
[14:7] Reserved
[6:0] Delay value

group.
Important: For more information about performing various clocking and delay calculations,
Related Information
Output and Strobe Enable Minimum and Maximum Phase Settings on page 225
6.2.5.4. Calibration Guidelines
The PHY Lite for Parallel Interfaces Intel FPGA IP allows you to dynamically reconfigure
the features of the interface. However, performing calibration is an application specific
process. This section provides some general guidelines for calibrating the Arria 10 and
Cyclone 10 GX I/O architecture.
rdata_en to high.

one core clock cycle,eight strobes are toggled. Ideally, in normal PHY state, after the
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Figure 158. Input Path of PHY Lite for Parallel Interfaces Intel FPGA IP for Arria 10and
Cyclone 10 GX Devices
data_in
(PVT) data_io_n
strobe_in
strobe_in_n
dqs strobe_io
dqs_clean
(PVT)
rdata_valid
dqs_enable_out
rdata_en
phy_clk
interpolator_clk

red marker).
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rdata_en
gate (internal)
rdata_en
gate (internal)
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rdata_en
gate (internal)
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When dynamically reconfiguring the interpolator phase settings, the values must be
kept within the ranges below to ensure proper operation of the circuitry.
Minimum Interpolator Phase
VCO
Maximum Interpolator
Multiplication Core Rate
Output Bidirectional Bidirectional with Phase
Factor
OCT Enabled
1 Full 0x080 0x100 0x100 0xA80
Half 0x080 0x100 0x100 0xBC0
Quarter 0x080 0x100 0x100 0xA00
2 Full 0x080 0x100 0x180 0x1400
Half 0x080 0x100 0x180 0x1400
Quarter 0x080 0x100 0x180 0x1400
4 Full 0x080 0x100 0x280 0x1FFF
Half 0x080 0x100 0x280 0x1FFF
8 Full 0x080 0x100 0x480 0x1FFF
Half 0x080 0x100 0x480 0x1FFF
For more information about performing various clocking and delay calculations,

You can instantiate the PHY Lite for Parallel Interfaces Intel FPGA IP from IP Catalog in
Quartus Prime software. Intel provides an integrated parameter editor that allows you
to customize this IP to support a wide variety of applications.
Related Information
version upgrades.
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Table 131. PHY Lite for Parallel Interfaces Intel FPGA IP Parameter Settings
Values
Parameter

Clocks
Interface clock frequency 100 MHz - 1200 533.0 MHz External memory clock frequency.
MHz Note: To achieve timing closure at 534 MHz
and above, use dynamic reconfiguration
to calibrate the interface. Compile your
design with Quartus Prime with accurate
board skew information for final timing
analysis.
desired memory clock of this frequency to the PLL reference
clock frequency clock input of the memory interface.
Note: There is no minimum range, but the
maximum output frequency is 1600 MHz,
limited by the clock network. The
minimum range for the ref_clk signal
is 10 MHz but the maximum is
dependent on the speed grade.
Clock rate of user logic Full, Half, Quarter Quarter Determines the clock frequency of user logic in
Specify additional output On, Off Off Exposes additional output clocks from the
clocks based on existing PLL existing PLL.
Important: PHY Lite for Parallel Interfaces Intel
FPGA IP in Arria 10 and Cyclone 10
GX devices do not support exposing
additional output clocks when VCO
frequency is below 600 MHz.
Output Clocks
Note: These parameters are available only if the Specify additional output clocks based on existing PLL parameter
is turned on
Number of additional clocks 0 to 4 0 Specifies the number of additional clocks to be

exposed.
continued...
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Values
Important: PHY Lite for Parallel Interfaces Intel

FPGA IP in Arria 10 and Cyclone 10
GX devices do not support exposing
additional output clocks when VCO
outclk[4:0] (Reserved) — — PLL output clocks with the flag (Reserved) in the
QSYS GUI are reserved for PHY Lite for Parallel
Interfaces Intel FPGA IP internal functionality.
Desired Frequency — 133.25 MHz Specifies the output clock frequency of the
MHz. The minimum and maximum values
depend on the device used. The PLL only reads
the numerals in the first six decimal places.
Actual Frequency — 133.25 MHz Allows you to select the actual output clock
frequency from a list of achievable frequencies.
Phase shift units ps or degrees ps Specifies the phase shift unit for the
picoseconds (ps) or degrees.
Phase shift — 469.0 ps Specifies the requested value for the phase
shift. The default value is 0 ps.
Actual phase shift — 469.0 ps Allows you to select the actual phase shift from
a list of achievable phase shift values. The
default value is the closest achievable phase
shift to the desired phase shift.
Desired duty cycle 0.0–100.0 50.0 % Specifies the requested value for the duty cycle.
Actual duty cycle — 50.0 % Allows you to select the actual duty cycle from a
list of achievable duty cycle values. The default
value is the closest achievable duty cycle to the
desired duty cycle.
settings.
Interface ID — 0 The ID used to identify this interface in the I/O

column over the Avalon memory-mapped
interface bus.
I/O Settings
I/O standard SSTL-12 SSTL-15 Class Specifies the I/O standard of the interface's
SSTL-125 I strobe and data pins written to the .qip file of
the IP instance. When you choose None, the
SSTL-135
I/O standard is unspecified in the generated IP.
SSTL-15
SSTL-15 Class I
SSTL-15 Class II
SSTL-18 Class I
SSTL-18 Class II
1.2-V-HSTL Class
I
1.2-V-HSTL Class
II
1.5-V-HSTL Class
I
continued...
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Values
1.5-V-HSTL Class
II
1.8-V-HSTL Class
I
1.8-V-HSTL Class
II
1.2-V POD
1.2-V
1.5-V
1.8-V
None
configuration LVDS with on-
chip termination,
LVDS without on-
chip termination
General Settings
Fast simulation model On, Off Off Turn on this option to reduce PHY Lite for
Parallel Interfaces Intel FPGA IP simulation time.
Note: This option is preliminarily supported in
Quartus Prime v18.1.
Group <x> Parameter Settings
Copy parameters from another On, Off Off Select this option when you want to copy the
group parameter settings from another group.
enable this option.
Group 1 - 17 1 Choose the group index that you want as the

parameter settings source. The changes made
to the source is updated automatically to all the
target groups.
You can only choose the group index which the
parameter settings are not copied from another
group.
enable this option.

Pin width 1 to 48 9 Number of pins in this data/strobe group.

A data width up to 48 is achievable if no strobe
is used in the group. The number of strobes is
controlled by the Use output strobe, Strobe
configuration and Use separate capture
strobe parameters.

continued...
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Values

cycles For example, a design with an external clock
frequency of 533 MHz in half-rate has a valid
read latency range of 5 to 63 external interface
clock cycles.
Refer to the Read Latency topic for minimum
rate.
Swap capture strobe polarity On, Off Off Internally swap the negative and positive
capture strobe input pins. This feature is only
available for complementary strobe
configurations.
Capture strobe phase shift 0, 45, 90, 135, 90 Internally phase shift the input strobe relative to
180 input data.

Write latency 0 to 3 (maximum 0 Additional delay added to the output data in

value is memory clock cycles.
dependent on the Refer to the Write Latency topic for write latency
rate) settings based on FPGA core clock rate.
Use output strobe On, Off On Use an output strobe.
180 output data.
Group <x> General Data Settings

Data configuration Single ended, Single ended Selects the type of data. Single ended data type
Differential uses one pin. Differential data type uses 2 pins.

Strobe configuration Single ended, Single ended Select the type of strobe. A single ended strobe
Differential, uses one pin, which reduces the maximum
Complementary possible number of data pins in the group to 47.
Differential/complementary strobe types use 2
pins, which reduces the maximum possible
number of data pins in the group to 46.
Note: The differential strobe configuration uses
DDIO and read FIFO. The
complementary strobe configuration
uses two single-ended input buffers and
clocks the data into the capture DDIO
and read FIFO using both clocks (as
required by protocols such as QDRII).
The output path functionality is the
same.
continued...
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Values
Use separate strobes On, Off Off Separate the bidirectional strobe into input and
output strobe pins. Use separate strobes is only
available for a bidirectional data group with the
output strobe enabled.

OCT enable size 0 - 4 (Arria 10 1 Specifies the delay between the OCT enable
and Cyclone 10 signal assertion and the dqs_enable signal
GX devices) assertion. You must set a value that is large
Note: For Quartus Prime software version prior
to 17.0, refer to related information for
known issue.
Expose termination ports On, Off Off Turn on to expose the series and parallel
termination ports to connect separate OCT
block.
To enable this option, turn off Use Default OCT
Values parameter and select a value for Input
OCT Value or Output OCT Value parameters.
Use Default OCT Values — — Use default OCT values based on the I/O
Input OCT Value No termination, No Specifies the group's data and strobe input
calibration the IP instance. The list of legal values is
dependent on the I/O standard parameter
setting. Refer to the I/O Standards topic for
Output OCT Value No termination, No Specifies the group's data and strobe input
calibration, <n> the IP instance. The list of legal values is
with no dependent on the I/O standard parameter
calibration setting. Refer to the I/O Standards topic for
Group <x> Timing Settings

Generate Input Delay On, Off On Instructs SDC to generate set_input_delay

Input Strobe Setup Delay Constraint in ns 0.03 ns Specifies the group's input setup delay
Input Strobe Hold Delay Constraint in ns 0.03 ns Specifies the group's input hold delay constraint
Constraint against the input strobe.
the Read Channel for DQS signal of read channel.
Generate Output Delay On, Off On Instructs SDC to generate set_output_delay

continued...
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Values
Output Strobe Setup Delay Constraint in ns 0.03 ns Specifies the group's output setup delay
Output Strobe Hold Delay Constraint in ns 0.03 ns Specifies the group's output hold delay
the Write Channel for DQS signal of write channel.
Group <x> Dynamic Reconfiguration Timing Settings

Dynamic Reconfiguration Read DQ Per-Bit DQ Per-Bit Specifies the Read Deskew algorithm for Timing
Deskew Algorithm Deskew, DQ Deskew Analyzer to use when performing I/O timing
Custom Deskew • DQ Per-Bit Deskew: Each DQ pin is adjusted
independently to minimize the skew within
the DQ bits. DQS signal is adjusted to center-
align to the de-skewed DQ bus. Each DQ bit
may have different delay chain settings.
• DQ Group Deskew: DQS signal is adjusted
center-align to the DQ bus without de-
skewing individual DQ bits. All DQ bits within
the same group has same delay chain
settings.
defined.
and
and
Dynamic Reconfiguration DQ Per-Bit DQ Per-Bit Specifies the Write Deskew algorithm for Timing
Write Deskew Algorithm Deskew, DQ Deskew Analyzer to use when performing I/O timing
Custom Deskew
continued...
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Values
• DQ Per-Bit Deskew: DQS signal is centered to

each individual DQ bits. Each DQ bit may
have different delay chain settings.
• DQ Group Deskew: DQS signal is centered to
the DQ bus group. All DQ bits within the
same group has same delay chain settings.
defined.
and
and
Related Information
• KDB link: Can the Intel Arria 10 and Intel Cyclone 10 GX I/O PLL have a VCO
• KDB link: Unsupported OCT enable size values for Arria 10 Altera PHYLite.
Applicable to the Quartus Prime software version prior to 17.0.
• Read Latency on page 232
• Write Latency on page 233

This table shows the minimum read latency value supported by PHY Lite for Parallel Interfaces Intel FPGA IP
based on the core clock rate and VCO multiplier factor settings.
Cycle)
Full rate 1 4
2 4
4 3
8 3
continued...
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Cycle)
Half rate 1 5
2 5
4 4
8 4
Quarter rate 1 7
2 7
4 7
8 7

This shows the maximum write latency value supported by PHY Lite for Parallel Interfaces Intel FPGA IP based
on the core clock rate and VCO multiplier factor settings.

Core Clock Rate
Cycle)
Full rate 1 0
2 0
4 0
8 0
Half rate 1 1
2 1
4 1
8 1
Quarter rate 1 3
2 3
4 3
8 2
6.3.2. Signals

synchronous with strobe_in to ensure the dqs_enable signal
is in-sync with strobe_in.
reset_n Input 1 Resets the interface. This signal is asynchronous.

continued...
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interface_locked Output 1 Interface locked signal from PHY Lite for Parallel Interfaces Intel
FPGA IP to Intel FPGA IP FPGA core. This signal indicates that the
PLL and PHY circuitry are locked.
Data transfer should starts after the assertion of this signal.
pll_extra_clock[0..3] Output 4 These are the additional output clock signals generated by PHY
Lite for Parallel Interfaces Intel FPGA IP when you enable Specify
additional output clocks based on existing PLL parameter.
Important: PHY Lite for Parallel Interfaces Intel FPGA IP in Arria
10 and Cyclone 10 GX devices do not support
exposing additional output clocks when VCO
pll_locked Output 1 This is the locked signal for the additional output clocks generated
by the IP.

Output path signals are signals that are available when you set the Pin Type parameter to either Output or
Bidirectional.
oe_from_core Input Quarter-rate: 4 x PIN_WIDTH Output enable signal from core logic.
Half-rate: 2 x PIN_WIDTH Synchronous to the core_clk
output from the IP.
Full-rate: 1 x PIN_WIDTH
Quarter rate-DDR: 8 x PIN_WIDTH

Half-rate DDR: 4 x PIN_WIDTH
Full-rate DDR: 2 x PIN_WIDTH Data signal from core logic.
data_from_core Input Synchronous to the core_clk
Quarter-rate SDR: 4 x PIN_WIDTH output from the IP.
strobe_out_in Input Quarter-rate: 8 Strobe signal from core logic.

Half-rate: 4 Synchronous to the core_clk
Note: This path is always DDR.
strobe_out_en Input Quarter-rate: 4 Strobe output enable from core logic.

Half-rate: 2 Synchronous to the core_clk
data_out/data_io Output/ • 1 to 48 if data configuration is Data output from PHY Lite for Parallel
Bidirectional Single Ended Interfaces Intel FPGA IP.
• 1 to 24 if data configuration is Synchronous to the strobe_out or
Differential strobe_io output from the IP.
Output, the data_out signals are
used. If the Pin Type parameter is
set to Bidirectional, the data_io
signals are used.
continued...
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data_out_n/ Output/ 1 to 24 Negative data output from PHY Lite

data_io_n Bidirectional for Parallel Interfaces Intel FPGA IP is
enabled when data configuration is
set to Differential. Data is
synchronous to the strobe_out or
strobe_io output from the IP. If
the Pin Type is set to Output, the
data_out_n ports are used. If the
data_io_n ports are used.
strobe_out/ Output/ 1 Positive output strobe from PHY Lite

strobe_io Bidirectional for Parallel Interfaces Intel FPGA IP.
strobe_out signal is used. If the
Pin Type is set to Bidirectional the
strobe_io signal is used. The Use
Separate Strobes parameter forces
the use of the strobe_out signal
with a Bidirectional Pin Type.
strobe_out_n/ Output/ 1 Negative output strobe from PHY Lite

strobe_io_n Bidirectional for Parallel Interfaces Intel FPGA IP.
This is used if the Strobe
Configuration is set to Differential
or Complementary.
strobe_out_n signal is used. If the
Pin Type is set to Bidirectional, the
strobe_io_n signal is used. The
Use Separate Strobes parameter
forces the use of the strobe_out_n
signal with a Bidirectional Pin
Type.

Bidirectional.
data_to_core Output Quarter-rate DDR: 8 x PIN_WIDTH Output data to the core logic. Valid
Half-rate DDR: 4 x PIN_WIDTH on rdata_valid. Synchronous to
Full-rate DDR: 2 x PIN_WIDTH
Quarter-rate SDR: 4 x PIN_WIDTH IP.
rdata_en Input Quarter-rate: 4 This signal represents the number of

Half-rate: 2 expected words to read from the
external device.
Full-rate: 1
IP.
asserted and strobe_in is stable.
continued...
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rdata_valid Output Quarter-rate: 4 This signal determines which data are

Half-rate: 2 valid when reading from Read FIFO.
Full-rate: 1 Delayed by READ_LATENCY with
clock cycles.
Synchronous to the core_clk
output from the PHY Lite for Parallel
data_in/ Input/ 1 to 48 if data configuration is Single Input and output data from/to
data_io Bidirectional Ended external device. Synchronous to the
1 to 24 if data configuration is Differential strobe_in or strobe_io input.
The first data_in must be associated
with positive edge of strobe_in/
strobe_io.
data_in ports are used. If the pin
data_io ports are used.
data_in_n/ Input/ 1 to 24 Negative data input/output from

data_io_n Bidirectional external device enabled when data
configuration is set to Differential.
Data is synchronous to the
strobe_in or strobe_io input. If
data_in_n ports are used. If the pin
data_io_n ports are used.
strobe_in/ Input/ 1 Input and output strobe from/to

strobe_io Bidirectional external device. If the pin type is set
to Input, the strobe_in signal is
Bidirectional, the strobe_io signal
is used.
strobe_in_n/ Input/ 1 Negative strobe from/to external

strobe_io_n Bidirectional device. This is used if the Strobe
Configuration parameter is set to
Differential or Complementary. If
strobe_in_n signal is used. If the
strobe_io_n signal is used.
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6.3.2.4. Avalon Configuration Bus Interface Signals
interface slave and Avalon memory-mapped interface master interfaces when you
perform dynamic reconfiguration. Connect the Avalon memory-mapped interface slave
to either a master in the core or the master interface of either an PHY Lite for Parallel
Interfaces Intel FPGA IP or the External Memory Interface IP to be placed in the same
column. You can only connect the master interface to the slave interface of a PHY Lite
for Parallel Interfaces Intel FPGA IP or External Memory Interface IP to be placed in
the same column.
Table 137. Avalon Memory-Mapped Interface Master Interface Signals

avl_clk Input 1 Avalon interface clock.
avl_reset_n Input 1 Reset input synchronous to avl_clk.
avl_read Input 1 Read request from io_aux. This signal is synchronous to the
avl_clk input.
avl_write Input 1 Write request from io_aux. This signal is synchronous to the
avl_clk input.
avl_byteenable Input 4 Controls which bytes should be written on avl_writedata.
avl_address Input 28 (Arria 10 Address from io_aux. This signal is synchronous to the
and Cyclone 10 avl_clk input.
GX devices)
avl_readdata Output 32 Read data to io_aux. This signal is synchronous to the

avl_clk input.
avl_writedata Input 32 Write data from io_aux. This signal is synchronous to the
avl_clk input.
avl_readdata_valid Output 1 Indicates that read data has returned.
avl_waitrequest Output 1 Stalls upstream logic when it is asserted.
Table 138. Avalon Memory-mapped Slave Interface Signals

avl_out_clk Output Connect this signal to the input Avalon interface of another
PHY Lite for Parallel Interfaces Intel FPGA IP or the External
Memory Interfaces IP.
avl_out_reset_n Output 1 Connect this signal to the input Avalon interface of another
PHY Lite for Parallel Interfaces Intel FPGA IP or the External
Memory Interfaces FPGA IP.
avl_out_read Output 1 Indicates read transaction.
avl_out_write Output 1 Indicates write transaction.
avl_out_byteenable Output 4 Controls which bytes should be written on

avl_out_writedata.
avl_out_writedata Output 32 The data packet associated with the write transaction.
avl_out_address Output 28 (Arria 10 Avalon address (in byte granularity). Value is identical to
and Cyclone 10 avl_address but with zeroes padded on the LSBs.
GX devices)
continued...
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avl_out_readdata Input 32 The data packet associated with

avl_out_readdata_valid.
avl_out_readdata_val Input 1 Indicates that read data has returned.

id
avl_out_waitrequest Input 1 Stalls upstream logic when it is asserted.
Related Information
For more information about connecting these signals
6.3.2.5. Termination Signals
Table 139. Termination Signals

The termination signals are signals that are available when you enable the Expose termination ports
parameter.
group_seriestermin Input 16 Connect this signal to the series

ationcontrol termination control signal of the OCT
Intel FPGA IP to receive series
termination code to calibrate Rs.
Connect this signal to the parallel

group_parallelterm termination control signal of the OCT
Input 16
inationcontrol Intel FPGA IP to receive parallel
termination code to calibrate Rt.
6.4. I/O Standards

The PHY Lite for Parallel Interfaces Intel FPGA IP allows you to set I/O standards on
the pins associated with the generated configuration. The I/O standard controls the
available strobe configurations and OCT settings for all groups.
Table 140. I/O Standards and Termination Values for Arria 10 Devices
Terminations (Ω) Calibrated/ (Ω) (17) Support
(16) Uncalibrated
Terminations
(Ω)(16)
SSTL-12 (18) 60, 120 40, 60 240 Yes
SSTL-125 (18) 60, 120 34, 40 240 Yes
SSTL-135 (18) 60, 120 34, 40 240 Yes
SSTL-15 (18) 60, 120 34, 40 240 Yes

continued...
(16) 0 is equivalent to no termination.

(17) RZQ pin is not required for uncalibrated output terminations.
(18) Use this I/O standard if input termination is required with interface frequency more than 533
MHz.
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Terminations (Ω) Calibrated/ (Ω) (17) Support
(16) Uncalibrated
Terminations
(Ω)(16)
SSTL-15 Class I (19) 0, 50 0, 50 100 Yes
SSTL-15 Class II(19) 0, 50 0, 25 100 Yes
SSTL-18 Class I(19) 0, 50 0, 50 100 Yes
SSTL-18 Class II(19) 0, 50 0, 25 100 Yes
1.2-V HSTL Class I(19) 0, 50 0, 50 100 Yes
1.2-V HSTL Class II(19) 0, 50 0, 25 100 Yes
1.5-V HSTL Class I(19) 0, 50 0, 50 100 Yes
1.8-V HSTL Class I(19) 0, 50 0, 50 100 Yes
1.2-V POD 34, 40, 48, 60, 80, 34, 40, 48, 240 Yes
120, 240 60
1.2-V — — — No
1.5-V — — — No
1.8-V — — — No
Table 141. I/O Standards and Termination Values for Cyclone 10 GX Devices
Terminations Calibrated/ (Ω) (17) Support
(Ω) (16) Uncalibrated
Terminations
(Ω)(16)
SSTL-12 (20) 60, 120 40, 60 240 Yes
SSTL-125 (20) 60, 120 34, 40 240 Yes
SSTL-135 (20) 60, 120 34, 40 240 Yes
SSTL-15 (20) 60, 120 34, 40 240 Yes
SSTL-15 Class I (21) 0, 50 0, 50 100 Yes
SSTL-15 Class II(21) 0, 50 0, 25 100 Yes

continued...
(16) 0 is equivalent to no termination.

(17) RZQ pin is not required for uncalibrated output terminations.
(19) Use this I/O standard if input termination is required with interface frequency equal or less
than 533 MHz.
(20) Use this I/O standard if input termination is required with interface frequency more than 533
MHz.
(21) Use this I/O standard if input termination is required with interface frequency equal or less
than 533 MHz.
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Terminations Calibrated/ (Ω) (17) Support
(Ω) (16) Uncalibrated
Terminations
(Ω)(16)
SSTL-18 Class I(21) 0, 50 0, 50 100 Yes
SSTL-18 Class II(21) 0, 50 0, 25 100 Yes
1.2-V HSTL Class I(21) 0, 50 0, 50 100 Yes
1.5-V HSTL Class I(21) 0, 50 0, 50 100 Yes
1.8-V HSTL Class I(21) 0, 50 0, 50 100 Yes
1.2-V POD 34, 40, 48, 60, 80, 34, 40, 48, 240 Yes
120, 240 60
1.2-V — — — No
1.5-V — — — No
1.8-V — — — No
Related Information
• On-Chip I/O Termination in Arria 10 Devices
• On-Chip I/O Termination in Cyclone 10 GX Devices
• KDB link: Selected input mode termination value for data bus is not valid. Please
select a value of 50 ohm or higher.
Input termination limitation for PHY Lite for Parallel Interfaces IP.

The POD I/O standard allows configurable VREF. By default, the externally provided
VREF is used and using an internal VREF requires the following .qsf assignments:
set_instance_assignment -name VREF_MODE <mode> -to <pin_name>
Note: The VREF settings are at the lane level, so all pins using a lane must have the same
VREF settings (including GPIOs).

CALIBRATED Use internal VREF generated using VREF codes from the Avalon memory-mapped interface
reconfiguration bus.
VCCIO_45 Use internal VREF generated using static VREF code. VREF is 45% of VCCIO.
continued...
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Figure 161. VREF
Input Buffer
VCCIO
Rt
+
Vref -
R
VCCIO
Internal VREF
+
-
Resistor
Ladder R

6.4.1.1. Calibrated VREF Settings
Table 143. Calibrated VREF Settings

This table lists the calibrated VREF settings that you can set over the Avalon memory-mapped interface
calibration bus. This table is applicable to all Intel FPGA devices.
000000 60.00%
000001 60.64%
000010 61.28%
000011 61.92%
000100 62.56%
000101 63.20%
continued...
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000110 63.84%
000111 64.48%
001000 65.12%
001001 65.76%
001010 66.40%
001011 67.04%
001100 67.68%
001101 68.32%
001110 68.96%
001111 69.60%
010000 70.24%
010001 70.88%
010010 71.52%
010011 72.16%
010100 72.80%
010101 73.44%
010110 74.08%
010111 74.72%
011000 75.36%
011001 76.00%
011010 76.64%
011011 77.28%
011100 77.92%
011101 78.56%
011110 79.20%
011111 79.84%
100000 80.48%
100001 81.12%
100010 81.76%
100011 82.40%
100100 83.04%
100101 83.68%
100110 84.32%
100111 84.96%
101000 85.60%
101001 86.24%
continued...
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101010 86.88%
101011 87.52%
101100 88.16%
101101 88.80%
101110 89.44%
101111 90.08%
110000 90.72%
110001 91.36%
110010 92.00%
110011 -> 111111 Reserved
Related Information

PHY Lite for Parallel Interfaces Intel FPGA IP provides valid OCT settings for each
group (refer to the I/O Standards topic for supported termination values). These
settings are written to the .qip of the instance during generation. If you select an I/O
standard that supports OCT in the General tab, you can use the OCT blocks provided
in the Arria 10 and Cyclone 10 GX devices.

Related Information
instance with an RZQ pin at the system level manually.
Use the following steps to set RZQ pin locations for the PHY Lite for Parallel Interfaces
Intel FPGA IP:
1. In the Group <x> OCT Settings tab, disable Use Default OCT Values and
Expose termination ports.
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Figure 162. Group <x> OCT Settings Parameter Settings


RZQ pin:

<altera_phylite_strobe_pin>

<altera_phylite_data_pin[*]>

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6.4.2.2. Manual Insertion of OCT Block
You may also instantiate the OCT Intel FPGA IP separately in your project and connect
the termination ports to the PHY Lite for Parallel Interfaces Intel FPGA IP.
1. Expose the PHY Lite for Parallel Interfaces Intel FPGA IP termination ports by
disable Use Default OCT Values.
2. Select the available OCT values in the Input OCT Value parameter. This displays
the Expose termination ports parameter.
Note: For supported input and output OCT values, refer to the I/O Standards
topic.
3. Select Expose termination ports to expose the termination ports in the IP.
4. Connect the termination ports to a OCT Intel FPGA IP either in power-up or user
mode.
Figure 163. RTL View of PHY Lite for Parallel Interfaces Intel FPGA IP Interfacing with
OCT Intel FPGA IP in User Mode
group_0_data_in[3:0] phylite_test_ip
group_0_data_in[3:0]
oct_0_parallel_termination_control[15:0] group_0_parallelterminationcontrol[15:0]
calibration_request oct_test_ip
cal_request 4’h0group_0_rdata_en[3:0]
clock
refclk oct_0_series_termination_control[15:0] group_0_seriesterminationcontrol[15:0]
reset group_1_data_out[3:0]
rstn group_0_strobe_in
rzqin group_1_strobe_out
octrzqin0 32’h0group_1_data_from_core[31:0]
u1
16’h0group_1_oe_from_core[15:0] interface_locked
group_0_strobe_in
group_1_parallelterminationcontrol[15:0]
group_1_seriesterminationcontrol[15:0]
ref_clk
reset_n
u0
Related Information
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Follow these guidelines to place the PHY Lite for Parallel Interfaces Intel FPGA IP group
pins.
1. All groups in a PHY Lite for Parallel Interfaces Intel FPGA IP must be placed across
a contiguous set of lanes. The number of lanes depends on the number of pins
used by the group.
2. Two groups, from either the same or different PHY Lite for Parallel Interfaces Intel
FPGA IP, cannot share an I/O lane.
3. For PHY Lite for Parallel Interfaces Intel FPGA IP instance that spans more than
one I/O bank, all groups in the interface must be placed across a contiguous set of
banks within an I/O column. The number of I/O banks required depends on the
memory interface width.
4. Pins that are not used in an I/O bank are available as general purpose I/O (GPIO)
pins.
5. To constrain groups from separate PHY Lite for Parallel Interfaces Intel FPGA IP
instances into the same I/O bank, the instances must share the same reference
clock and reset sources, the same external memory frequencies, and the same
voltage settings.
6. A reference clock network can only span across maximum of 6 I/O banks.
7. You cannot share the OCT termination block across the I/O column. You can
instance with an RZQ pin through RZQ_GROUP assignment.
Table 144. Group Pin Placement

PHY Lite for Parallel Interfaces Intel FPGA IP does not support DQS for X4.
Number of Pins in Group Valid DQS Group in a Bank Valid Index in a Bank
1-12 DQS for X8/X9 {0-11}/{12-23}/{24-35}/{36-47}
13-24 DQS for X16/X18 {0-23}/{24-47}
25-48 DQS for X32/X36 {0-47}
Related Information
Pin-Out Files for Intel FPGA Devices
For specific DQS group numbers refer to the specific device pin-out file

Interfaces Intel FPGA IP from a dedicated clock pin. Use the clock pin in one of the I/O
banks used by the PHY Lite for Parallel Interfaces Intel FPGA IP. You must use
contiguous I/O banks to implement multiple interfaces (consisting of a combination of
External Memory Interface and PHY Lite for Parallel Interfaces Intel FPGA IP). If you
use the same reference clock for these interfaces, place the reference clock in any of
the contiguous I/O banks.
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Note: For Quartus Prime software version 18.1 or later, you may see error warning message
for design with encrypted IOPLL IP. The auto-generated .sdc files of the IOPLL IP are
not supported if you use encryption. You must manually create the .sdc file using
create_clock and create_generated_clock to replace the auto-generated .sdc
file in the design for refclk and output clocks.
Related Information
• Guideline: I/O Standards Supported for I/O PLL Reference Clock Input Pin
• Clock Networks and PLLs in Arria 10 Devices - PLL Cascading
For more information about PLL cascading in Arria 10 devices.
6.5.3. Reset
You can source the reset to the PHY Lite for Parallel Interfaces Intel FPGA IP from an
external pin or from the core. If you source the reset from an external pin, you must
configure the I/O standard of the reset signal in the .qsf file with the following
command:
set_location_asignment <PIN_NUMBER> -to <signal_name>
6.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O
Bank
You can instantiate multiple PHY Lite for Parallel Interfaces Intel FPGA IPs within an
I/O column. To constrain groups from separate PHY Lite for Parallel Interfaces Intel
FPGA IP instances into the same I/O bank, the instances must share the same
reference clock and reset sources, the same external memory frequencies and the
same voltage settings.
Related Information
• KDB Link: Error(14566): The Fitter cannot place 1 periphery component(s) due to

If you are using the dynamic reconfiguration feature, all interfaces of the External
Memory Interfaces and PHY Lite for Parallel Interfaces Intel FPGA IP cores in the same
I/O column must share the reset signal. Multiple IP cores requiring Avalon core
access require daisy chain connectivity.
Related Information
• Daisy Chain on page 209
Describes the daisy chain connectivity
• KDB link: Why is the read data value incorrect the Intel Arria 10 PHYLite IP?
6.5.6. Timing
The Quartus Prime software generates the required timing constraints to analyze the
timing of the PHY Lite for Parallel Interfaces Intel FPGA IP on the all Intel FPGA
devices.
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6.5.6.1. Timing Components
Table 145. Timing Components

Source synchronous Read Path Memory DQ Capture Source synchronous timing paths—paths where
and optionally Device Register clock and data signals are passed from the
calibrated (22) transmitting devices to the receiving devices.
Optionally calibrated paths—paths with delay
Source synchronous Write Path FPGA Memory elements that are dynamically reconfigurable to
and optionally DQ/DQS Device achieve timing closure, especially at higher
calibrated (22) frequency, and to maximize the timing margins.
You can calibrate these paths by implementing
an algorithm and turning on the optional
dynamic reconfiguration feature. An example of
the calibrated path is the FPGA to memory
device write path, in which you can dynamically
reconfigure the delay elements to, for instance,
compensate the skew due to process voltage
temperature variation.
Internal FPGA Core to PHY Core Write FIFO The internal FPGA paths are paths in the FPGA
Lite for Registers fabric. The Timing Analyzer reports the
Parallel corresponding timing margins.
Interfaces
Intel FPGA IP
Path
Internal FPGA PHY Lite for Read FIFO Core Registers

Parallel
Interfaces
Intel FPGA IP
to Core
6.5.6.2. Timing Constraints and Files
To successfully constrain the timing for PHY Lite for Parallel Interfaces Intel FPGA IP,
the IP generates a set of timing files. You can locate these timing files in the
<variation_name> directory:
• <variation_name> .sdc
• <variation_name> _ip_parameters.tcl
• <variation_name> _pin_map.tcl
• <variation_name>_report_timing.tcl
6.5.6.2.1. <variation_name>.sdc
You can find the location of the <variation_name>.sdc file in the .qip or .qsys,
which is generated during the IP generation. The <variation_name> .sdc allows the
Fitter to optimize timing margins with timing driven compilation and allows the Timing
Analyzer to analyze the timing of your design.
(22) Can be optionally calibrated by using dynamic reconfiguration.
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The IP uses <variation_name>.sdc for the following operations:

• Creating clocks on PLL inputs
• Creating generated clocks
• Calling derive_clock_uncertainty
• Creating set_output_delay and set_input_delay constraints to analyze the
timing of the read and write paths
6.5.6.2.2. <variation_name>_parameter.tcl
The <variation_name>_parameters.tcl file is a script that lists the following PHY

Lite for Parallel Interfaces Intel FPGA IP parameters used in the .sdc file and report
timing scripts:
• Jitter
• Simultaneous switching noise
• Calibration uncertainties
6.5.6.2.3. <variation_name>_ip_parameters.tcl
The <variation_name>_ip_parameters.tcl file lists the PHY Lite for Parallel

Interfaces Intel FPGA IP parameters and is read by the <variation_name>.sdc.
6.5.6.2.4. <variation_name>_pin_map.tcl
The <variation_name>_pin_map.tcl is a TCL library of functions and procedures

that <variation_name>.sdc uses.
6.5.6.2.5. <variation_name>_report_timing.tcl
The <variation_name>_report_timing.tcl file is a script that contains timing

analysis flow and reports the timing slack for your variation. This script runs
automatically during calibration (during static timing analysis) by sourcing the
following files:
• <variation_name>_ip_parameters.tcl
• <variation_name>_pin_map.tcl
You can also run <variation_name>_report_timing.tcl with the Report DDR
function in the Timing Analyzer. This script runs for every instance of the same
variation.
Note: You can only use the Report DDR function if you enable the dynamic reconfiguration
feature.
6.5.6.2.6. <variation_name>_report_timing_core.tcl
The <variation_name>_report_timing_core.tcl file is a script that

<variation_name>_report_timing.tcl uses to calculate the timing slack for
your variation. <variation_name>_report_timing_core.tcl runs automatically
during compilation.
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6.5.6.3. Timing Analysis
Table 146. Timing Analysis

This table lists the timing analysis performed in the I/O and FPGA for the PHY Lite for Parallel Interfaces Intel
FPGA IP.
I/O The PHY Lite for Parallel Interfaces Intel FPGA IP generation creates the appropriate generated clock
settings for the read strobe on the read path and the write strobe of the write path, according to their
strobe type (singled-ended, complementary, or differential) and their interface type (SDR or DDR) in the
following format:
• Clock name for read strobe—<pin_name>_IN.
• Clock name for the write path—<pin_name> for positive strobe.
• Clock name for the write path—<pin_name>_neg for negative strobe.
The set_false_path, set_input_delay and set_output_delay constraints are also generated to
ensure proper timing analysis of the PHY Lite for Parallel Interfaces Intel FPGA IP.
FPGA The PHY Lite for Parallel Interfaces Intel FPGA IP generation creates the clock settings for the user core
clock and the periphery clock in the following formats:
• user core clock—<variation_name>_usr_clk
• periphery clock— <variation_name>_phy_clk*
The user core clock is for user core logic and the periphery clock is the clock for the PHY Lite for Parallel
Interfaces Intel FPGA IP periphery hardware. With these clock settings, the Timing Analyzer analyzes the
timing of this IP interface transfer and within core transfer correctly.
6.5.6.4. Timing Closure Guidelines
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration
You can dynamically reconfigure the delay elements in the I/O to optimize process,
voltage, temperature variations by implementing a calibration algorithm that modifies
the input and output delays.
Related Information
6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
The Input Strobe Setup Delay Constraint and Input Strobe Hold Delay
Constraint parameters ensure that an input to the FPGA from the an external device
meets the internal FPGA setup and hold time requirements. The value of these
constraints are calculated from various timing parameters such as setup and hold
timing of the external device, board trace delay and clock skew.
The following figure shows the considerations required to determine the Input Strobe
Setup Delay Constraint and Input Strobe Hold Delay Constraint values. The
external device sends data and clock to the FPGA through interconnect on the board.
The FPGA uses the clock signal from the external device to latch input data to the
FPGA. The maximum and minimum values of the output clock TCO are values available
in the external device data sheet.
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Figure 164. Input Strobe Setup and Hold Delay Constraints Considerations
External FPGA
Device
Data Data input to FPGA
data_trace (max/min) PHY Lite
for Parallel
tCO
Interface
Input clock Input clock to FPGA Intel FPGA IP
Clock
PLL
The following is the derivation for Input Strobe Setup Delay Constraint and Input
Strobe Hold Delay Constraint:
Input strobe setup delay constraint = Maximum board skew + maximum TCO
Input strobe hold delay constraint = Minimum board skew + minimum TCO
maximum TCO = DQS to DQ skew (tDQSQ)
minimum TCO = Data hold skew (tQHS)
Figure 165. Input Data Cycle Timing Diagram

t CH
t CL
t QH tQHS
t DQSQ
Data valid window
DQ_skew_min DQ_skew_max DQ_skew_min DQ_skew_max
t CL = Clock cycle low

t CH = Clock cycle high
t DQSQ = DQS-DQ skew
t QH = DQ-DQS hold
tQHS = Data hold skew
The following is an example of Input Strobe Setup Delay Constraint and Input
• Maximum TCO = 0.6 ns
• Minimum TCO = -0.6 ns
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Input Strobe Setup Delay Constraint = 0.03 + 0.6= 0.63 ns
Input Strobe Hold Delay Constraint = -0.03 + (-0.6) = -0.63 ns
Insert these values into the Input Strobe Setup Delay Constraint and Input
tool.
Figure 166. Example of Input Strobe Delay Value from Timing Analyzer
iEXT=Input Strobe Delay Constraint + (0.5*Inter Symbol Interference of Read Channel)
6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
The Output Strobe Setup Delay Constraint and Output Strobe Hold Delay
Constraint ensure that the data output from the FPGA to the external device meets
the setup and hold requirements of the external device. The value of these constraints
are calculated from various timing parameters such as setup and hold timing of the
external device, board trace delay and clock skew.
The following figure shows the considerations required to determine the Output
Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint
values. These constraints are depending on the clock and data traces, and setup and
hold requirements of the external device. With system-centric delays, you can obtain
the setup and hold requirements, clock delay, and data trace delay values for the
external device through the device data sheet.
Figure 167. Output Strobe Setup and Hold Delay Constraints Considerations
FPGA External Device
PHY Lite for Parallel Data output to external device

Interface Intel FPGA IP Data Data
data_trace (max/min) (tSU ,t H)
Input clock PLL Output clock to external device

Clock Clock
The following is the derivation for Output Strobe Setup Delay Constraint and
Output Strobe Hold Delay Constraint:
Output strobe setup delay constraint = Maximum board skew + maximum tSU
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Output strobe hold delay constraint = Minimum board skew + minimum tH
maximum tSU = clock setup time
minimum tH = clock hold time
Figure 168. DDR Output Cycle Timing Diagram
t SUdq
DQ bit time
t SUdq
SU margin Hold margin
The following is an example of Output Strobe Setup Delay Constraint and Output
• Maximum tSU = 0.75 ns
• Minimum tH = 0.75 ns
Output Strobe Setup Delay Constraint = 0.03 + 0.75= 0.78 ns
Output Strobe Hold Delay Constraint = -0.03 - 0.75 = -0.78 ns
Insert these values into the Output Strobe Setup Delay Constraint and Output
tool.
Figure 169. Example of Output Strobe Delay Value from Timing Analyzer
oEXT= Output Strobe Setup delay constraint + (0.5 * Inter Symbol Interference of the Write Channel)
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6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
If the input data is not edge-aligned, use the following equation to calculate the new
Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint
values:
New Input Strobe Setup Delay Constraint Value = Clock to data skew - Input
New Input Strobe Hold Delay Constraint Value = Clock to data skew + Input
For example, if the memory speed is 800 MHz and the clock to data skew value is 0.1
with input data phase shift of 90°:
New Input Strobe Setup Delay Constraint value = 0.1-1.25*(90/360) =

-0.2125ns.
New Input Strobe Hold Delay Constraint value = 0.1 + 1.25*(90/360) = 0.4125ns
Important: Ensure that you make the changes in the Input Strobe Setup Delay Constraint and
Input Strobe Hold Delay Constraint parameters.
6.5.6.4.5. I/O Timing Violation
It can be difficult to achieve timing closure for I/O paths at high frequency. Use the
dynamic reconfiguration feature to calibrate the I/O path.
Related Information
For more information about using the dynamic reconfiguration feature to calibrate
the I/O path
6.5.6.4.6. Internal FPGA Path Timing Violation
If timing violations are reported at the internal FPGA paths (such as

<instance_name>_usr_clk or <instance_name>_phy_clk_*), consider the
following guidelines:
If setup time violation is reported, lower the clock rate of the user logic from full-rate
to half-rate, or from half-rate to quarter-rate. This reduces the frequency requirement
of the IP core-to-core data transfer.
If hold time violation is observed, you may increase hold uncertainty value to equal or
higher than the violation amount in the .sdc file. This will provide a more stringent
constraint during design fitting. Following is an example to increase the hold
uncertainty.
If {$::quartus(nameofexecutable) != “quartus_sta”}{
set_clock_uncertainty -from [<instance_name>_phy_clk_*] -to

[<instance_name>_phy_clk_*] -hold 0.3 -add
set_clock_uncertainty -from [<instance_name>_usr_clk] -to

[<instance_name>_usr_clk] -hold 0.3 -add
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However, increasing the hold uncertainty value may cause setup timing violation at
slow corner.
6.6. Design Example

The PHY Lite for Parallel Interfaces Intel FPGA IP is able to generate a design example
that matches the same configuration chosen for the IP. The design example is a simple
design that does not target any specific application; however you can use the design
example as a reference on how to instantiate the IP and what behavior to expect in a
simulation.
not edit the files.

reside.
Intel FPGA IP:
• Variant without dynamic reconfiguration design example
• Variant with dynamic reconfiguration design example
Dynamic Reconfiguration OFF ed_synth.qsys (synthesis Consists of configurable PHY Lite for
instance.
ed_sim.qsys (simulation Consists of sim_ctrl, agent, addr/cmd

only) and PHY Lite for Parallel Interfaces
Intel FPGA IP instances.
Perform read and write transaction
verification.
ON ed_synth.qsys (synthesis Consists of IOAUX and PHY Lite for

instances.
You need to instantiate NIOS and
AVL_Controller manually or create
user logic to perform address
translation.
phylite_debug_kit.qsys Consists of NIOS, AVL_Controller, API

(synthesis only) functions, IOAUX and PHY Lite for
Parallel Interfaces Intel FPGA IP
instances.
continued...
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A recommended example design to

perform dynamic reconfiguration.
This design example does not
support simulation.
ed_sim.qsys (simulation Consists of sim_ctrl, agent, addr/

only) cmd, cfg_ctrl, avl_ctrl and PHY Lite
core instances.
This design example demonstrates
dynamic reconfiguration and uses
FSM to perform calibration.
When the Enable dynamic reconfiguration option is not selected, Quartus Prime
software generates a design example of PHY Lite for Parallel Interfaces Intel FPGA IP
without a dynamic reconfiguration module.
This design example consists of simulation and synthesis design files.
6.6.1.1.1. Generating the Hardware Design Example
The make_qii_design.tcl generates a synthesizable hardware design example

along with a Quartus project, ready for compilation.
generation:

can open and compile this project with the Quartus Prime software.
The make_sim_design.tcl generates a simulation design example along with tool-

specific scripts to compile and elaborate the necessary files.
simulation tools. Each subdirectory contains the specific scripts to run simulation with
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connectivity for your IP configuration. Functionally, the simulation iterates over each
group in your configured IP and performs basic reads/writes to an associated agent
(one per group) in the testbench. A simple one group PHY Lite for Parallel Interfaces
Intel FPGA IP instantiation in the testbench is used for basic address and command
outputs to the agent. A side bus between the sim_ctrl and the agents is used to
check that the reads and writes are valid.

Side read/write data in DUT)
DRAM clock
Core clock Read/Write
PHY Lite DRAM clock
command ADDR/CMD Write command
Read command Latency Delays
Core clock
PHY Lite DUT
Read/Write
enable data
data strobe DRAM clock

Example Design, Quartus Prime software generates two design examples:
• Dynamic reconfiguration with debug kit design example.
• Dynamic reconfiguration with configuration control module.
6.6.1.2.1. Dynamic Reconfiguration with Debug Kit
This design example is a simulation design example that is capable to perform

dynamic calibration for PHY Lite for Parallel Interfaces Intel FPGA IP in Arria 10 and
Cyclone 10 GX devices.
The design example includes:

• A fully configurable PHY Lite for Parallel Interfaces Intel FPGA IP
• An Avalon controller to perform address translation
• A Nios V processor to perform dynamic calibration for PHY Lite for Parallel
• A set of application program interface (API) to configure delay chains for PHY Lite
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Figure 171. Dynamic Reconfiguration with Debug Kit Design Example
NIOS V AVL_CTRL PHY Lite for Parallel Interfaces DUT
Avalon
Avalon Controller Bus
Controller Bus
Table 148. Dynamic Reconfiguration with Debug Kit Design Example Generated Files
The example design folders are named differently in Arria 10 and Cyclone 10 GX devices.
• For Arria 10, the example design folder is named as phylite_0_example design.
• For Cyclone 10 GX, the example design folder is named as phylite_c10gx_0_example_design.
Example Design Files Description
<example_design_folder>/readme.txt This file provide simple instructions to generate and use the
example design.
<example_design_folder>/hello_world.c This is the main test program.
<example_design_folder>/ This is the system design file.

phylite_debug_kit.qsys
<example_design_folder>/ This file contains the set of APIs use in the test program.
phylite_dynamic_reconfigurations.c
<example_design_folder>/ This is the header file for the APIs.

phylite_dynamic_reconfiguration.h
<example_design_folder>/ This is an interconnect module between PHY Lite for Parallel

phylite_niosii_bridge.v Interfaces Intel FPGA IP and Nios V processor.
<example_design_folder>/
phylite_niosii_bridge_hw.tcl
<example_design_folder>/issp.tcl This is the In-System Source and Probes module. Use this
file to reset the system and to probe the status of the
interface_locked signal and dynamic calibration done
status from Nios II processor.
Table 149. API Functions in Dynamic Reconfiguration Debug Kit Design Example
API Function Argument Return Value Description
hw_get_num_groups ID Integer Read from

AVL_CTRL_REG_NUM_GROUPS register
for the specified ID.
hw_get_group_info ID, GROUP_NUM {16'h0000, Read from AVL_CTRL_REG_GROUP_

num_lanes[7:0], INFO register for the specified ID and
num_pins[7:0]} group number.
The return values are the number of
lanes and number of pins available for
the specified ID and group number.
hw_get_num_lanes ID, GROUP_NUM Integer Read from the AVL_CTRL_REG_GROUP_

INFO register for the specified ID and
group number.
lanes available for the specified ID and
group number.
continued...
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hw_get_num_pins ID, GROUP_NUM Integer Read from the AVL_CTRL_REG_GROUP_

INFO register for the specified ID and
group number.
pins available for the specified ID and
group number.
hw_get_input_delay ID, GROUP_NUM, Integer Read from the AVL_CTRL_REG_IDELAY

PIN_NUM, CSR register for the specified ID, group
number, and pin ID.
Specified CSR to:
• 0 to read from Avalon Controller
register
• 1 to read from CSR register
hw_get_output_delay ID, GROUP_NUM, Integer Read from the AVL_CTRL_REG_ODELAY

PIN_NUM, CSR register for the specified ID, group
number and pin number.
Specified CSR to:
register
hw_get_strobe_input_delay ID, GROUP_NUM, Integer Read from the

PIN_NUM, CSR AVL_CTRL_REG_DQS_DELAY delay
register for the specified ID, group
Specified CSR to:
register
hw_get_strobe_enable_delay ID, GROUP_NUM, Integer Read from the

PIN_NUM, CSR AVL_CTRL_REG_DQS_EN_DELAY
Specified CSR to:
register
hw_get_strobe_enable_phase ID, GROUP_NUM, Integer Read from the

PIN_NUM, CSR AVL_CTRL_REG_DQS_EN_PHASE_SHIFT
Specified CSR to:
register
hw_get_read_valid_enable_de ID, GROUP_NUM, Integer Read from the

lay PIN_NUM, CSR AVL_CTRL_REG_RD_VALID_DELAY
Specified CSR to:
register
hw_set_input_delay ID, GROUP_NUM, — Write to AVL_CTRL_REG_IDELAY register

PIN_NUM, input for the specified ID, group number and
delay value (integer) pin number.
continued...
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Refer to the Control Registers

Description topic for valid value range.
hw_set_output_delay ID, GROUP_NUM, — Write to AVL_CTRL_REG_ODELAY

PIN_NUM, output register for the specified ID, group
delay value (integer) number and pin number.
hw_set_strobe_input_delay ID, GROUP_NUM, — Write to AVL_CTRL_REG_DQS_DELAY

PIN_NUM, strobe register for the specified ID, group
input delay value number and pin number.
(integer) Refer to the Control Registers
hw_set_strobe_enable_delay ID, GROUP_NUM, — Write to

PIN_NUM, strobe AVL_CTRL_REG_DQS_EN_DELAY
enable delay value register for the specified ID, group
(integer) number and pin number.
hw_set_strobe_enable_phase ID, GROUP_NUM, — Write to

PIN_NUM, strobe AVL_CTRL_REG_DQS_EN_PHASE_SHIFT
enable phase value register for the specified ID, group
hw_set_read_valid_enable_de ID, GROUP_NUM, — Write to

lay PIN_NUM, read valid AVL_CTRL_REG_RD_VALID_DELAY
enable delay value register for the specified ID, group
Related Information
Control Registers Description on page 219
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Avalon Controller
The example design provides an Avalon controller to simplify the access to the
dynamic reconfiguration registers of an interface. The Avalon controller is useful when
there are multiple groups or instantiation of the PHY Lite for Parallel Interfaces Intel
FPGA IP. A single controller can support multiple interfaces in an I/O column.
Figure 172. Avalon Controller

Avalon Memory-Mapped
Avalon Memory-Mapped Interface Output
Interface Input (to PHY Lite
(from user logic) instance daisy chain)
Avalon Controller
The input interface is as follows:
avl_in_address[31:0] =
{8'h00,interface_id[3:0],grp[4:0],pin[5:0],csr[0],register[7:0]}
Note: There is no look-up stage here. The Avalon controller automatically looks up and
caches all the necessary data.
Table 150. Avalon Controller Registers

This table lists the available registers in the Avalon controller. For more information, refer to the Control
Registers Description topic.
Register Register Name Pin Csr[0] Register Data on Description

[7:0] [5:0] Access avl_read
Type data /
writedat
a
8'h00 AVL_CTRL_REG_NUM_GROUPS 0 0: Access to Avalon {24'h000 Number of groups

Avalon register: 000,num within an interface.
register. RO _grps[7:
CSR 0]}
register:
N/A
8'h01 AVL_CTRL_REG_GROUP_INFO 0 0: Access to Avalon {16'h000 Number of pins within

Avalon register: 0,num_la a group.
register. RO nes[7:0],
CSR num_pin
register: s[7:0]}
N/A
8'h02 AVL_CTRL_REG_IDELAY 0-47 0: Access to Avalon {23'h000 Pin input delay. Use
Avalon register: 000,dq_d this register to set pin
register. RW elay[8:0] PVT compensated
CSR } input delay.
register:
N/A
8'h03 AVL_CTRL_REG_ODELAY 0-47 0: Access to Avalon {19'h000 Pin output delay. Use
Avalon register: 00,outpu this register to read
register. RW t_delay[1 and set the pin output
2:0]} delay.
continued...
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Register Register Name Pin Csr[0] Register Data on Description

[7:0] [5:0] Access avl_read
Type data /
writedat
a
1: Access to CSR
CSR register:
register. RO
Only read
operation is
allowed.
8'h04 AVL_CTRL_REG_DQS_DELAY 0: DQS 0: Access to Avalon {22'h000 Strobe input delay of

A Avalon register: 000,dqs_ a pin. Use this
1: DQS register. RW delay[9: register to set the
B CSR 0]} strobe PVT
(23) register: compensated input
N/A delay.
8'h05 AVL_CTRL_REG_DQS_EN_DELAY 0 0: Access to Avalon {26'h000 Strobe enable input

Avalon register: 0000,dqs delay of a pin. Use
register. RW _en_dela this register to set the
1: Access to CSR y[5:0]} strobe enable delay.
CSR register:
register. RO
Only read
operation is
allowed.
8'h06 AVL_CTRL_REG_DQS_EN_PHASE_SH 0: DQS 0: Access to Avalon {19'h000 Strobe enable input

IFT A Avalon register: 00,phas phase of a pin. Use
1: DQS register. RW e[12:0]} this register to set the
B 1: Access to CSR strobe enable phase.
(23) CSR register:
register. RO
Only read
operation is
allowed.
8'h07 AVL_CTRL_REG_RD_VALID_DELAY 0 0: Access to Avalon {25'h000 Read val to set the

Avalon register: 0000,rd_ read valid delay.
register. RW vld_dela
1: Access to CSR y[6:0]}
CSR register:
register. RO
Only read
operation is
allowed.
Note: The example Avalon controller does not currently support VREF reconfiguration.
Related Information
• Control Registers Description on page 219
Example of Accessing Dynamic Reconfiguration Control Registers using Avalon Controller
This example shows the steps to access the dynamic reconfiguration control registers
using Avalon controller with the following PHY Lite for Parallel Interfaces Intel FPGA IP
settings:
(23) Strobe logic B is only used by the negative pin of complementary strobes
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• Number of groups: 1. The group index is automatically set to 0x00.

• Interface ID: 0x04
• Pin width: 5
• Strobe configuration: Differential
Below is the Avalon address value to read AVL_CTRL_REG_DQS_DELAY Avalon

register (strobe pin delay) at offset 0x04:
Note: The PHY Lite for Parallel Interfaces Intel FPGA IP fixes the strobe pin as pin[0].
avl_in_address[31:0] = {8'h00,0x04,0x00,0x00,0x00,0x04}
Below is the Avalon address value to read AVL_CTRL_REG_IDELAY Avalon register

(input data pin) at offset 0x02 for data pin 4. The pin number for data pin 4 is 0x06:
avl_in_address[31:0] = {8'h00,0x04,0x00,0x06,0x00,0x02}
Generating the Dynamic Reconfiguration with Debug Kit Design Example

1. In Quartus Prime, select File ➤ New Project Wizard to create a new project
directory and specify phylite_debug_kit as the project name.
2. Select device and instantiate PHY Lite for Parallel Interfaces Intel FPGA IP and turn
on the Use dynamic reconfiguration option.
3. Click Generate Example Design.
4. In your example design directory, open the phylite_debug_kit.qsys file and
click Generate HDL to generate the .qsys design example files.
5. In Quartus Prime, right click on the design example project and select Settings.
6. In Files tab, browse to the <generated design example folder/
phylite_debug_kit> and add in phylite_debug_kit.qip file into your
project.
7. Select Start Compilation to compile the design example project.
8. In Quartus Prime, select Tools ➤ Nios II Software Build Tool for Eclipse.
Create a new workspace when prompted.
9. In Nios II - Eclipse software, select File ➤ New ➤ Nios II Application and BSP
from Template.
10. In the Nios II Application and BSP from Template window, select
phylite_debug_kit_sopcinfo file in SOPC Information File name
parameter to load the CPU settings.
11. Specify a project name in the Project name parameter.
12. Select Hello World for the Project Template.
13. Click Finish to generate the project.
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14. Copy hello_world.c, phylite_dynamic_reconfiguration.c, and

phylite_dynamic_reconfiguration.h files from the generated example
design folder into your Eclipse project folder. You can refresh the Nios II Eclipse
window by pressing F5 to make sure these files are added into your Eclipse
project.
15. In the Nios II Eclipse window, click Project ➤ Build Project to generate .elf
file.
16. Run the following command in Nios II Command Shell to convert the .elf file
into .hex.
elf2hex --input=<elf_filename>.elf --base=0x40000 --end=0x7ffff --width=32 --

output=phylite_debug_kit_inst_mem.hex
17. Copy and add the phylite_debug_kit_inst_mem.hex file into the ed_synth
project folder.
18. Add the following command in the ed_synth.qsf to include the
phylite_debug_kit_inst_mem.hex in your project compilation.
set_global_assignment -name MISC_FILE
phylite_debug_kit_inst_mem.hex
19. Compile the ed_synth project file to generate .sof file to run the example
design on your hardware.
Note: For information about using Nios V, contact Intel Premier Support and quote
#15015694334.
Running the Dynamic Reconfiguration with Debug Kit Design Example

1. Download the phylite_debug_kit.sof file into the FPGA.
2. From the Quartus installation directory, double click on the Nios II Command
Shell.bat to launch the Intel Nios II command shell (command shell A). Repeat the
same step to launch a second command shell (command shell B).
3. In command shell B, use the following command to run Nios II terminal
application for result printouts.
nios2-terminal --cable=<jtag_cable_num>
4. Use the following command in command shell A to reset the system and start the
dynamic reconfiguration application.
quartus_stp -t issp.tcl phylite_debug_kit.qpf
Note: For information about using Nios V, contact Intel Premier Support and quote
#15015694334.
6.6.1.2.2. Dynamic Reconfiguration Using Finite State Machine
This design example provides you a synthesizable system capable to perform dynamic
calibration for PHY Lite for Parallel Interfaces Intel FPGA IP core in Arria 10 and
Cyclone 10 GX devices.
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Features
• Perform dynamic reconfiguration using Avalon controller

• Read and write transactions monitoring
• Delay values monitoring
Software Requirements
• Quartus Prime software
• Active-HDL, ModelSim - Intel FPGA Edition, or VCS Simulator
Functional Description
This design example introduces the cfg_ctrl and avl_ctrl blocks, which work with
the sim_ctrl module to demonstrate the basic functionality of the PHY Lite for
Parallel Interfaces Intel FPGA IPs Avalon memory-mapped interface based
reconfiguration. The agent is also modified to insert delays on the data and clocks,
which the new modules will compensate for.
Note: The cfg_ctrl module performs a simplistic reconfiguration of the interface that stops
at the first working delay values. The design example only support simulation. A
robust calibration algorithm should sweep over the entire valid range of delays to
choose the correct value for the application.
Figure 173. Dynamic Reconfiguration Using Finite State Machine Design Example
This figure shows a high-level view of the simulation design example with one group.

in DUT)
Side read/write data
ref_clk_gen ref_clk reset_gen
DRAM clock PHY Lite ADDR/CMD reset_n

ref_clk DRAM clock
Core clock
Read/Write
Write command
command Read command Latency Delays
ref_clk
Core clock Driver PHY Lite DUT reset_n
Core clock
Lock Read/Write
enable Data DRAM clock
Data
strobe
Data Core clock DRAM clock
Strobe
Lock
Reconfiguration
Flow Control
Dynamic Reconfiguration Only
cfg_ctrl Avalon avl_ctrl Avalon Memory-mapped Bus

Memoy-mapped
Bus
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Table 151. Design Components Description

ref_clk_gen Generates clock to reset_gen, PHY Lite for Parallel Interfaces Intel FPGA IP
ADDR/CMD (ref_clk), and PHY Lite for Parallel Interfaces Intel FPGA IP DUT
(ref_clk) blocks.
reset_gen Generates reset to PHY Lite for Parallel Interfaces Intel FPGA IP ADDR/CMD and
PHY Lite for Parallel Interfaces Intel FPGA IP DUT blocks.
sim_ctrl • Generates read/write commands to PHY Lite for Parallel Interfaces Intel FPGA
IP ADDR/CMD block.
• Generates side read/write commands and data to Agent block.
• Generates strobe and data to Driver block.
Driver Generates strobe and data for each group and to PHY Lite for Parallel Interfaces
Intel FPGA IPDUT block.
PHY Lite for Parallel Interfaces Intel Passing read/write commands and command clock from sim_ctrl to Agent.
FPGA IP ADDR/CMD
Agent FIFO to store data from PHY Lite for Parallel Interfaces Intel FPGA IP DUT and
side read/write data from sim_ctrl block.
cfg_ctrl This is configuration control block which performs read and write delay calibration
before test begin.
The calibration results is passed to the PHY Lite for Parallel Interfaces Intel FPGA
IP DUT through Avalon Controller.
Contains 4 FSMs:
1. Main FSM – cfg_ctrl state
2. Write Strobe FSM – Calibration state for Output Strobe
3. Read Strobe FSM – Calibration state for Input Strobe
4. Read Enable FSM – Calibration state for Strobe Enable and Input Data
avl_ctrl The Avalon controller is used to perform address translation to store delay
settings from the calibration done by cfg_ctrl block.
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Figure 174. Design Example Functional Flow

Start
Reset cfg_ctrl module
Dynamically reconfigure
data group's settings
Function name: reconfigure_grp
Pin Type?
Output Input
Bidirectional
Dynamically reconfigure write strobe setting Dynamically reconfigure write strobe setting
Function name: reconfigure_grp_write Function name: reconfigure_grp_write
a) Read from Pin Output Delay CSR register a) Read from Pin Output Delay CSR register
b) Write to DUT and read back b) Write to DUT and read back
c) If fail, update Pin Output Delay c) If fail, update Pin Output Delay Avalon register
Avalon register d) Repeat step b) and c) until pass
d) Repeat step b) and c) until pass e) Done
e) Done
Write data to DUT

Write data to DUT and read back to verify data is correct
Dynamically reconfigure read strobe setting

Simulation ends
Function name: reconfigure_grp_read
a) Read from Strobe PVT Compensated Input Delay
CSR register
c) If fail, update Strobe PVT Compensated Input Delay
Avalon register
d) Repeat step b) and c) until pass
e) Done
Dynamically reconfigure read enable and

input data settings
Function name: reconfigure_grp_read_en_and_data
a) Read from Strobe Enable Phase CSR register
c) If data[0] is mismatched,
update Strobe Enable Phase Avalon register
d) Repeat step b) and c) until data[0] is matched
e) Get number of data pin
f) Write to Agent and read back
g) If fail, update Pin PVT Compensated Input Delay
Avalon register
h) Repeat f) and g) until pass
i) Done
Write data to Agent

Simulation ends
Related Information
Avalon Controller on page 261
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Generating the Dynamic Reconfiguration with Configuration Control Module Design

Example
1. In Quartus Prime software, instantiate PHY Lite for Parallel Interfaces Intel FPGA
IP core.
2. Customize parameter settings per your requirement and turn on the Use
dynamic reconfiguration option.
3. Click Generate Example Design. Specify a directory name to generate the
design example.
4. To generate Verilog or mixed-language simulation files, go to the design example
directory and run the following script in Nios V Command Shell.
5. To generate VHDL simulation files, go to the design example directory and run the
following script in Nios V Command Shell.
Running the Dynamic Reconfiguration with Configuration Control Design Example

1. Change the working directory to <Example Design>\sim\ed_sim\sim
\<Simulator>.
2. Run the simulation script for the simulator of your choice. Refer to the table below.
Modelsim <Example Design>\sim\ed_sim a. do msim_setup.tcl

\sim\mentor b. ld_debug
waveform window.
d. run -all
VCS <Example Design>\sim\ed_sim a. sh vcs_setup.sh

\sim\synopsys\vcs
VCSMX <Example Design>\sim\ed_sim a. sh vcsmx_setup.sh

\sim\synopsys\vcsmx
Aldec Example Design\sim\ed_sim\sim a. do rivierapro_setup.tcl

\aldec b. ld_debug
waveform window.
d. run -all
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Figure 175. Sample Simulation Output
6.7. Application Specific Design Example

This design example demonstrates the PHY Lite for Parallel Interfaces Intel FPGA IP
implementation for a NAND Flash design in Arria 10 devices.
The following figure shows the RTL view of the design example.
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Figure 176. RTL Viewer for a NAND Flash Simple Design Based on the PHY Lite for Parallel
Related Information
PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP Core NAND FLASH Design
Example
6.7.1. Implementation using the PHY Lite for Parallel Interfaces Intel
FPGA IP
You can configure the PHY Lite for Parallel Interfaces Intel FPGA IP to support multiple
groups (maximum 48 I/O pins each).
The following lists the possible implementations:

• Instantiates one PHY Lite for Parallel Interfaces Intel FPGA IP with two groups
— Bidirectional type for DQ and DQS signals
— Output type for Addr/Cmd signals
Note: Each group in the PHY Lite for Parallel Interfaces Intel FPGA IP can have 48 I/Os, and
the IP supports up to 18 groups.
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Figure 177. General Tab Settings
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Figure 178. Group 0 Settings (Bidirectional Type for DQ and DQS)
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Figure 179. Group 1 Settings (Output Type for Addr/Cmd)
Related Information
PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP Core NAND FLASH Design
Example
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Send Feedback
7. PHY Lite for Parallel Interfaces Intel FPGA IP User

Guide Document Archives
For the latest and previous versions of this user guide, refer to PHY Lite for Parallel
Interfaces Intel FPGA IP User Guide. If an IP or software version is not listed, the user
guide for the previous IP or software version applies.
IP versions are the same as the Quartus Prime Design Suite software versions up to
v19.1. From Quartus Prime Design Suite software version 19.2 or later, IP cores have
a new IP versioning scheme.
683716 | 2024.04.01
Send Feedback
8. Document Revision History for the PHY Lite for Parallel

Interfaces Intel FPGA IP User Guide
Document Version Quartus Prime Changes
Version
2024.04.01 24.1 • Added the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 E-
Series Devices chapter.
• Updated the sub-bank in the Agilex 7 F-Series and I-Series I/O Sub-
bank Interconnects topic with additional diagrams.
• Added a note in the Guidelines: Group Pin Placement topic of the PHY
Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-
Series Devices chapter.
2024.01.12 23.4 • Updated the Allowed values for read_enable_offset based on RcvEn
coarde delay table.
• Updated parameters in the Address Register Map table.
• Added statements in the Dynamic Reconfigurable Delays topic about
setting the InternalClocksOn bit and performing train reset, and a link
to the Input Path Signals table.
• Added a statement in the Guidelines: Group Pin Placement topic under
the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series
and I-Series Devices chapter about potential design failure.
• Added a Worst Case Losses table under the I/O Timing topic of the PHY
Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 M-Series Devices
chapter.
• Added examples about quarter rate and half rate modes in the Agilex 7
F-Series and I-Series Input DQS/Strobe Tree topic.
• Updated the Pin Placement Restrictions section to add a note about
avoiding overlapping of base addresses and information about ODT
Rotation.
• Added a note about avoiding overlapping of base addresses in the
Parameter Settings topic.
• Updated the IP names throughout the document to PHY Lite for Parallel
• Updated the figure showing the M-Series FPGA I/O bank structure.
2023.08.02 23.2 • Removed the note about restricted support for M-Series FPGAs.
• Added rzq signal in the Clock and Reset Interface Signals table for the
PHY Lite for Parallel Interfaces Agilex 7 FPGA IP for M-Series.
• Updated the RZQ value for 1.2-V HSTL in the I/O Standards and
Termination Values for Agilex 7 M-Series Devices table.
continued...
8. Document Revision History for the PHY Lite for Parallel Interfaces Intel FPGA IP User Guide
683716 | 2024.04.01

Version
• Added the following sub-bank ordering diagrams:

— Sub-bank Ordering with ID in Top I/O Row in Agilex 7 AGF022 and
— Sub-bank Ordering with ID in Bottom I/O Row in Agilex 7 AGF022
and AGF027 Devices, Package R31C
— Sub-bank Ordering with ID in Top I/O Row in Agilex 7 AGI022 and
— Sub-bank Ordering with ID in Bottom I/O Row in Agilex 7 AGI022
and AGI027 Devices, Package R29A
— Sub-bank Ordering with ID in Top I/O Row in Agilex 7 AGI027
and AGI027 Devices, Package R31A
and AGI027 Devices, Package R31B
• Updated quarter core clock rate and added half and full core clock rates
in the following tables for PHY Lite for Parallel Interfaces Agilex 7 FPGA
IP for F-Series and I-Series.
— PHY Lite for Parallel Interfaces Agilex 7 FPGA IP for F-Series and I-
Series Supported Interface Frequency
— Maximum Write Latency
• Updated the description in the Dynamic Reconfiguration Guidelines
section.
• Updated the Strobe Enable Phase [9:0] incremental delay description in
the Control Register Bit Description for PHY Lite for Parallel Interfaces
Agilex 7 FPGA IP for F-Series and I-Series.
• Updated the description, dqs_clean Timing Diagram, and Adding Extra
Dummy Pulses to Return PHY to Normal State diagram in the Strobe
Enable Window Calibration sections for the following IPs:
— PHY Lite for Parallel Interfaces Agilex 7 FPGA IP for F-Series and I-
Series
— PHY Lite for Parallel Interfaces Stratix 10 FPGA IP
— PHY Lite for Parallel Interfaces Arria 10 FPGA IP and PHY Lite for
Parallel Interfaces Cyclone 10 GX FPGA IP
• Made editorial updates throughout the document.
2023.04.10 23.1 • Added information about Agilex 7 (F-Series, I-Series, and M-Series) in
Device Family Support section.
• Added PHY Lite for Parallel Interfaces Agilex 7 FPGA IP for M-Series
section.
• Updated the PHY Lite for Parallel Interfaces Agilex 7 FPGA IP for F-
Series and I-Series section.
— Added link to External Memory Interfaces Agilex 7 FPGA IP User
Guide.
— Added information about PHY Lite for Parallel Interfaces instances
for Agilex 7 FPGA IP for F-Series and I-Series in I/O Standards.
— Updated the range in Input DQ/DQS Delay Chains Maximum Values
section.
continued...
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Version
2022.06.21 22.2 • Removed Output Path Data Alignment and Input Path Data Alignment
sections.
• Removed information about PHY Lite for Parallel Interfaces IPs and the
External Memory Interface IPs from Reconfiguration Features and
Register Addressing section.
• Added KDB link in Generate the Simulation Design Example section.
• Added information to use +define
+EMIF_DISABLE_CAL_OPTIMIZATIONS in Generate the Simulation
Design Example section.
2021.12.13 21.4 • Updated the About the PHY Lite for Parallel Interfaces IP section.
• Updated the Intel Agilex I/O Sub-bank Interconnects section:
— Updated the figure Sub-bank Ordering with ID in Top I/O Row in
Intel Agilex AGF012 and AGF014, Package R24B.
— Updated the figure Sub-bank Ordering with ID in Bottom I/O Row in
Intel Agilex AGF012 and AGF014, Package R24B.
— Updated the figure Sub-bank Ordering with ID in Top I/O Row in
Intel Agilex AGF014, Package R24C.
— Updated the figure Sub-bank Ordering with ID in Bottom I/O Row in
Intel Agilex AGF014, Package R24C.
• Updated the Intel Agilex Input DQS/Strobe Tree section:
— Added the figure Pin Placement Example.
— Updated the column header of the Pins Usable as Read Capture
Clock / Strobe Pair table.
• Updated the PHY Lite for Parallel Interfaces Intel Agilex FPGA IP Top
Level Interfaces section.
• Updated the Dynamic Reconfiguration section:
— Updated the Input DQ/DQS Delay Chains Maximum Values section.
• Added a footnote on Values parameter in PHY Lite for Parallel Interfaces
IP Parameter Settings table recommending to select based on the
design, ideally through analog simulation using FPGA IBIS models and
specific board.
• Added a note on choosing the VREF range for the design using analog
simulation in the Input Buffer Reference Voltage (VREF) and Input
Buffer Reference Voltage (VREF) sections.
• Added the figure High-Level View of the Synthesis Design Example with
One Group.
• Added related information in Calibration Guidelines section.
continued...
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Version
2021.09.01 21.1 Removed unsupported VREF modes from the VREF_MODE Description table
for the PHY Lite for Parallel Interfaces Agilex 7 FPGA IP: VCCIO_45,
VCCIO_50, VCCIO_55, VCCIO_65, VCCIO_70, VCCIO_75.
2021.07.16 21.1 • Updated the figure showing the I/O bank structure to improve clarity
and to remove 3 V I/O.
• Updated the PHY Lite for Parallel Interfaces Agilex 7 FPGA IP v21.0.0 as
follows:
— Restructured the About the PHY Lite for Parallel Interfaces IP
section.
— Updated the column header of the Pins Usable as Read Capture
Clock / Strobe Pair table.
— Updated the Output Path section.
— Added description for the Example Output for Quarter Rate DDR
diagram.
— Updated the Dynamic Reconfiguration Guidelines section.
— Updated the Strobe Enable Window Calibration section.
— Added the Input DQ/DQS Delay Chains Maximum Values section.
— Added the I/O Timing section.
— Updated the values for Capture strobe phase shift and Strobe
configuration in the PHY Lite for Parallel Interfaces IP Parameter
Settings table.
— Updated the Input Buffer Reference Voltage (VREF) section.
• Updated the VREF range selection via QSF for POD 1.2 V
assignment command.
• Added support for Calibrated VREF via dynamic reconfiguration.
• Added DDR4_CAL and DDR4_CAL_RANGE2 VREF modes in the
VREF_MODE Description table.
• Updated the PHY Lite for Parallel Interfaces Stratix 10 FPGA IP as
follows:
— Updated the Strobe Enable Window Calibration section.
— Updated the Dynamic Reconfiguration section.
• Updated the Strobe Enable Window Calibration section for the PHY Lite
for Parallel Interfaces Arria 10 FPGA IP and PHY Lite for Parallel
Interfaces Cyclone 10 GX FPGA IP.
• Removed references to the NCSim simulator.
• Updated the topic listing the document archives to correct the topic title
and the titles of the archived documents from Quartus Prime versions
18.0 through 20.3.
2021.02.04 20.4 Updated the PHY Lite for Parallel Interfaces Agilex 7 FPGA IP v20.3.0 as
follows:
• Updated the I/O resource and added support for dynamically
reconfigurable delay chains using Avalon memory-mapped interface for
Agilex 7 devices in the Features section.
• Updated the Agilex 7 I/O Sub-bank Interconnects section.
— Stated that each sub-bank is labeled with ID number to facilitate pin
placement.
— Updated figure titles and added ID numbers in the diagrams.
• Updated the Pins Usable as Read Capture Clock / Strobe Pair table.
• Updated the maximum frequency for speed grade –2 and –3 in the PHY
Lite for Parallel Interfaces Agilex 7 FPGA IP Supported Interface
Frequency table.
• Added the Dynamic Reconfiguration section.
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Version
• Updated the PHY Lite for Parallel Interfaces IP Parameter Settings

table.
— Updated values for Clock rate of user logic, Use dynamic
reconfiguration, and Pin width.
— Added the Pin Placement section.
— Removed the Expose termination ports parameter.
— Removed the Group <x> Placement Settings section.
• Removed the Termination Signals and Manual Insertion of OCT Block
sections.
• Updated the steps to set RZQ pin locations in the RZQ_GROUP
Assignment section.
• Updated the Guidelines: Group Pin Placement section.
— Updated the guidelines for group pin placement.
— Updated the Pin Index Mapping table.
— Added guidelines and example for automatic and manual pin
placement.
— Removed the Example of Occupied Data Pins for a Single Group
Using Automatic Pin Placement and Example of Occupied Data Pins
for a Single Group Using Manual Pin Placement diagrams.
• Added command codes in the Reference Clock section.
• Added the Generate the Design Example section. Included Generate the
Simulation Design Example as a sub section.
Updated the Guidelines: Group Pin Placement sections for the following
IPs:
• PHY Lite for Parallel Interfaces Stratix 10 FPGA IP
• PHY Lite for Parallel Interfaces Arria 10 FPGA IP
• PHY Lite for Parallel Interfaces Cyclone 10 GX FPGA IP

Version
2020.11.13 20.3 • Updated the figure showing the I/O bank structure to add the pin
naming orientation.
• Repaired multiple broken links and descriptions throughout the
document.
2020.10.19 20.3 • Added information about PHY Lite for Parallel Interfaces Agilex 7 FPGA
IP v20.3.0 support in Agilex 7 devices.
• Restructured the user guide to separate the information into specific
devices.
2020.06.30 20.2 Updated the Stratix 10 I/O Bank Structure figure showing the I/O bank
structure:
• Added I/O bank structure for Stratix 10 GX 10M device.
• For I/O banks figure of other Stratix 10 devices:
— Marked only bank 3A as SDM shared LVDS I/O.
— Marked HPS shared LVDS I/Os.
— Added 3 V I/O banks 7A, 7B, and 7C.
279
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Document Version Quartus Prime IP Version Changes

Version
2020.02.24 19.3 19.1 • Added Why is the read data value incorrect for the
DQS input delay when using the Dynamic
Reconfiguration mode in the Arria 10 PHYLite IP?
KDB link to the Dynamic Reconfiguration topic.
• Editorial updates for the Output Path — Write
Latency 2 and Input Path ─ Read Latency 7 figures.
• Updated dqs_enable signals in the Input Path
figure to match signal names in Blocks in Data,
Strobe, and Read Enable Paths table.
• Removed redundant signal description for
avl_writedata in the Avalon Memory-Mapped
Master Interface Signals table.
• Rebranded Avalon-MM to Avalon Memory-Mapped
Interface.
2019.12.16 19.3 19.1 • Updated note and related information link on

using .sdc file in encrypted IOPLL Intel FPGA IP
instances in the Reference Clock topic.
2019.11.07 19.3 19.1 • Added the following topics:

— Release Information
— Timing Closure: Input Strobe Setup and Hold
Delay Constraints
— Timing Closure: Output Strobe Setup and Hold
Delay Constraints
• Added KDB link Why does the PHY Lite for Parallel
Interfaces Stratix 10 FPGA IP cannot be assigned to
Bank 3A or 3D when using the Stratix 10 1ST040*
device? to Functional Description chapter.
• Added KDB link Error(14566): The Fitter cannot
place 1 periphery component(s) due to conflicts
with existing constraints (1 PHYLITE_GROUP(s)). to
Constraining Multiple PHY Lite for Parallel Interfaces
to One I/O Bank chapter.
• Added KDB link Warning: Failed to find atom
information in IOPLL SDC: ERROR: Cannot access
ENUM_IOPLL_FEEDBACK data of the encrypted
atom node 111916. This operation involves an
encrypted atom node. Use the BOOL_ENCRYPTED
test to avoid such nodes and the error. to
Reference Clock topic.
2019.04.04 19.1 19.1 • Added Can the Arria 10 and Cyclone 10 GX I/O PLL
have a VCO frequency below the minimum value
shown in the device datasheets? KDB link in Clocks,
Clock Frequency Relationships, and Parameter
Settings sections.
2019.04.01 19.1 19.1 • Added new parameter Reference clock I/O

configuration in PHY Lite for Parallel Interfaces IP
Core Parameter Settings table.
• Removed information on manual assignment for
reference clock I/O standards in the I/O Standards
chapter.
2019.01.09 18.1 18.1 Added estimation time for a delay register value to
change in Reconfiguration Features and Register
Addressing.
continued...
280
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Version
2018.09.21 18.1 18.1 • Clarified the definition for full, half, and quarter
core clock rate in PHY Lite for Parallel Interfaces
Supported Interface Frequency tables.
• Added legend and updated Input Path figure to
show each path and distinguish internal and
external signals.
• Updated description for data, strobe, and read and
strobe enable paths in Blocks in Data, Strobe, and
Read and Strobe Enable Paths table.
• Updated read operation description in Read
Operation Sequence table.
• Updated Input Path Waveform, Output Path - Write
Latency 0, and Output Path - Write Latency 3
figures.
• Updated description in Input Path Signals table.
• Added a note to rdata_en signal in Input Path
Signals to describe when user should assert the
signal when using PHY Lite for Parallel Interfaces IP
as a receiver.
• Clarified that only when External Memory Interface
with Debug Component IP cores exists in the design
with PHY Lite for Parallel Interfaces, the First
PHYLite Instance in the Avalon Chain
parameter should be disabled.
• Added new parameter Fast simulation model in
PHY Lite for Parallel Interfaces table.
• Updated RZQ_GROUP Assignment topic with steps
to manually assign user defined RZQ pin location.
• Added the following topics:
— Example of Accessing Dynamic Reconfiguration
Control Registers using Parameter Table
— Example of Accessing Dynamic Reconfiguration
Control Registers using Avalon Controller
• Removed description on supported devices for
tables with information that supports all devices.
• Clarified that PHY Lite for Parallel Interfaces in Arria
10 and Cyclone 10 GX devices do not support
exposing additional output clocks if the VCO
frequency is lower than 600 MHz in PHY Lite for
Parallel Interfaces IP Core Parameter Settings table.
• Added pll_extra_clock[0..3] and
pll_locked signals in Clock and Reset Interface
Signals table.
• Updated Output Path and Input Path block
diagrams with parameters that impact the internal
modules.
2018.06.06 18.0 18.0 • Removed For Arria 10 and Cyclone 10 GX devices,

this value is for DQS output strobe. For Stratix 10
devices, this value is for both DQ and DQS output
strobe. note from Pin Output Delay feature in
Control Register Description table.
2018.05.07 18.0 18.0 • Changed VCCN voltage supply name to VCCIO.

• Renamed Addressing section to Reconfiguration
Features and Register Addressing.
• Added Control Register Addresses tables for Stratix
10, Arria 10, and Cyclone 10 GX devices.
• Added Control Registers Description table for
Stratix 10, Arria 10, and Cyclone 10 GX devices.
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Version
• Added How can the PHY Lite IP RZQ pin location be

assigned? Knowledge Base Link in On-Chip
Termination (OCT) section.
• Added First PHYLite Instance in the Avalon
Chain parameter to the PHY Lite for Parallel
Interfaces IP Core Parameter Settings table.
• Made Example Design Avalon Controller section as
a sub-section in Dynamic Reconfiguration with
Debug Kit Design Example.
• Updated Avalon Controller Registers table with
register descriptions.
• Renamed Pin Output Phase feature to Pin Output
Delay.
• Updated the minimum interface frequency
recommended for dynamic reconfiguration to 533
MHz in the PHY Lite for Parallel Interfaces IP Core
Parameter Settings table.
• Updated all IP names as per Intel rebranding.
Date Version Changes
November 2017 2017.11.30 • Added information about Intel FPGA PHYLite for Parallel Interfaces in Stratix
10 and Cyclone 10 GX devices.
• Added note to Reference Clock on page 246 about using cascaded PLL as a
reference clock in Arria 10 devices and a link to the KDB.
• Rebranded to Intel FPGA PHYLite for Parallel Interfaces IP core.
June 2017 2017.06.16 • Added a note for the I/O Column for Arria 10 Devices figure.
• Updated Top-Level Interface diagram.
• Updated OCT section.
• Updated Guidelines: Group Pin Placement section.
• Updated the reference clock source in the Reference Clock section.
• Added Reset section.
• Added a note on Report DDR function in
"<variation_name>_report_timing.tcl" section.
• Updated Altera PHYLite for Parallel Interfaces IP Core Parameter Settings
table.
— Removed Use core PLL reference clock connection parameter.
— Added description for outclk (Reserved) parameter.
— Updated OCT enable size values and description.
— Added new parameter: Expose termination ports.
• Updated the description for ref_clk and interface_locked signals in the
Clock and Reset Interface Signals table.
• Updated the description for data_in and data_io signals in Input Path
Signals table.
• Rebranded as Intel.
February 2017 2017.02.24 • Removed 30 and 40 Ohms termination values for SSTL-125, SSTL-135, and
SSTL-15 I/O standards.
• Added a footnote to I/O Standards table recommending to use I/O standards
SSTL-15 Class I, SSTL-15 Class II, SSTL-18 Class I, SSTL-18 Class II, 1.2V
HSTL Class I, 1.2V HSTL Class II, 1.5V HSTL Class I, 1.5V HSTL Class II,
1.8V HSTL Class I, and 1.8V HSTL Class II for interface frequency equal or
less than 533 MHz and if input termination required.
• Added a footnote to I/O Standards table recommending to use I/O standards
SSTL-12, SSTL-125, SSTL-135, and SSTL-15 for interface frequency more
than 533 MHz and if input termination required.
continued...
282
683716 | 2024.04.01
October 2016 2016.10.28 • Added OCT section.

• Clarified that output terminations can be calibrated and uncalibrated in I/O
Standards table.
• Added footnote to clarify that uncalibrated output terminations do not require
RZQ pin in I/O Standard table.
• Clarified ONFI device support is for synchronous mode only.
• Updated Altera PHYLite for Parallel Interfaces IP Core supported Interface
Frequency table.
• Clarified that reference clock using differential I/O standards support LVDS
input buffer only.
• Updated I/O standards table with Valid Input Termination values.
• Added new guidelines to Group Pin Placement section.
• Updated Avalon Address for following features in the Address Map table:
— Pin PVT Compensated Input Delay
— Strobe PVT compensated input delay
— Strobe enable phase
• Added Altera PHYLite NAND Flash design example in Application Specific
Design Example section.
• Removed IP Migration for Arria V, Cyclone V, and Stratix V section.
May 2016 2016.05.02 • Change External memory clock domain to Interface clock domain.
• Removed VCO Frequency Multiplication Factor table.
• Updated equation to calculate values for Input Strobe Setup Delay
Constraint and Input Strobe Hold Delay Constraint parameters.
• Updated Address Map table with values to enable Avalon address and CSR
address.
• Added a note to show the location of the Altera PHYLite for Parallel Interfaces
IP core in IP Catalog.
• Updated values for OCT enable size parameter.
• Added reference link to I/O Standards table in Data configuration
parameter description.
• Added VCO clock frequency parameter in Parameter Settings table.
• Updated Minimum Read Latency and Maximum Write Latency tables.
• Updated PHYLite_delay_calculations.xlsx file.
• Added issp.tcl file description in Dynamic Reconfiguration with Debug Kit
Design Example Generated Files table.
• Updated steps to generate Dynamic Reconfiguration with Debug Kit design
example.
• Added functional description, simulation steps and result to Dynamic
Reconfiguration with Configuration Control Module Design Example.
• Added Altera PHYLite for Parallel Interfaces IP Core Document Archives
section.
December 2015 2015.12.11 • Changed Input Path Waveform figure label from "Intrinsic output delay at
current in and out rates and frequency" to "Intrinsic input delay at current in
and out rates and frequency".
November 2015 2015.11.02 • Added Altera PHYLite for Parallel Interface IP core uses cases.
• Clarified the condition for reference clock restriction in Reference Clock
section.
• Added description for <variation_name>_parameter.tcl,
<variation_name>_report_timing.tcl, and
<variation_name>_report_parameter_core.tcl files into
Timing Constrains and Files section.
• Provided example timing constraint command for increasing hold time
uncertainty value.
• Added footnote to clarified functionality for DQS A and DQS B signals.
continued...
283
683716 | 2024.04.01
• Added new parameters in the Altera PHYLite for Parallel Interfaces IP Core
Parameter Settings table:
— Copy parameters from another group
— Group
— OCT enable size
— Inter Symbol Interference of the Read Channel
— Inter Symbol Interference of the Write Channel
— Group <x> Dynamic Reconfiguration Timing Settings
• Added new dynamic reconfiguration with debug kit hardware example design.
• Added Write Latencies table in Parameter Settings.
• Updated Read Latencies table.
• Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.12 • Updated Avalon Address R/W from 3'h2 to 3'h4 for all features in Address
Map table.
• Added new parameter Use core PLL reference clock connection and Data
configuration in Altera PHYLite for Parallel Interfaces IP Core Parameter
Settings table.
• Updated values in VCO Frequency Multiplication Factor table.
January 2015 2015.01.28 Updated related information link to Functional Description for External Memory
Interfaces in Arria 10 Devices.
December, 2014 2014.12.30 • Updated the name of the IP core from Altera PHYLite for Memory to Altera
PHYLite for Parallel Interfaces.
• Updated the maximum clock frequency from 800 MHz to 1333.333 MHz.
• Clarified that to achieve timing closure at 800 MHz and above, you must use
dynamic reconfiguration to calibrate the interface.
• Added data_out_n/data_io_n signals to the Output Path Signals table.
• Added data_in_n/data_io_n signals to the Input Path Signals table.
• Updated data_out/data_io and data_in/data_io signals in the Input
Path Signals and Output Path Signals tables.
• Updated Parameter Settings table to include Group <x> Timing Settings
information.
• Updated Timing section to include Input Strobe Setup Delay Constrain
and Input Strobe Hold Delay Constrain parameters information.
August, 2014 2014.08.18 • Renamed the term megafunction to IP core.

• Added information about output path data alignment, input path data
alignment, OCT, I/O standards, placement restrictions, timing, dynamic
reconfiguration.
• Added the PHYLite_delay_calculations.xlsx file.
• Replaced ALTERA_PHYLite_nand_flash_example_131a10.qar file with
nand_flash_example_14.0a10.qar file.
November, 2013 2013.11.29 Initial release.
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PHY Lite for Parallel Interfaces

Intel® FPGA IP User Guide

Online Version 683716

1. About the PHY Lite for Parallel Interfaces IP ................................................................. 5

4.4. I/O Standards....................................................................................................120

6.5.2. Reference Clock..................................................................................... 246

1. About the PHY Lite for Parallel Interfaces IP

In addition, this IP supports the Dynamic Reconfiguration feature, which enables

1.1. Device Family Support

2. PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex

2.1. Release Information

Quartus Prime Pro Version 24.1

Release Date 2024.04.01

2.2. Functional Description

Figure 1. Agilex 5 HSIO Bank Structure (Die Top View)

Top Index Sub-Bank Bottom Index Sub-Bank

Top I/O Bank Row

Bottom I/O Bank Row

2A 2B Top Index Bottom Index

HMC Clock Fabric HMC

Equation 1. Relationships Between Clock Domains

Core Clock Frequency = Interface Clock Frequency÷PHYLITE_IN_RATE

600-1250 4 1 600-1250 300-625 150-312.5

300-600 2 2 600-1200 300-600 150-300

150-300 1 4 600-1200 300-600 150-300

Note: • For the boundary frequencies of 300 MHz, PHYLITE_IN_RATE = 1 and

2.2.1.2. Output Path

Figure 4. Simplified Output Path

Pipeline Phase Shift

TX FIFO Phase Shift

Inherent Delay TxDqDelay

Pipeline Shift Register

Table 4. Internal Components of the Simplified Output Path

Pipeline Registers Represent pipeline stages in the output path.

TX FIFO Stores the data to be transmitted out.

Table 5. Types of Delay in Output Path

Table 6. Output Path Reconfigurable Delays

Feature Description Min Max

TxDqDelay[10:7] Integer number of VCO clock cycles 0 15

The following figure shows an example of TX data transfer in QR DDR. In this

Figure 5. Output Operation

Figure 6. Default Output Path Settings

2.2.1.3. Input Path

Figure 7. Simplified Input Path

Pipeline RcvEn Shift Register Phase Shift

Per Group read_enable_offset

Per Pin RxDqsNDelayPi/

Pipeline Registers Represent pipeline stages in the input path

2x RX FIFOs Perform 2:1 rate conversion on the RX data

Shift Registers Perform the following functions:

Phase Shift Logics Perform the following functions:

Table 9. Types of Delay in Input Path

Inherent latency Static Captured in pipeline stages from the assertion of

Negative-edge strobe_in delay

Table 10. Input Path Reconfigurable Delays Description

Feature Description Bit-field Description Min Max

RxRcvEnPiRank0[10:7 • RcvEn delay Bit 10 to bit 7 0 15

RxDqsNDelayPi[6:0] • strobe_in delay Phase shift in the 0 127

read_enable_offset[ • rdata_valid delay Delay before reading 0 15