Introduction To Quartus II and VHDL Hierarchical Design
Introduction To Quartus II and VHDL Hierarchical Design
Introduction To Quartus II and VHDL Hierarchical Design
Sheet
Faculty of Engineering
Module Details
Module Code EC3102 Module Title Advanced Digital Design
Program: SLIIT Course: BSc
Stream: Mechatronics
Assessment details
Title Introduction to Group assignment NO
Quartus II and VHDL If yes, Group No.
Hierarchical Design
Lecturer/ Instructor Mr. Sachith Perera Date of Performance 26-07-2022
Due date 03-08-2022 Date submitted 02-08-2022
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EN20401412 Perera P N D
Marks: [ All marks are subject to external moderation and approval of board
of examinations]
Sri Lanka Institute of Information Technology
Laboratory 1
Introduction to Quartus II and VHDL Hierarchical Design
Name: Perera P N D
EN Number: EN20401412
Date of Performance: 26-07-2022
Date of Submission: 02-08-2022
a. Half adder
Figure 3 Simulation
Figure 4 Pin Planner
b. Full adder
Figure 10 Simulation
e.