Lau - 2023 - Recent Advances and Trends in Chiplet Design and Heterogeneous Integration

Recent Advances and Trends
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in Chiplet Design and
Heterogeneous Integration
John H. Lau Packaging
Fellow ASME
Unimicron Technology Corporation, In this study, chiplet design and heterogeneous integration packaging, especially (a)
No. 179, Shanying Rd., chip partition and heterogeneous integration driven by cost and technology optimization,
Taoyuan City 33341, Taiwan Figs. 1(a) and 1(b) chip split and heterogeneous integration driven by cost and yield,
Figs. 1(b) and 1(c) multiple system and heterogeneous integration with thin-film layers
directly on top of a build-up package substrate, Figs. 1(c) and 1(d) multiple system and
heterogeneous integration with an organic interposer on top of a build-up package
substrate, Figs. 1(d) and 1(e) multiple system and heterogeneous integration with through-
silicon via (TSV) interposer on top of a build-up package substrate, Fig. 1(e), will be
investigated. Figures 1(c)–1(e) are driven by formfactor and performance. Emphasis is
placed on their advantages and disadvantages, design, materials, process, and examples.
Some recommendations will also be provided. [DOI: 10.1115/1.4062529]
1 Introduction technology) is shown in Fig. 5. It can be seen the power of Moore’s

law, which increases the number of transistors and functionalities
In 2011, Xilinx asked Taiwan Semiconductor Manufacturing
with a reduction of feature size. Unfortunately, the end of Moore’s
Company (TSMC) to fabricate its field-programable gate array
law is fast approaching, and it is more and more difficult and costly
(FPGA) system-on-chip (SoC) with the 28 nm process technology.
to reduce the feature size (to do the scaling) to make the SoC.
Because of the large chip size, the yield was very poor. Then, Xilinx
redesigned and split the large FPGA into four smaller chiplets as
shown in Fig. 2 and TSMC manufactured the chiplets at high yield 3 Chiplets Design and Heterogeneous Integration
(with the 28 nm process technology) and packaged them on their Packaging
chip-on-wafer-on-substrate (CoWoS) technology. CoWoS is a 2.5D
IC integration, which is the key structure (substrate) to let those four According to International Business Strategies, Fig. 6 shows the
chiplets do vertical and mainly lateral communications. The advanced design cost versus feature size through 5 nm. It can be seen
minimum pitch of the four redistribution layers (RDLs) on the that it will take more than $500 106 to just design the 5 nm feature
TSV-interposer is 0.4 lm, Fig. 3. On Oct. 20, 2013, Xilinx and size. For the 5 nm process technology high manufacturing yield
TSMC [1] have jointly announced the production release of the development, it will take another $1 109.
Virtex-7 HT family with 28-nm process technology, what the pair Figure 7 shows the plots of yield (percent of good dies) per wafer
claims is the industry’s first chiplet design and heterogeneous versus chip size for monolithic design and two-, three-, and four-
integration package in production. Since then, there are a few high- chiplet design [2]. In general, the larger the chip size, the lower the
volume manufacturing (HVM) products using the chiplet design and semiconductor manufacturing yield. Also, a 360 mm2 monolithic
heterogeneous integration packaging technology, which will be die will have a yield of 15% while a four-chiplet design (each
discussed in this study. SoC will be briefly mentioned first. 99 mm2) more than doubles the yield to 37%. The total die area of the
four-chiplet design incurs a 10% area penalty (36 mm2 for a
combined silicon area of 396 mm2) but the significant improvement
2 System-on-Chip in yield which directly translates to lower cost.
System-on-chip integrates ICs with different functions such as
CPU (central processing unit), GPU (graphic processing unit),
3.1 Chip Partition. In chip partition and heterogeneous
memory, etc. into a single chip for the system or subsystem. The
integration (driven by cost and technology optimization), Fig.
most famous SoC is Apple’s application processors (AP), which are
1(a), the SoC, such as the logic and I/Os, are partitioned into
simply shown in Fig. 4 for A10 through A15. The number of
functions (chiplets): logic and I/O. These chiplets can be stacked
transistors versus years with various feature sizes (process
(integrated) by the front-end CoW (chip-on-wafer) or WoW (wafer-
on-wafer) methods and then assembled (integrated) on the same
Contributed by the Electronic and Photonic Packaging Division of ASME for
publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received March 18,
substrate of a single package by using heterogeneous integration
2023; final manuscript received May 3, 2023; published online June 23, 2023. Assoc. techniques [1–38]. It should be emphasized that the front-end
Editor: Willem Van Driel. chiplets’ integration can yield a smaller package area and better
Journal of Electronic Packaging Copyright V

C 2024 by ASME MARCH 2024, Vol. 146 / 010801-1
Fig. 1 Chiplet design and heterogeneous integration packaging. (a) Chip partition. (b) Chip split. (c) Multiple
system and heterogeneous integration with thin-film layers. (d) Multiple system and heterogeneous integration
with organic interposer. (e) Multiple system and heterogeneous integration with TSV-interposer.
Fig. 2 Xilinx/TSMC’s FPGA chip splitting [1]
010801-2 / Vol. 146, MARCH 2024 Transactions of the ASME

Fig. 3 Xilinx/TSMC’s 2.5D IC integration [1]
Fig. 4 Apple’s application processor (AP) SoC. Reproduced with permission. # 2023 Springer Nature.
Fig. 6 Advanced design cost versus feature size. Reproduced

Fig. 5 Apple’s AP. Transistor versus feature size versus year. with permission from International Business Strategies.
Journal of Electronic Packaging MARCH 2024, Vol. 146 / 010801-3

Fig. 7 Semiconductor yield versus chip size [2]
electrical performance but is optional. This integration is the focus (AMD) published a paper on “Cost-Effective Design of Scalable
of Secs. 4–8. High-Performance Systems Using Active and Passive Interposers”
[10]. It shows AMD’s future chiplets design and heterogeneous
3.2 Chip Split. In chip split and heterogeneous integration integration packaging, which will be three-dimensional (3D) IC
(driven by cost and yield), Fig. 1(b), the SoC, such as logic, is split integration as shown in Fig. 8, i.e., the chiplets are (stacked) on top of
into smaller chiplets, such as logic1, logic2, and logic3. These the other chiplet such as logic, so-called the active TSV-interposer.
chiplets can be stacked (integrated) by the front-end CoW or WoW
methods and then assembled on the same substrate of a single
package by using heterogeneous integration techniques [1–38].
Again, the front-end integration of chiplets is optional. This
integration is the focus of Secs. 4–8.
3.3 Multiple System and Heterogeneous Integration.
Besides chip partition and chip split, there is another group of
chiplet design and heterogeneous integration packaging, which is
called multiple system and heterogeneous integration as shown in
Figs. 1(c)–1(e). This group of integration is driven by formfactor and
performance and will be discussed in Sec. 9.
4 Advanced Micro Devices Chiplets Design and
Heterogeneous Integration Packaging
4.1 UCSB/Advanced Micro Devices Future Chiplets Design
and Heterogeneous Integration Packaging. In 2017, University
of California at Santa Barbara (UCSB) and advanced micro devices
Fig. 9 AMD’s EPYC shipped in 2019 [8,9]
Fig. 8 UCSB/AMD’s future chiplet design and heterogeneous

integration packaging [10] Fig. 10 Structure of AMD’s EPYC [8,9]

second-Gen EPYC is a new breed of server processors which sets a
higher standard for data centers. It shows that Rome server product
makes use of a 9–2–9 package (Fig. 9) for signal connectivity with
four layers above the package core for signal routing. One of the
signaling layers (others are similar) is shown in Fig. 10 along with
the physical position of the CCD (CPU compute die), IOD (IO die),
as well as main external DRAM (dynamic random-access memory)
and SerDes interfaces.
For high-performance servers and desktop processors the I/Os are
very heavy. Analog devices and bump pitches for I/Os benefit very
little from leading edge technology and is very costly. One of the
solutions is to partition the SoC into chiplets reserving the expensive
leading-edge silicon for CPU core while leaving the I/Os and
memory interfaces in n 1 generation silicon. Because AMD
committed to keeping the EPYC package size and pin-out
unchanged, there needs to be a close silicon/package codesign as
the number of die increases from four in the first EPYC to nine in the
second Gen EPYC.
The second Gen EPYC chiplet performance versus cost is shown
Fig. 11 AMD’s die cost comparison: chiplet (7 nm 1 12 nm) in Fig. 11. AMD reveal that on TSMC’s 7 nm process technology the
versus monolithic (7 nm) [8,9] cost to manufacture a 16-core monolithic die is more than double
that of a multichiplets CPU. It can be seen from Fig. 11 that: (a) the
lower the core counts, the lower the saving, (b) higher core counts
and performance than possible with a monolithic design, (c) lower
costs at all core count/performance points in the product line, (d) cost
scales down with performance by depopulating chiplets, and (e)
14 nm process technology for IOD reduces the fixed cost. AMD also
optimize the cost structure and improve die yields by using much
smaller chiplets. AMD used the expensive 7 nm process technology
by TSMC for the core cache dies and moved the DRAM and Pie
logic to a 14 nm I/O die fabricated by Global Foundries.
4.3 Advanced Micro Devices Three-Dimensional V-Cache.

During IEEE/ISSC 2022 [3] and IEEE/ECTC 2022 [4], AMD
introduced their 3D V-Cache chiplets design and heterogeneous
integration packaging. Figure 12 shows schematically AMD’s 3D
V-Cache chiplet design and heterogeneous integration packaging.
The key components of this structure are a bottom compute die, top
static random-access memory (SRAM) die, and structural dies to
balance the structure and provide thermal path for heat dissipation
Fig. 12 AMD’s 3D V-Cache [3,4]
from bottom compute die to the heat sink (Fig. 13). The bottom die
(81 mm2) is the “Zen 3’ CPU which is fabricated by TSMC’s 7 nm
process technology. The top die (41 mm2) is the extended L3 die
4.2 Advanced Micro Devices Extreme-Performance Yield which is also fabricated by TSMC’s 7 nm process technology. The
Computing. In mid-2019, AMD introduced the second-generation bottom die with TSV is face-down with C4 (controlled collapse chip
EPYC (extreme-performance yield computing), 7002-series, code- connection) bumps. The top die is also face-down, which is face-to-
name Rome which doubled the number of cores to sixty-four. The back Cu–Cu hybrid bonding to the bottom die, as shown in Fig. 14.
Fig. 13 AMD’s 3D V-cache. Key components [3,4].

Fig. 14 AMD’s 3D V-cache. Physical organization [3,4].
Fig. 15 TSMC’s SoIC SRAM (face)-to-CPU (back) Cu–Cu hybrid Fig. 16 Intel’s Foveros 3D IC integration [13]
bonding of the AMD’s 3D V-cache [5]
5.2 Intel’s Lakefield. In July 2020, Intel shipped their mobile

Figure 15 shows the bonding process and the bonded interface, (notebook) processor “Lakefield,” which is based on their Foveros
which is fabricated by TSMC’ SoIC (system on integrated chips) technology (TYPE-3 of ODI). The SoC is partitioned (e.g., CPU,
technology. The Cu–Cu hybrid bonding minimum pitch is 9 lm. GPU, LPDDR4, etc.) and split (e.g., the CPU is split into one big
CPU and 4 smaller CPU) into chiplets as shown in Figs. 18 and 19.
These chiplets are then face-to-face bonded (stacked) on an active
5 Intel’s Chiplets Design and Heterogeneous TSV-interposer (a large 22FFL base chip) with a CoW (chip-on-
Integration Packaging wafer) process. The interconnect between the chiplets and the logic
base chip is microbump (Cu pillar þ SnAg solder cap) as shown in
5.1 Intel’s Foveros Technology. Figure 16 shows Intel’s Figs. 18 and 19. The interconnect between the base chip and the
Foveros technology (announced in Dec. 2018). It can be seen that package substrate is C4 bump and between the package substrate
the TSV interposer is with CMOS (complementary metal-oxide-
semiconductor) devices (an active interposer), just like a chip, and is
face-to-face thermal compression bonded with the chiplets or SoC.
Figures 17(a) and 17(b) show another technology, announced
during SEMICON West in July 2019, by Intel called omni-
directional interconnect (ODI). For ODI Type 1, Fig. 17(a), the
active TSV interposers (chips) are underneath the big chip such as an
SoC, and are face-to-face thermal compression bonded with the
SoC. For ODI Type 2, Fig. 17(b), the active TSV interposer (bridge,
i.e., chip) is underneath and connecting the chiplets/SoCs. ODI Type
3 is a special case of Type 2, in which the active interposer (or the
base logic chip) is connecting the SoCs/chiplets. Intel also
announced the management data input/output (MDIO) for die-to-
die interface, which is used to replace the current advanced interface
bus (AIB). All these heterogeneous integrations on TSV interposers
are for extreme high performance, and the active TSV interposers
are for even higher performance [18–20]. Fig. 17 (a) ODI (Type 1) and (b) ODI (Type 2) [14]

Fig. 18 Intel’s Lakefield shipped in August 2020 [16]
and PCB is solder ball. The final package formant is a PoP (package-
on-package) (12 mm 12 mm 1 mm) as shown in Fig. 18. The
chiplet design and heterogeneous integration packaging is in the
bottom package and the upper package is housing the memories with
wire bonding technology.
The fabrication of the chiplets is with Intel’s 10 nm process
technology and of the base chip is 22 nm. Since chiplets’ size is
smaller and not all the chips are using the 10 nm process technology,
the overall yield must be higher and thus it translates to lower cost.
It should be noted that this is the very first HVM (high volume
manufacturing) of 3D chiplets integration. Also, this is the very first
HVM of processors for mobile products such as the notebook by 3D
IC integration.
5.3 Intel’s Foveros-Direct. During Intel Architecture Day

(Aug. 13, 2020), they announced a Cu–Cu hybrid bonding for their
FOVEROS technology. At IEEE Hot Chip Conference (Aug. 2021),
they called it FOVEROS-Direct [20] and demonstrated that with
bumpless hybrid bonding the pitch can go down to 10 lm instead of Fig. 20 Intel’s Foveros-Direct (Cu–Cu hybrid bonding) [20]
50 lm like the Lakefield as shown in Fig. 20.
Fig. 19 SEM images of Intel’s Lakefield [17] Fig. 21 Intel’s Ponte Vecchio (spaceship of GPU) [11]

Fig. 22 Schematic of Intel’s Ponte Vecchio [12]
5.4 Intel’s Ponte Vecchio. Another of Intel’s chiplet design Table 1 Key components and their dimensions in Intel’s Ponte
and heterogeneous integration packaging technology is called Ponte Vecchio
Vecchio GPU, or the “spaceship of a GPU” [11,17], which should be
the largest and most chiplets designed to date, Figs. 21–25. The Integration Foveros þ EMIB
Ponte Vecchio GPU will be making use of several key technologies,
Power envelope 600 W
which will power 47 different compute chiplets and 16 thermal dies
Transistor count > 100 B
based on different process nodes and architectures. While the GPU Total tiles 63 (47 functional þ 16 thermal tiles)
primarily makes use of Intel’s 7-nm extreme ultraviolet lithography HBM count 8
(EUV) process node for those eight RAMBO (random access Package form factor 77.5 62.5 mm (4844 mm2)
bandwidth-optimized SRAM tiles), Intel will also be producing Platforms Three platforms
some Xe-HPC compute dies through external fabs (such as TSMC IO 4 16 90 G SERDES, 1 16PCle Gen5
with their 5-nm note for those 16 compute tiles). To be precise Total Silicon 3100 mm2 Si
(Table 1) there are: 47 chiplets consist of 16 Xe-HPCs (internal/ Silicon footprint 2330 mm2 Si footprint
external), 16 thermal dies, eight Rambos (internal), two Xe-Bases Package layers 11–2–11 (24-layer)
2.5D count 11 2.5D connections
(internal), 11 EMIBs (internal), two Xe-Links (external), and eight
Resistance 0.15 mX Rpath/tile
HBMs (external). The maximum top-die (chiplet) size ¼ 41 mm2; Package pins 4468 pins
the base die size ¼ 650 mm2; die-to-die pitch ¼ 36 lm; and package Package cavity 186 mm2 four cavities
layers ¼ 11–2–11, package pins ¼ 4468, and package size ¼
77.5 mm 62.5 mm (Table 1). The power envelope is 600 W. A
close-up of the EMIB is shown in Figs. 23 and 24.
The thermal management of a structure with 600 W of power
envelope is a challenge. Intel’s strategies are (Fig. 25): (a) using
thick interconnect layers in the base and compute tiles act as lateral
heat spreaders, (b) using high microbump density over potential
hotspots to compensate for reduced thermal spreading in a thin-die
stack, and (c) using high array density of power TSVs to reduce C4
bump temperature. In addition, the compute tile thickness is
increased to 160 lm to improve thermal mass for turboperformance.
Furthermore, there are 16 additional thermal shield dies stacked to
provide a thermal solution over exposed base die area to conduct
heat. Backside metallization with solder thermal interface material
(TIM) is applied on all the top dies. The TIM eliminates air gaps
caused by different die stack heights to reduce thermal resistance.
5.5 Intel’s Roadmap. Intel’s roadmap of chiplet design and

heterogeneous integration packaging in terms of interconnect
density versus power efficiency is shown in Fig. 26 [12]. It can be
seen that Cu–Cu hybrid bonding with < 10 lm pad pitch, >10,000/
mm2 pad density, and < 0.05qJ/bit power are their goals soon.
6 TSMC’s Chiplets Design and Heterogeneous

Integration Packaging
6.1 TSMC’s System on Integrated Chips. TSMC have been
Fig. 23 Closed-up of Intel’s Ponte Vecchio [17] working on chiplet design and heterogeneous integration packaging

Fig. 24 Key components in Intel’s Ponte Vecchio [17]
Fig. 25 Thermal management of the Ponte Vecchio GPU [11]
Fig. 26 One of Intel’s roadmaps on chiplet design and hetero- Fig. 27 TSMC’s SoIC (system on integrated chips) versus
geneous integration packaging [12] microbump flip chip [27]

Fig. 28 SoIC versus flip chip: (a) Electrical performance and (b) Pad pitch and density [26]
technology of 3Dfabric is their SoIC (system on integrated chips),

which was announced during the TSMC Annual Technology
Symposium (May 1, 2018) in Santa Clara, CA. 3Dfabric provides
chiplet heterogeneous integrations that are fully integrated from
front to back end. The application-specific platform leverages
TSMC’s advanced wafer technology, open innovation platform
design ecosystem, and 3DFabric for fast improvements and time-to-
market.
Frontend 3D hybrid bonding (stacking) technology SoIC with
CoW and WoW provides flexible chip-level chiplets design and
integration (Fig. 27). Comparing with the conventional microbump
flip chip technology, hybrid bonding SoIC has many advantages, e.
g., better electrical performance, Fig. 28(a), and density, Fig. 28(b),
and better thermal performance and less energy spent per bit data as
shown in Fig. 29 [28].
Fig. 29 SoIC versus typical 3D IC integration: energy and
thermal resistance [28] 6.2 TSMC’s CoWoS With System on Integrated Chips. In
3D backend package integration, CoWoS’ increased envelope and
enriched technology content offers exceptionally high computing
for a few years [22–28]. At the TSMC Annual Technology
performance and high memory bandwidth to meet HPC needs on
Symposium (Aug. 25, 2020), TSMC announced their 3DFabric
clouds, data center, and high-end servers as shown in Fig. 30(a).
(3D fabrication) technology for mobile, high-performance comput-
Figure 15 shows one of AMD products fabricated by TSMC’s SoIC
ing, automotive, and IoT (internet of things) applications. The core
technology.
6.3 TSMC’s Integrated Fan-Out Package-on-Package With

System on Integrated Chips. In another 3D backend package
integration, InFO (integrated fan-out) derivative technology offers
memory-to-logic, logic-to-logic, PoP (package-on-package), etc.
applications as shown in Fig. 30(b).
Fig. 30 Frontend stacking of chiplets with SoIC before heteroge-

neous integration packaging. (a) CoWoS with SoIC. (b) InFO PoP Fig. 31 TSMC’s roadmaps on CoWoS with SoIC and InFO PoP
with SoIC. Reproduced with Permission from [28]. # 2019 IEEE. with SoIC [27]

6.4 TSMC’s Roadmap. TSMC’s chiplet design and heteroge- interposer or the whole organic build-up package substrate to
neous integration packaging roadmap is shown in Fig. 31 [27]. It can support the lateral communication between chiplets. Therefore, the
be seen that CoWoS and InFO PoP are already in HVM and CoWoS concept of using small area and a fine-metal L/S/H RDLs bridge to
with SoIC and InFO PoP with SoIC are ramping up in HVMg. connect the chiplets to perform lateral communication (to reduce
cost and enhance performance) for chiplet design and heterogeneous
integration packaging has been proposed and is a very hot topic
7 Advantages and Disadvantages of Chiplets Design and today. There are at least two different groups of bridge, namely, rigid
Heterogeneous Integration Packaging bridge and flexible bridge. Only rigid bridge will be discussed in this
The key advantages of chiplet heterogeneous integrations (chip study.
partition and chip splitting) compared with SoCs are yield Rigid bridge consists of the RDLs and the substrate. Most rigid
improvement (lower cost) during manufacturing, time-to-market, bridges are made with silicon substrate and the RDLs are fabricated
and cost reduction during design. Figure 7 shows the plots of yield on a silicon wafer. Some rigid bridges are even with TSVs. Today,
(percent of good dies) per wafer versus chip size for monolithic most of the products and publications with bridges are rigid bridges.
design and 2-, 3-, and 4-chiplet design [2]. It can be seen that the There are at least three groups of rigid bridges, namely, (a) rigid
smaller the chip size the higher the semiconductor manufacturing bridges embedded in build-up package substrate, Sec. 8.1, (b) rigid
yield. The significant improvement in yield directly translates to bridges embedded in fan-out EMC (epoxy molding compound) with
lower costs. Also, chip partitioning will enhance the time-to-market. RDLs, Sec. 8.2, and (c) hybrid bonding bridge, Sec. 8.3.
Furthermore, chiplets with CPU cores can reduce silicon design and
manufacturing costs. Finally, there is also thermal benefit to using
chiplets as the chips are spread out across the package. 8.1 Intel’s Embedded Multidie Interconnect Bridge. The
The disadvantages of chiplet heterogeneous integration are: (1) most famous rigid bridge is Intel’s EMIB (embedded multidie
additional package area due to chip partition and chip splitting, (2) interconnect bridge) [39–42]. Figure 32 shows one of Intel’s EMIB
the chiplets interfaces (bridges) increase packaging costs, (3) more patents [39]. It can be seen that the EMIB die is embedded in the
complexity and packaging design effort, and (4) past methodologies cavity of a build-up package substrate, which is supporting the
are less suitable for chiplets. Thus, the challenges (opportunities) for chiplets.
packaging technologists are to reduce the size of packages and For EMIB, there are at least three important tasks, Figs. 32 and 33,
provide high-density, high-performance, and low-cost chiplets namely: (a) wafer bumping of two different kinds of bumps on the
interfaces – bridges. chiplets wafer (but there are not bumps on the bridge); (b)
embedding the bridge in the cavity of a build-up substrate and
then laminating the top surface of the substrate; and (c) bonding the
8 Lateral Coummication Between Chiplets (Bridge) chiplets on the substrate with the embedded bridge.
In the past, lateral communications of chiplet design and
heterogeneous integration packaging are by fine metal line width, 8.1.1 Solder Bumps for Embedded Multidie Interconnect
spacing, and thickness (L/S/H) TSV-interposer or build-up organic Bridge. It can be seen from Fig. 32 that there are two kinds of
package substrate. For example, Figs. 2 and 3 show the Virtex-7 HT bumps on the chiplet, namely, the C4 (controlled collapse chip
family with TSV-interposer shipped by Xilinx in 2013. The TSV- connection) bumps and the C2 (chip connection or copper-pillar
interposer is known to have a very high cost. On the other hand, with solder-cap micro) bumps. Thus, wafer bumping of the chiplets
Fig. 9 shows AMD’s second-generation EPYC server processors wafer poses a challenge, but Intel has already taken care of this issue.
[8,9], the 7002-series, shipped in mid-2019. The EPYC is a two-
dimensional (2D) IC integration technology, i.e., all the chiplets are 8.1.2 Fabrication of Embedded Multidie Interconnect Bridge
side-by-side on a 9–2–9 build-up package substrate. The 20-layer Substrate. There are two major tasks in fabricating the organic
fine metal L/S/H organic substrate is not cheap. package substrate with EMIB (Fig. 33). One is to make the EMIB,
It should be noted that the requirement of lateral communications and the other is to make the substrate with EMIB. To make the
(RDLs) between chipets is fine-metal L/S/H and at a very small and EMIB, one must first build the RDLs (including the contact pads) on
local area of the chiplets. There is no reason to use the whole TSV- a Si-wafer. The way to make the RDLs depends on the L/S/H of the
Fig. 32 Intel’s EMIB patent and structure [39]

conductive wiring of the RDLs. Finally, attach the non-RDL side of holes and make contact pads, Fig. 33(c). (Smaller pads on a finer
the Si-wafer to a die-attach film, and then singulate the Si-wafer. pitch are for C2 bumps, while larger pads on a gross pitch are for C4
To make the substrate with an EMIB, first place the singulated bumps.) The organic package substrate with an EMIB is ready for
EMIB with the die-attached film on top of the Cu foil in the cavity of bonding of the chips as shown in Fig. 33(d).
the substrate, Fig. 33(a). It is followed by laminating a dielectric film Today, the minimum metal L/S/H is 2 lm/2 lm/2 lm and the
on the whole organic package substrate and then, drilling (on the bridge size is from 2 mm 2 mm to 8 mm 8 mm [40], but most are
dielectric film) and Cu plating to fill the holes (vias) to make equal and less than 5 mm 5 mm [41]. The dielectric layer thickness
connections to the contact pads of the EMIB. Continue Cu plating to is 2 lm. Usually, there are 4 RDLs. One of the challenges of the
make lateral connections of the substrate as shown in Fig. 33(b). EMIB technology is to fabricate the organic build-up package
Then, it is followed by laminating another dielectric film on the substrate with cavities for the silicon bridges and then laminate (with
whole substrate and drilling (on dielectric) and Cu plating to fill the pressure and temperature) another build-up layer on top (to meet the
Fig. 33 Intel’s EMIB in build-up package substrate. Reproduced with Permission from [41]. # 2019 IEEE.
Fig. 34 Intel’s Kaby Lake processor with AMD’s Radeon graphics as well as HBM with EMIB.
Reproduced with Permission from [41]. # 2019 IEEE.

substrate surface flatness requirement) for chiplets (with both C2 Interface quality.
and C4 bumps) bonding. Intel and its suppliers are working toward Die attach film material design.
high-yield manufacturing of the substrate. Die shift.
Via-to-die-pad overlay alignment.
8.1.3 Bonding Challenges for Embedded Multidie Interconnect Integrated process considerations.
Bridge. Intel published a paper at IEEE/ECTC 2021 [42] that
pointed out the following bonding challenges of chiplets:
8.1.4 Intel’s Products with Embedded Multidie Interconnect
Die bonding process. Bridge. Figure 34 shows Intel’s processor (Kaby Lake) that
Manufacturing throughput. combines its high-performance 86 cores with AMD’s Radeon
Die warpage. Graphics into the same processor package using Intel’s own EMIB
Fig. 35 Intel’s Agilex FPGA with EMIB. Reproduced with Permission from [41]. # 2019 IEEE.
Fig. 36 IBM’ DBHi [43,45]

as well as HBM (2017). Unfortunately, Intel canceled all the Kaby 35, while for IBM’s DBHi, there are C4 bumps on the chiplets
Lake-G products in October 2019. and C2 bumps on the bridge, Fig. 36.
Figure 35 shows the Agilex FPGA (field programable gate array) For Intel’s EMIB, the bridge is embedded in the cavity of a
module. It can be seen that the FPGA and other chips are attached on build-up substrate with a die-attach material and then
top of a build-up package substrate with EMIB with fine-metal L/S/ laminated with another build-up layer on top. Therefore, the
H RDLs. The TSV interposer is not needed. Figure 24 shows the substrate fabrication is very complicated as mentioned in
Intel spaceship of GPU (Ponte Vecchio), which has 11 EMIBs.
8.2 IBM’s Direct Bonded Heterogeneous Integration. Dur-

ing IEEE/ECTC2021 and 2022, IBM presented seven papers on
“Direct Bonded Heterogeneous Integration (DBHi) Si Bridge”
[43–50], Fig. 36. The major differences between Intel’s EMIB and
IBM’s DBHi are as follows:
For Intel’s EMIB, there are two different (C4 and C2) bumps on
the chiplets (and there are no bumps on the bridge), Figs. 32 and
Fig. 39 DBHi TCB temperature-force-time profile [49]
Fig. 37 IBM’s DBHi. (a) C2 bumps on the bridge while C4 bumps

on the chiplet and (b) Ordinary build-up package substrate with
cavity [43,45].
Fig. 40 Applied Materials’ bridge patent with fan-out bridge-first
and die face-up process (US 10,651,126) [51]
Fig. 38 DBHi bonding process. (a) TCB of the bridge die to Chip 1
with NCP. (b) TCB of the bridge die to Chip 2 with NCP. (c) C4
solder reflow of the Chip 1 and Chip 2 on the package with cavity Fig. 41 Unimicron’s bridge patent with fan-out bridge- first and
and then underfill [49]. die face-down process (US 11,410,933) [52]

Sec. 8.1. For IBM’s DBHi, the substrate is just a regular build- used for making the UBM and metal pad, and the second lithography is
up substrate with a cavity on top as shown in Fig. 37(b). used to make the C4 bumps by injection molded solder (IMS) method.
8.2.1 Solder Bumps for Direct Bonded Heterogeneous Integra- 8.2.2 DBHi Bonding Assembly. The bonding assembly process
tion. As shown in Fig. 37(a), there are C2 bumps on the bridge. of DBHi is very simple, Fig. 38. First, apply the nonconductive paste
However, there are C4 bumps and Cu pads on the chiplet of the same (NCP) on Chip 1. Then, bond the Chip 1 and the bridge with thermal
wafer. Thus, wafer bumping poses a challenge. IBM use a double compression bonding (TCB). After bonding, the NCP becomes the
lithography process to resolve this issue [43]. The first lithography is underfill between Chip 1 and the bridge. Then, apply NCP on the
bridge and bond Chip 2 and the bridge with TCB. Those steps are
followed by placing the module (Chip 1 þ bridge þ Chip 2) on the
organic substrate with a cavity and then going through the standard
flip-chip reflow assembly process.
The stage temperature, bonding force, and bond-head tempera-
ture versus time during bonding are shown in Fig. 39 [49]. It can be
seen that: (a) the bonding stage temperature (T1) is small and kept at
constant all the times, (b) the bond-head temperature consists of
three stages: (i) at the first stage the temperature (T2) is larger than
T1, which is used to melt and flow the NCP; (ii) at the second stage
the temperature (T3 ¼ 2 T1) is the largest, which is used to reflow the
solder; and (iii) at the final stage the temperature (T4) is less than T2
and larger than T1, which is used to solidify the solder joints. The
underfill under the bridge is optional. Figure 36 shows the
Fig. 42 IME’s bridge patent with fan-out bridge-last or RDL-first

process (US 11,018,080) [53]
Fig. 45 SPIL’s FO-EB [56]
Fig. 43 (a) TSMC’s InFO-LSI and (b) CoWoS-LSI [54]
Fig. 46 Amkor’s S-Connect with Si-bridge [57]
Fig. 44 ASE’s sFOCoS [55] Fig. 47 IME’s bridge with EFI [58]

demonstration by IBM. If the bridge is very thin, e.g., 50 lm and the Dealing with a situation in which there is more than one rigid
C2 bump is very short, e.g., 30 lm, then the cavity of the package bridge on a chiplet.
substrate is not needed if the C4 solder bump height is > 85lm. Dealing with a situation in which there are more than two
chiplets on a package substrate.
8.2.3 Direct Bonded Heterogeneous Integration Challenges.
The challenges in IBM’s DBHi are:
8.3 Bridge Embedded in Fan-Out Epoxy Molding Com-
Handling and bonding of a portion of the tiny rigid bridge on a pound With Redistribution Layers. Intel’s and IBM’s rigid
portion of the large chiplet with very fine-pitch pads. bridges are either embedded in or are on an organic package
Fig. 48 High-speed standardized chip-to-chip interface (bridge) – Universal Chiplet
Interconnect Express (UCIe)
Fig. 49 Universal Chiplet Interconnect Express’s standard and advanced packaging with
bridges [59]

Fig. 50 Hybrid bonding bridge
Fig. 51 Hybrid bonding bridge with C4 bumps on the package substrate
Fig. 52 Hybrid bonding bridge with C4 bumps on the chiplet wafer

substrate. There is another class of rigid bridge, which is embedded 8.3.2 Unimicron’s Bridge-First and Face-Down Process. On
in the fan-out EMC and connected to the fan-out RDL-substrate. June 21, 2022, Unimicron obtained the U.S. patent U.S. 11,410,933
[52] in which the bridge is embedded in the fan-out EMC by the chip
(bridge) first and die face-down process (Fig. 41).
8.3.1 Applied Materials’ Bridge-First and Face-Up Process.
On May 12, 2020, Applied Materials obtained the U.S. patent 8.3.3 IME’s Bridge-Last Process. On May 25, 2021, IME
10,651,126 [51]. The company’s design embedded the bridge in obtained the U.S. patent U.S. 11,018,080 [53] in which For the
EMC by the fan-out chip (bridge) first and die face-up process bridge is embedded in the EMC and connected to the RDL-substrate
(Fig. 40). by the chip (bridge) last or RDL-first fan-out process, (Fig. 42).
Fig. 53 Multiple system and heterogeneous integration on (a) package substrate, (b) package substrate with thin-
film layers, (c) package substrate with organic interposer, (d) package substrate with passive TSV interposer, and
(e) package substrate with active TSV interposer [61,62].
Fig. 54 Multiple system and heterogeneous integration on package substrate [63]

8.3.4 Publications by TSMC, ASE, Amkor, SPIL, IME, and comparable technology as S-Connect fan-out interposer (Fig. 46). In
Universal Chiplet Interconnect Express. In the past couple of years, Ref. [58], IME presented its bridge and called it embedded fine
there are many publications in rigid bridges embedded in fan-out interconnect (EFI) (Fig. 47). During IEEE/ECTC (June 2022), IBM
EMC with RDLs. For examples, On Aug. 25, 2020, during TSMC’s published six papers [44–50] in this area.
Annual Technology Symposium, the company announced its An important consortium concerned with bridge technology is the
Universal Chiplet Interconnect ExpressV (UCIeV), Fig. 48.
R R
integrated fanout local silicon interconnect (InFO_ LSI) and chip-
on-wafer-on-substrate local silicon interconnect (CoWoSV _LSI)
R
According to the consortium’s website, the organization addresses
(Fig. 43) [54]. During IEEE/ECTC (June 2021), there were at least customer requests for a more customizable, package-level
four papers published regarding the application of fan-out pack- integration—combining best-in-class die-to-die interconnect and
aging technology to embed the rigid bridge in the EMC with RDLs protocol connections from an interoperable, multivendor ecosys-
for the chiplets to perform lateral communications. All four of these tem. This new open industry standard establishes a universal
interconnect at the package level. The UCIeV board of directors and
R
papers discuss very similar technologies. In Ref. [55], ASE
embedded the bridge in the EMC using the fan-out packaging leadership (promoters) include founding members ASE, AMD,
method and called it stacked Si bridge fan-out chip-on-substrate Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corpo-
(sFOCoS) (Fig. 44). In Ref. [56], Siliconware Precision Industries ration, Qualcomm Incorporated, Samsung Electronics, and TSMC,
Co., Ltd. (SPIL) called its similar technology fan-out embedded along with newly elected members, Alibaba and NVIDIA.
In Ref. [59], Intel published the UCIeV 1.0 specification, which
R
bridge (FO-EB) (Fig. 45). In Ref. [57], Amkor referred to its
provides a complete standardized die-to-die interconnect with
physical layer, protocol stack, software model, and compliance
testing. Figure 49 shows examples of standard packaging and
advanced packaging with chiplet design and heterogeneous
integration. It can be seen that there are three different kinds of
bridges for advanced packaging: (1) bridge embedded in organic
package substrate; (2) bridge embedded in Si-interposer; and (3)
bridge embedded in fan-out EMC with RDLs.
8.4 Hybrid Bonding Bridge. Unimicron proposed the use of

Cu–Cu hybrid bonding for the bridge between chiplets in chiplet
design and heterogeneous integration packaging, (Fig. 50). The
advantages of this structure are: (1) higher density, (2) better
performance, and (3) ordinary package substrate. There are at least
two options: one is with C4 bumps on the package substrate, and the
other is with C4 bumps on the chiplet wafer.
8.4.1 C4 Bump on Package Substrate. Figure 51 shows the
process flow of a hybrid bonding bridge with C4 bumps on the
package substrate. For the bridge wafer, the processing starts off
with chemical vapor deposition (CVD) to make a dielectric material
Fig. 55 (a) TSMC’s AiP [64] and (b) Unimicron’s heterogeneous such as SiO2 and then it is planarized by an optimized chemical
integration of RF chip and baseband chip on package substrate mechanical polishing (CMP) process to make the Cu dishing. Then,
[65] the bridge wafer is diced into individual chips (still on the blue tape
Fig. 56 Shinko’s heterogeneous integration of chips on package substrate with thin-film

layers [66,67]

Fig. 57 Unimicron’s heterogeneous integration of chips on package substrate with thin-film
layers: (a) Thin-film layers and (b) build-up package substrate
Fig. 58 Unimicron’s heterogeneous integration of chips on package substrate with thin-film layers
Fig. 59 Samsung’s multiple system and heterogeneous integration on a package substrate

with RDL organic interposer [84,85]

temperature. These steps are followed by annealing to achieve
covalent bonding between oxide layers and metallic bonding
between Cu–Cu contacts and the diffusion of Cu atoms. For the
package substrate, the process is to stencil print the solder paste on
the substrate and then reflow into C4 solder bumps. For the final
assembly, the bridge þ chiplets module is picked and placed on the
package substrate, then the C4 bumps are reflowed.
8.4.2 C4 Bump on Chiplet Wafer. Figure 52 shows the process
flow of the hybrid bonding bridge with C4 bumps on the chiplet
wafer. It can be seen that, compared with the C4 bumps for the
package substrate case, the process steps for the bridge wafer and the
chiplet wafer are the same up to the bridge-to-chiplet wafer bonding
step. After that, the C4 bumps are fabricated by wafer bumping on
the chiplet wafer. Then, the chiplet wafer is diced into individual
modules (bridge þ chiplets with C4 bumps). The final assembly is
accomplished by picking and placing the individual module on the
package substrate and reflowing the C4 solder bumps.
9 Multiple System and Heterogeneous Integration

Besides the chip partition and chip split there is another group of
chiplets design and heterogeneous integration packaging called
multiple system and heterogenous integration, which is driven by
formfactor and performance [60–62]. There are at least five different
Fig. 60 ASE’s multiple system and heterogeneous integration kinds of multiple systems and heterogenous integrations as shown in
on a package substrate with RDL organic interposer [86–95] Fig. 53, which will be discussed briefly in Secs. 9.1–9.5.
9.1 Multiple System and Heterogeneous Integration on

of the wafer) after application of a protective coating layer on the Package Substrate (2D IC Integration). Figure 53(a) shows a
wafer surfaces to prevent any particles and contaminants that may multiple system and heterogeneous integration on a package
cause interface voids during the subsequent bonding process. These substrate (2D IC integration). It can be seen that the multiple system
steps are followed by activating the bonding surface by using plasma is supported by a high-density package substrate. An example is
and hydration processes for better hydrophilicity and a higher shown in Fig. 54, where the heterogeneous integration of three chips
density of a hydroxyl group on the bonding surface. To process the is supported by a fine metal L/S (2 lm/2 lm) RDL-substrate [63],
chiplet wafer, repeat the CVD process for the SiO2, CMP for the Cu Fig. 55(a) shows a TSMC’s patent on AiP (antenna-in-package)
dishing, and plasma and hydration of the activation of the bonding [64]. Figure 55(b) shows Unimicron’s patent on the heterogeneous
surface. Then, pick and place the individual bridge chip on the integration of the RF chip and the baseband chip on a fan-out RDL-
chiplet wafer and perform the SiO2-to-SiO2 bonding at room substrate, and the patch antenna [65].
Fig. 61 (a) TSMC’s multiple system and heterogeneous integration on a package substrate
with RDL organic interposer. (b) CoWoS-R1 [86–89].

9.2 Multiple System and Heterogeneous Integration on Pack- (plated) with Cu through the thin-film layers and stopped at the pad
age Substrate With Thin-Film Layers (2.1D IC Integration). of the build-up package substrate.
Figure 53(b) shows a multiple system and heterogeneous integration
on a package substrate with thin-film layers [33]. An example is 9.3 Multiple System and Heterogeneous Integration on Pack-
shown in Fig. 56, where the 2 lm/2 lm (L/S) thin-film layers age Substrate With TSV-Less Interposer (2.3D IC Integration).
are built directly on top of the build-up package substrate [66,67]. Figure 53(c) shows a multiple system and heterogeneous integration
However, because of the flatness of the build-up package on a hybrid package substrate with a TSV-less interposer (or organic
substrate the yield loss of manufacturing the thin-film layers is interposer) [60–62]. The structure consists of a multiple system on a
very large. hybrid substrate which is a combination of a build-up package
A new method is shown in Figs. 57 and 58 [68], where the thin- substrate [or high-density interconnect (HDI)], solder joints with
film layers with a glass temporary carrier, Fig. 57(a), and the build- underfill [69–73], and a fine metal L/S RDL-substrate (or organic
up package substrate, Fig. 57(b), are built separately, and then they interposer). The organic interposer of the hybrid substrate can be
are combined with either PID (photo-imageable dielectric) or ABF fabricated by the fan-out chip-first packaging process [74–79] or the
(Ajinomoto build-up film), Fig. 58. Vias are drilled and filled chip-last (or RDL-first) process [80–108].
Fig. 62 Unimicron’s heterogeneous integration of two chips on a package substrate with

organic interposer made by PID [102–104]
Fig. 63 Unimicron’s heterogeneous integration of two chips on a package substrate with

organic interposer made by ABF [105,106]

Fig. 64 Unimicron’s heterogeneous integration of three chips on a hybrid substrate [107,108]
For hybrid substrate with organic interposer fabricated by fan-out Furthermore, the logistic is simpler; after receiving the known-good
chip-last packaging process [80–108], the organic interposer and the hybrid substrate from the substrate houses, the OSAT (outsourced
build-up package substrate are fabricated separately. Then, they are semiconductor assembly and test) houses just bond the chips/HBMs
combined in two different assembly processes. One is to first bond on the known-good hybrid substrate.
the chips on the organic interposer, underfilling and EMC (epoxy For examples, Fig. 62 shows the heterogeneous integration of two
molding compound) molding, and then assemble the module chips on a hybrid substrate with an organic interposer made from
(chips þ organic interposer) on the build-up package substrate PID [102–104], Fig. 63 shows the heterogeneous integration of two
[80–101]. For example, Fig. 59 shows Samsung’s multiple system chips on a hybrid substrate with an organic interposer made from
and heterogeneous integration on a package substrate with a TSV- ABF [105,106], and Fig. 64 shows the heterogeneous integration of
less interposer (or organic interposer) [84,85], Fig. 60 shows ASE’s three chips on a hybrid substrate made by an interconnect-layer
[93–95], and Fig. 61 shows TSMC’s [86–89]. [107,108]. It has been found that (a) the metal lines in the organic
The other assembly process is first to combine the organic interposer made from ABF are flatter than those from PID, and (2)
interposer and the build-up package substrate into a hybrid substrate the solder bumps and underfill are replaced by an interconnect-layer
through the solder joints that are enhanced with underfill [102–106] made by prepreg with vias filled by conductive paste. Figure 65
or through the interconnection-layer [107,108]. Then, test the shows the heterogeneous integration of the EIC (electrical
combined substrate and make sure it is a known-good hybrid integrated circuits) and PIC (photonic integrated circuits) on a
substrate. Finally, bond the chips on the known-good hybrid hybrid substrate [109].
substrate. In this case, the yield loss of the hybrid substrate
especially the organic interposer is easier to control and smaller.
Also, there is very little chance of losing the known-good dies. 9.4 Multiple System and Heterogeneous Integration on
Package Substrate With Passive TSV-Interposer (2.5D IC
Integration). Figure 53(d) shows a multiple system and heteroge-
neous integration on a package substrate with a passive TSV
Fig. 65 Heterogeneous integration of EIC and PIC on a package Fig. 66 Graphcore’s multiple system and heterogeneous inte-
substrate with organic interposer gration on a package substrate with a passive TSV interposer [29]

Fig. 67 Fujitsu’s multiple system and heterogeneous integration on a package substrate with
a passive TSV interposer [226]
interposer [110–233]. 2.5D IC integrations use a through-silicon via processor (Fig. 66) [29], Fujitsu shipped their A64FX CPU
(TSV)-interposer to support the SoC and memories such as the high- (Fig. 67) [226], etc.
bandwidth memory (HBM) and then it is attached to a package
substrate, Fig. 53(d). The TSV-interposer consists of TSVs and
RDLs and is called passive TSV-interposer. 9.5 Multiple System and Heterogeneous Integration on Pack-
The first papers published on 2.5D IC integration were by Leti age Substrate With Active TSV-Interposer (3D IC Integration).
[110,111] at ECTC2005 and 2006. On Oct. 20, 2013, Xilinx and Figure 53(e) shows a multiple system and heterogeneous integration
TSMC [1] jointly announced the production release of the Virtex-7 on a package substrate with an active TSV interposer [10,18–20,
HT family, what the pair claims is the industry’s first 2.5D IC 30,31,233], which is, besides TSVs and RDLs, with CMOS devices.
integration in production. Since then, AMD shipped their Radeon For example, Intel’s Foveros (Figs. 16–19) [18–20], Leti/STMi-
R9 Fury X GPU [176], Nvidia shipped their Pascal 100 GPU [177], croelectronics’ INTACT (Fig. 68) [30,31], and heterogeneous
Graphcore shipped their intelligence processing unit (IPU) integration of EIC on PIC with TSVs (Fig. 69) [62].
Figure 70 shows schematically a large-body-sized glass-based
interposer for high-performance computing by George Institute of
Technology (GIT) [233]. It can be seen that; (a) the glass interposer
with TGVs is supporting chiplets as well as active routers and
passive components, and (b) there are RDLs on the active
interposer’s topside and bottom-side. Also, the electrical perform-
ance (insertion loss per unit length) for different traces on glass
interposer is better than that on silicon. A cross section of the sample
Fig. 68 Leti/STMicroelectronics’ six chiplets on a package Fig. 69 Multiple system and heterogeneous integration of EIC
substrate with an active TSV interposer [30,31] on PIC with TSV interposer (an active TSV interposer)

Fig. 70 (a) Schematic of glass-based active interposer. (b) Fabricated sample. (c) Insertion
loss/mm for various traces on glass active interposers and silicon [233].
is shown in the middle of Fig. 70. It can be seen that a 100 lm-thick 10.2 Structural Design and Material Selection of Multiple
die embedded in the glass cavity is connected to the chiplet (not System and Heterogeneous Integration With Very Large
shown) on top of the TGV-interposer with RDLs. Package Substrate. The package substrate for multiple system
and heterogeneous integration packaging is getting larger and larger.
10 Potential Research Topics For example, Fig. 72(a) shows the one (85 mm x 85 mm) by
Samsung [230] and Fig. 72(b) shows the one (91 mm x 91 mm) by
10.1 Interconnection Technology Between Chiplets and MediaTek [76]. Assembly issues such as warpages, stretch or open
Bridge. For chip partition and chip split, the interface (bridge) solder solders, etc. exist. Thus, optimal structural design and its
between chiplets is one of the most important elements in chiplet material selection are of utmost importance.
design and heterogeneous integration packaging. Currently, the
most used interconnect technology between the bridge and chiplets
is microbump (Cu-pillar þ solder cap) as shown in Fig. 71. A 10.3 Frontend Hybrid Bonding of Chiplets Before Hetero-
potential research topic is: “what is the interconnect technology geneous Integration Packaging. As mentioned in Secs. 3.1 and 3.2
between the bridge and chiplets, so the system will achieve better and Figs. 1(a) and 1(b), frontend integration of some of the chiplets
performance, higher density, simpler package substrate, and lower (before package heterogeneous integration) can yield a smaller
cost?” package size and a better performance [60]. Thus, it is a very good
R&D topic. Figure 73 shows the example of Cu–Cu hybrid bonding
between some chiplets before they are attached to the organic
interposer or the TSV interposerk.
11 Summary and Recommendations

Some important results and recommendations are summarized as
follows:
SoCs with chip scaling are and will be here to stay. However
only a handful of companies such as Apple, Samsung, Intel,
AMD, Nvidia, Huawei, Google can afford them at finer feature
size (advanced nodes). Chiplet design and heterogeneous
integration packaging provide alternatives (options) to SoCs,
especially for advanced nodes, which most companies cannot
afford.
Fig. 71 (a) Current interconnects between bridge and chips. Chiplet design such as chip partition and chip split are driven by
(b) New interconnects between bridge and chips, which will yield semiconductor manufacturing yield and cost. Examples such
higher density (finer pitch), better performance, and simpler as those given by Xilinx/TSMC, AMD/TSMC, and Intel have
package substrate. been presented.

Fig. 72 Multiple system and heterogeneous integration on a package substrate with a passive
TSV interposer. (a) Package substrate 5 85 mm 3 85 mm [230]. (b) Package substrate 5
91 mm 3 91 mm [76].
Fig. 73 Multiple system and heterogeneous integration on a package substrate with

(a) organic interposer and (b) TSV interposer. For both cases, Cu–Cu bonding some of the
chiplets before heterogenous integration packaging.
Chiplet design and heterogeneous integration packaging is no- are higher density (finer pitch), better performance, less
good (the opportunity) for packaging: (a) increase package size process steps, simpler package substrate, and lower cost.
and package complexity, (b) increase packaging efforts such as Multiple systems and heterogeneous integration such as 2D,
bridge design, fabrication, and assembly, and (c) increase 2.1D, 2.3D, 2.5D, and 3D IC integration are driven by
packaging cost. formfactor and performance. Examples such as those given
In general, the semiconductor cost is a few times the packaging by TSMC, Shinko, Samsung, ASE, Graphcore, Fujitsu, Leti,
cost, therefore, the savings that can be achieved with chiplet STMicroelectronics, and Unimicron have been presented.
design and heterogeneous integration packaging are worth One of the trends in chiplet design and heterogeneous
pursuing. integration packaging is to develop new interconnect method
Interface (bridge) is the most important element of chiplets between the bridge and the chiplets such that higher
design and heterogeneous integration packaging. Bridges performance, finer pitch, higher density, simpler package
embedded in (a) package substrate such as those given be substrate, and lower cost can be achieved.
Intel and IBM, and (b) fan-out EMC with RDLs such as those One of the trends in chiplet design and heterogeneous
given by Applied Materials, TSMC, Unimicron, ASE, Amkor, integration packaging is to optimal design and material
SPIL, and IME have been briefly presented. selection of multiple system and heterogeneous integration
A new interconnect between the bridge and the chiplets with structure with very large package substrate (100 mm
hybrid bonding technology has been proposed. Its advantages 100 mm).

One of the trends in chiplet design and heterogeneous 10 nm and 2FFL Hybrid Processor System in 12 12 mm2, 1 mm Package-on-
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Lau - 2023 - Recent Advances and Trends in Chiplet Design and Heterogeneous Integration

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Recent Advances and Trends

1 Introduction technology) is shown in Fig. 5. It can be seen the power of Moore’s

Journal of Electronic Packaging Copyright V

Fig. 2 Xilinx/TSMC’s FPGA chip splitting [1]

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Fig. 6 Advanced design cost versus feature size. Reproduced

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Fig. 8 UCSB/AMD’s future chiplet design and heterogeneous

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4.3 Advanced Micro Devices Three-Dimensional V-Cache.

Fig. 13 AMD’s 3D V-cache. Key components [3,4].

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5.2 Intel’s Lakefield. In July 2020, Intel shipped their mobile

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5.3 Intel’s Foveros-Direct. During Intel Architecture Day

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5.5 Intel’s Roadmap. Intel’s roadmap of chiplet design and

6 TSMC’s Chiplets Design and Heterogeneous

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Fig. 25 Thermal management of the Ponte Vecchio GPU [11]

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technology of 3Dfabric is their SoIC (system on integrated chips),

6.3 TSMC’s Integrated Fan-Out Package-on-Package With

Fig. 30 Frontend stacking of chiplets with SoIC before heteroge-

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Fig. 32 Intel’s EMIB patent and structure [39]

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Fig. 36 IBM’ DBHi [43,45]

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8.2 IBM’s Direct Bonded Heterogeneous Integration. Dur-

Fig. 39 DBHi TCB temperature-force-time profile [49]

Fig. 37 IBM’s DBHi. (a) C2 bumps on the bridge while C4 bumps

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Fig. 42 IME’s bridge patent with fan-out bridge-last or RDL-first

Fig. 45 SPIL’s FO-EB [56]

Fig. 43 (a) TSMC’s InFO-LSI and (b) CoWoS-LSI [54]

Fig. 46 Amkor’s S-Connect with Si-bridge [57]

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Fig. 51 Hybrid bonding bridge with C4 bumps on the package substrate

Fig. 52 Hybrid bonding bridge with C4 bumps on the chiplet wafer

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Fig. 54 Multiple system and heterogeneous integration on package substrate [63]

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8.4 Hybrid Bonding Bridge. Unimicron proposed the use of

Fig. 56 Shinko’s heterogeneous integration of chips on package substrate with thin-film

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Fig. 59 Samsung’s multiple system and heterogeneous integration on a package substrate

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9 Multiple System and Heterogeneous Integration

9.1 Multiple System and Heterogeneous Integration on

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Fig. 62 Unimicron’s heterogeneous integration of two chips on a package substrate with

Fig. 63 Unimicron’s heterogeneous integration of two chips on a package substrate with

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11 Summary and Recommendations