OPERATING MODES OF 8086 MICROPROCESSOR

8086 microprocessor characteristics:

 It contains 20 bit address bus.
 It contains 16-bit data bus, therefore 8086 is called as 16-bit microprocessor.
 It is 2-stage pipelined processor. It can prefetch 6-bytes from memory and store
into queue to increase the speed of the execution.
 It’s control bus carries signals for executing operations such as read, write etc.
 It has Memory Banks. 2 banks of 512KB each. These banks are called as lower
Bank (even) and higher Bank (odd).
 In 8086 the entire memory is divided into four memory segments which are code,
stack, data and extra segment.
 8086 has 16 bit IO address.
 It has 256 interrupts.
8086 has two operating Modes:
1. Minimum mode
2. Maximum mode
Minimum mode configuration of 8086 microprocessor (Min mode):
 In this 8086 is the only processor in the system.
 8086 is operated in minimum mode when MN/MX’ pin to logic 1.
 In this mode, all the control signals are given out by the 8086 itself.
Overview:
 The 8086 microprocessor operates in minimum mode when MN/MX’ = 1.
 In minimum mode, 8086 processor provides all the control signals needed
for memory operations and I/O interfacing.
 The components are transceivers, latches, 8284 clock generator, 74138
decoder, memory and i/o devices present in the system.
 The address bus of 8086 is 20 bits long. By this we can access 2 20 byte
memory i.e. 1MB.
 Out of 20 bits, 16 bits A0 to A15 (or 16 lines) are multiplexed with data bus.

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 By multiplexing, i.e. they will act as address lines during the first T-state of
the machine cycle and in the rest of T-states, they act as data lines. A 16 to
A19 are multiplexed S3 to S6 and BHE’ is multiplexed with S7.
Control signals provided by 8086 for memory operations and i/o
interfacing:
1) They are used to identifying whether the bus is carrying a valid address
or not.
2) In which direction data is needed to be transferred over the bus,
3) When to write data on to memory location and when to put read data on
the system bus.

Min mode circuit

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8282 (8 bits) latch:
 The latches are buffered D-FF.
 They are used to separate the valid address from the multiplexed
Address/data bus by using the control signal ALE, which is connected to
strobe(STB) of 8282.
 The ALE is active HIGH signal.
 Here three such latches are required because the address is 20 bits.
8286 (8 bits) transceivers:
 They are bidirectional buffers and also known as data amplifiers.
 They are used to separate the valid data from multiplexed add/data bus.
 Two such transceivers are needed because the data bus is 16 bits long.
 8286 is connected to DT/R’ and DEN’ signals.
 They are enabled through the DEN signal .
 The direction of data on the data bus is controlled by the DT/R’ signal.
 DT/R’ is connected to T and DEN’ is connected to OE’.

Fig: Direction of data flow

8284 clock generator:
 8284 clock generator is used to provide the clock.
 M/IO’= 1, then I/O transfer is performed over the bus.
And when M/IO’ = 0, then I/O operation is performed.
 The signals RD’ and write WR’ are used to identify whether a read bus cycle
or a write bus cycle is performing.
When WR’ = 0, then it indicates that valid output data on the data bus.
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 RD’ indicates that the 8086 is performing a read data or instruction fetch
process is occurring .During read operations, one other control signal is also
used, which is DEN ( data enable) and it indicates the external devices when
they should put data on the bus.
 Control signals for all operations are generated by decoding M/IO’, RD’, WR’.
They are decoded by 74138 3:8 decoder.

INTR and INTA:

 When INTR = 1, then there is an interrupt to 8086 by other devices for
their service.
When INTA’= 0,then it indicates that the processor is ready to service
them.
 The bus request is made by other devices using the HOLD signal and the
processor acknowledges them using the HLDA output signal.
 All kinds of memory and i/o operations are performed using the decoding
of M/IO’and RD’ WR’ as shown in the table above.

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Maximum mode configuration of 8086 microprocessor (Min mode):
 In this mode, we can connect more processors to 8086 (8087/8089).
 8086 max mode is basically for implementation of allocation of global
resources and passing bus control to other coprocessor (i.e. second processor
in the system), because two processors cannot access system bus at same
instant.
 All processors execute their own program.
 The resources which are common to all processors are known as global
resources.
 The resources which are allocated to a particular processor are known as
local or private resources.

Fig: Maximum mode circuit

Circuit explanation:
 When MN/ MX’ = 0, 8086 works in max mode.

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 Clock is provided by 8284 clock generator.
 8288 bus controller- Address from the address bus is latched into 8282 8-
bit latch. Three such latches are required because address bus is 20 bit.
 The ALE(Address latch enable) is connected to STB(Strobe) of the
latch. The ALE for latch is given by 8288 bus controller.
 The data bus is operated through 8286 8-bit transceiver. Two such
transceivers are required, because data bus is 16-bit.
 The transceivers are enabled by the DEN signal, while the direction of data
is controlled by the DT/R signal. DEN is connected to OE’ and DT/ R’ is
connected to T. Both DEN and DT/ R’ are given by 8288 bus controller.

 Control signals for all operations are generated by decoding S’ 2, S’1 and
S’0 using 8288 bus controller.

 Bus request is done using RQ’ / GT’ lines interfaced with 8086. RQ 0/GT0 has
more priority than RQ1/GT1.
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 INTA’ is given by 8288, in response to an interrupt on INTR line of 8086.
 In max mode, the advanced write signals get enabled one T-state in advance
as compared to normal write signals. This gives slower devices more time to
get ready to accept the data, therefore it reduces the number of cycles.
Advantages of max mode of 8086:
 It helps to interface more devices like 8087.This interface is also called
a closely coupled co-Processor configuration. In this 8086 is called as the
host and 8087 as Co-processor.
 It supports multiprocessing, Therefore it helps to increase the efficiency.
 The 8087 was the first floating-point coprocessor for the 8086 series of
microprocessors. The purpose of the 8087 was to increase calculations for
floating point operations, such as add, sub, multiply, divide, and square
root.
Disadvantages of max mode over min mode:
 It has more complex circuit than min mode.
Applications of 8086:
 Microcomputer are built using 8086. For example: IBM PC, used the Intel
8088, a version of the 8086 with 8-bit data bus.
 It is used in calculators.
 It is used for control purposes like in traffic signals (uses micro controllers
which are nothing but contains one or more CPUs along with memory and
programmable i/o peripherals).
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 Timing Diagram of 8086 processor for READ/WRITE Operations in
MINIMUM MODE:
The working of min mode can be easily understood by timing diagrams.

 All processors bus cycle is of at least 4 T-states (T1,T2,T3,T4).

 The address is given by processor in the T1 state. It is available on the bus
for one T-state.
 In T2, the bus is tristated for changing the direction of the bus ( in the case of a
data read cycle.)
 The data transfer takes place between T3 and T4.
 If the addressed device is slower, then the wait state is inserted between T 3 and
T4.

Opcode fetch or read timing diagram:

 At T1 state ALE =1, this indicates that a valid address is latched on the address
bus and also M / IO’= 1, which indicates the memory operation is in progress.
 In T2 state, the address is removed from the local bus and is sent to the
addressed device. Then the bus is tristated.
 When RD’ = 0, the valid data is present on the data bus.
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  During T2, DEN’ =0, which enables transceivers and DT/R’ = 0 ,which indicates
that the data is received.
 During T3, data is put on the data bus and the processor reads it.
 The output device makes the READY line high. This means the output device
has performed the data transfer process.
 When the processor makes the read signal to 1, then the output device will
again tristate its bus drivers.

Write memory cycle:

 At T1 state, ALE =1, this indicates that a valid address is latched on the address
bus and also M / IO’= 1, which indicates the memory operation is in progress.
 In T2 state, the processor sends the data to be written to the addressed location.
 The data is buffered on the bus until the middle of T4 state.
 The WR’=0 becomes at the beginning of T2.
 The BHE’ and A0 signals are used to select the byte or bytes of memory or I/O
word.
 During T2, DEN’ =0, which enables, transceivers and DT/R’ = 1 ,which indicates
that the data is transferred by the processor to the addressed device.
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