Pin diagram :

Certainly! The 8086 microprocessor is a significant chip introduced by Intel in 1978. It’s a 16-bit
microprocessor with a 40-pin Dual Inline Package (DIP). Let’s break down the pin diagram and
its functions in a simple manner:

Power Supply and Frequency Pins:

 Vcc (Pin 40): Connects to a +5V power supply.

 GND (Pins 1 and 20): Ground pins.
 CLK (Pin 19): Provides the clock signal with frequencies of 5, 8, or 10 MHz, depending
on the version.

Data and Address Bus Pins:

 AD0-AD15 (Pins 2-16, 39): These are multiplexed address/data lines. Initially, they carry
the 16-bit address; after that, they carry data. AD0-AD7 represent the lower byte, and
AD8-AD15 the higher byte.

Status and Control Pins:

 A16-A19/S3-S6 (Pins 23-25, 31): High order address lines multiplexed with status
signals.
 BHE/S7 (Pin 34): Bus High Enable indicates if the high byte (D8-D15) of the data bus is
being used. It’s active low.
 RD (Pin 32): Read signal, active low, indicates the processor is reading from memory or
I/O.
 READY (Pin 22): Acknowledgement from the peripheral that it’s ready for data transfer.

Interrupt Pins:

 INTR (Pin 18): Interrupt request, sampled during the last clock cycle of each instruction.
 NMI (Pin 17): Non-maskable interrupt, triggers a type II interrupt.

Miscellaneous Pins:

 RESET (Pin 21): Resets the processor, clearing the instruction queue.
 TEST (Pin 23): Used for wait operation, active high.
 MN/MX (Pin 33): Minimum/Maximum mode selection.
 INTA (Pin 24): Interrupt acknowledge.
 ALE (Pin 25): Address Latch Enable, indicates that the address bus holds a valid
address.
 DEN (Pin 26): Data Enable, used for data transceiver control.
The 8086 operates in two modes: Minimum mode (single microprocessor configuration) and
Maximum mode (multiple microprocessors configuration), which can be set using the MN/MX
pin.

The pin diagram is quite complex, but understanding the function of each pin can help you grasp
how the 8086 interfaces with other components in a system. For a more visual representation,
you can refer to detailed diagrams and explanations available online12. Remember, the
multiplexed nature of the address/data bus means that the same pins are used to transmit both
addresses and data, just at different times during the operation cycle.

2.

AD0-AD15: Address/Data bus. These are low order address bus. They are
multiplexed with data. When AD lines are used to transmit memory address the
symbol A is used instead of AD, for example A0-A15. When data are transmitted
over AD lines the symbol D is used in place of AD, for example D0-D7, D8-D15 or
D0-D15.
A16-A19: High order address bus. These are multiplexed with status signals.
S2, S1, S0: Status pins. These pins are active during T4, T1 and T2 states and is
returned to passive state (1,1,1 during T3 or Tw (when ready is inactive). These are
used by the 8288 bus controller for generating all the memory and I/O operation)
access control signals. Any change in S2, S1, S0 during T4 indicates the beginning
of a bus cycle.
S2 S1 S0 Characteristics

Interrupt
0 0 0
acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory
S2 S1 S0 Characteristics

1 1 1 Passive state

A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with
corresponding status signals.
A17/
S4 A16/S3 Function

0 0 Extra segment access

Stack segment
0 1
access

1 0 Code segment access

1 1 Data segment access

HE’/S7: Bus High Enable/Status. During T1 it is low. It is used to enable data onto
the most significant half of data bus, D8-D15. 8-bit device connected to upper half
of the data bus use BHE (Active Low) signal. It is multiplexed with status signal S7.
S7 signal is available during T2, T3 and T4.
RD’: This is used for read operation. It is an output signal. It is active when low.
READY : This is the acknowledgement from the memory or slow device that they
have completed the data transfer. The signal made available by the devices is
synchronized by the 8284A clock generator to provide ready input to the
microprocessor. The signal is active high(1).
INTR : Interrupt Request. This is triggered input. This is sampled during the last
clock cycles of each instruction for determining the availability of the request. If any
interrupt request is found pending, the processor enters the interrupt acknowledge
cycle. This can be internally masked after resulting the interrupt enable flag. This
signal is active high(1) and has been synchronized internally.
NMI : Non maskable interrupt. This is an edge triggered input which results in a
type II interrupt. A subroutine is then vectored through an interrupt vector lookup
table which is located in the system memory. NMI is non-maskable internally by
software. A transition made from low(0) to high(1) initiates the interrupt at the end
of the current instruction. This input has been synchronized internally.
INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each
interrupt acknowledge cycle.
MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor
will operate in.

RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters
used to force the microprocessor to release the local bus at the end of the
microprocessor’s current bus cycle. Each of the pin is bi-directional. RQ’/GT0′ have
higher priority than RQ’/GT1′.
LOCK’ : Its an active low pin. It indicates that other system bus masters have not
been allowed to gain control of the system bus while LOCK’ is active low(0). The
LOCK signal will be active until the completion of the next instruction.

TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0),
execution will continue, else the processor remains in an idle state. The input is
internally synchronized during each of the clock cycle on leading edge of the clock.
CLK : Clock Input. The clock input provides the basic timing for processing
operation and bus control activity. Its an asymmetric square wave with a 33% duty
cycle.
RESET : This pin requires the microprocessor to terminate its present activity
immediately. The signal must be active high(1) for at least four clock cycles.
Vcc : Power Supply( +5V D.C.)
GND : Ground
QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086
instruction queue according to the table shown below:
QS1 QS0 Status

0 0 No operation

First byte of op code from

0 1
queue

1 0 Empty the queue

1 1 Subsequent byte from queue

M/IO’: This signal is used to distinguish between memory and I/O operations. The
M Signal is Active high whereas the IO’ Signal is Active Low. When this Pin is
High, the memory operations takes place. On the other hand, when the Pin is low,
the Input/Output operations from the peripheral devices takes place.
=DT/R : Data Transmit/Receive. This pin is required in minimum systems, that
want to use an 8286 or 8287 data bus transceiver. The direction of data flow is
controlled through the transceiver.

DEN: Data enable. This pin is provided as an output enable for the 8286/8287 in a
minimum system which uses transceiver. DEN is active low(0) during each memory
and input-output access and for INTA cycles.
HOLD/HOLDA: HOLD indicates that another master has been requesting a local
bus .This is an active high(1). The microprocessor receiving the HOLD request will
issue HLDA (high) as an acknowledgement in the middle of a T4 or T1 clock cycle.

ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the
address into the 8282 or 8283 address latch. It is an active high(1) pulse during T1 of
any bus cycle. ALE signal is never floated, is always integer.

Block diagram:
Sure, let’s simplify the block diagram of the 8086 microprocessor. The 8086 consists of two
main parts: the Bus Interface Unit (BIU) and the Execution Unit (EU). Here’s a
straightforward explanation of each:

Bus Interface Unit (BIU):

 Purpose: Handles all data and address transfers on the buses for the EU and interfaces
with memory and I/O devices.
 Components:
o Instruction Queue: Stores up to six bytes of the next instructions to be executed,
which speeds up processing.
o Segment Registers: Help in addressing memory by dividing it into segments.
There are four segment registers: CS (Code Segment), DS (Data Segment), SS
(Stack Segment), and ES (Extra Segment).
o Instruction Pointer: Holds the address of the next instruction to be executed.

Execution Unit (EU):

 Purpose: Decodes and executes instructions.

 Components:
o Control Circuitry: Decodes instructions and generates signals to control data
flow and operations.
o Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations.
o General Purpose Registers: Used for various functions like arithmetic
operations and addressing. They can be combined or used individually as 8-bit or
16-bit registers. These include AX, BX, CX, and DX.
 o Flag Register: Contains flags that indicate the status of operations and control
certain operations.

The BIU and EU work together to execute instructions: the BIU fetches instructions and passes
them to the EU, which then decodes and executes them. The use of segmented memory allows
the 8086 to access a large memory space, and the instruction queue helps in speeding up the
execution process by pre-fetching instructions.

This is a high-level overview, but for a more detailed understanding, including the specific roles
of each register and how they interact, you might want to look at visual diagrams and in-depth
explanations available in resources like textbooks or online articles12. Remember, the 8086 is a
complex piece of hardware, and its block diagram represents the intricate workings of its internal
architecture.

Describe how 20 bit Physical address is generated in

8086 microprocessor with suitable example.
In the 8086 microprocessor, the 20-bit physical address is generated by combining a 16-bit
segment register with a 16-bit offset register. This is done through a process called
segmentation, which allows the microprocessor to access a memory space larger than what a
single 16-bit register could address.

Here’s how the 20-bit physical address is calculated:

1. The 16-bit segment register is shifted left by 4 bits (which is equivalent to multiplying it
by 16 or 10H in hexadecimal).
2. The 16-bit offset register is then added to this shifted value to get the final 20-bit physical
address.

Let’s take an example to illustrate this:

Suppose we have the following values:

 Code Segment (CS) Register: 1234H

 Instruction Pointer (IP) Register: 5678H

The physical address would be calculated as follows:

\text{Physical Address} = (\text{CS} \times 10H) + \text{IP}

= (1234H \times 10H) + 5678H

= 12340H + 5678H

= 179B8H
So, the 20-bit physical address where the instruction pointed by the IP would be fetched from is
179B8H.

This segmentation mechanism allows the 8086 microprocessor to access up to 1MB of memory,
which is significantly more than the 64KB limit imposed by a single 16-bit register.

Define Logical and Effective address. Describe how 20 bit Physical

address is generated in 8086. If CS = 348AH and IP = 4214H,
calculate the Physical Address.
In the context of the 8086 microprocessor, a Logical Address refers to the address used by the
program to access memory. It’s not an actual memory location but rather an offset from a
segment base within the program’s address space. The logical address consists of two parts: the
segment part and the offset part.

An Effective Address (EA) or Offset Address is the offset for a memory operand within a
segment. It’s the displacement from the base address of the segment to the actual memory
location where data or instructions are stored. The effective address is calculated using the
segment register and the offset address as follows:

\text{Effective Address} = \text{Segment Register} + \text{Offset Address}

Now, let’s move on to the Physical Address. The 8086 microprocessor generates a 20-bit
physical address by combining a 16-bit segment register with a 16-bit offset register. This is
done through segmentation, which allows the processor to access a larger memory space. The
physical address is calculated by shifting the segment register 4 bits to the left (multiplying by
10H) and then adding the offset address:

\text{Physical Address} = (\text{Segment Register} \times 10H) + \text{Offset Address}

For the given values of CS (Code Segment) and IP (Instruction Pointer):

 CS: 348AH
 IP: 4214H

The physical address would be calculated as:

\text{Physical Address} = (348AH \times 10H) + 4214H

After performing the multiplication and addition, we get:

\text{Physical Address} = 348A0H + 4214H = 38AB4H

Explain memory segmentation in 8086 and list its
advantages.
Memory segmentation in the 8086 microprocessor is a system that divides the computer’s
memory into segments, each with its own specific function. This approach allows for more
efficient and flexible memory management. Here’s a simplified explanation:

Memory Segmentation in 8086:

 Segment Registers: The 8086 uses four segment registers—Code Segment (CS), Data
Segment (DS), Stack Segment (SS), and Extra Segment (ES)—to divide the memory into
segments.
 Logical Address: Consists of a segment selector (from one of the segment registers) and
an offset value, which together point to a specific memory location within a segment.
 Physical Address: Calculated by shifting the segment selector 4 bits to the left
(multiplying by 16) and adding the offset. This allows the 8086 to access up to 1MB of
memory.

Advantages of Memory Segmentation:

1. Enhanced Memory Management: Segmentation provides a powerful mechanism for

managing memory, making it easier for the processor to fetch and execute data.
2. Separation of Concerns: Different types of operations (data, stack, code) can be
performed in different segments, improving organization and efficiency.
3. Shared Data: Processes can easily share data by accessing the same data segments.
4. Extended Addressability: Using 16-bit registers, segmentation allows the processor to
address up to 1MB of memory, which would otherwise require 20-bit registers.
5. Protection: Segments can have different access rights, providing a level of protection
and security for the code and data.

These advantages make segmentation a key feature of the 8086 architecture, allowing it to
handle complex tasks and memory operations effectively123. It’s important to note that while
segmentation offers many benefits, it also introduces additional complexity to the memory
management process. However, the flexibility and control it provides outweigh the complexity
for most applications.

Tools
editor
•It is the program which allows you to create a file containingthe assembly
language statements for your program.
•Examples

are PC Write, Word stars and the editors thatcomes with assemblers.

•Creates Source file to be processed by the assembler

• As you type in your program, the editor stores the ASCIIcodes for the letters and
numbers in successive RAM

•When you have typed in all your program, you then save thefile on the hard disk.
This file is called source file and the extension is .asm.