MP Note Class 10

Prepared BY: BP BHATTA
Unit: 1
Introduction
Introduction:
A Microprocessor is a multipurpose programmable, clock driven, register based electronic device that
reads binary instructions from a storage device called memory, accepts binary data as input, processes
data according to those instructions and provide result s as output. The microprocessor operates in
binary 0 and 1 known as bits are represented in terms of electrical voltages in the machine that means 0
represents low voltage level and 1 represents high voltage level. Each microprocessor recognizes and
processes a group of bits called the word and microprocessors are classified according to their word
length such as 8 bits microprocessor with 8 bit word and 32 bit microprocessor with 32 bit word etc.
Fig: Block Diagram of Microprocessor
It is clock driven semiconductor device consisting of electronic logic circuits manufactured by using
either a large scale integration (LSI) or very large scale integration (VLSI) technique. It is capable of
performing various computing functions and making decisions to change the sequence of program
execution. It can be divided in to three segments.
A) Arithmetic/Logic unit: It performs arithmetic operations as addition and subtraction and logic
operations as AND, OR & XOR.
B) Register Array: The registers are primarily used to store data temporarily during the execution of a
program and are accessible to the user through instruction. The registers can be identified by letters
such as B, C, D, E, H and L.
C) Control Unit: It provides the necessary timing and control signals to all the operations in the
microcomputer. It controls the flow of data between the microprocessor and memory & peripherals.
Memory:
Memory stores binary information such as instructions and data, and provides that information to the
up whenever necessary. To execute programs, the microprocessor reads instructions and data from
memory and performs the computing operations in its ALU. Results are either transferred to the
output section for display or stored in memory for later use. Memory has two sections.
A. Read only Memory (ROM): Used to store programs that do not need alterations and can only read.
B. Read/Write Memory (RAM): Also known as user memory which is used to store user programs and
data. The information stored in this memory can be easily read and altered.
Input/output:
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• It communicates with the outside world using two devices input and output which are
also Known as peripherals.
• The input device such as keyboard, switches, and analog to digital converter transfer
binary information from outside world to the microprocessor.
• The output devices transfer data from the microprocessor to the outside world. They
include the devices such as LED, CRT, digital to analog converter, printer etc.
System Bus:
It is a communication path between the microprocessor and peripherals; it is nothing but a
group of wires to carry bits.
Applications of Microprocessors:
• Microcomputer: Microprocessor is the CPU of the microcomputer.
• Embedded system: Used in microcontrollers.
• Measurements and testing equipment: used in signal generators, oscilloscopes, counters,
digital voltmeters, x-ray analyzer, blood group analyzers baby incubator, frequency
synthesizers, data acquisition systems, spectrum analyzers etc.
• Scientific and Engineering research.
• Industry: used in data monitoring system, automatic weighting, batching systems etc.
• Security systems: smart cameras, CCTV, smart doors etc.
• Automatic system
• Communication system Some Examples are:
– Calculators
– Accounting system
– Games machine
– Complex Industrial Controllers
– Traffic light Control
– Data acquisition systems
– Military applications
Evolution of Microprocessor:
4-bit Microprocessors :The first microprocessor was introduced in 1971 by Intel Corp. It was named
Intel 4004 as it was a 4 bit processor. It was a processor on a single chip. It could perform simple
arithmetic and logic operations such as addition, subtraction, Boolean AND ,and Boolean OR. It had a
control unit capable of performing control functions like fetching an instruction from memory,
decoding it, and generating control pulses to execute it. It was able to operate on 4 bits of data at a
time. This first microprocessor was quite a success in industry. Soon other microprocessors were also
introduced. Intel introduced the enhanced version of 4004, the 4040.
8-bit Microprocessors: The first 8 bit microprocessor which could perform arithmetic and logic
operations on 8 bit words was introduced in 1973 again by Intel. This was Intel 8008 and was later
followed by an improved version, Intel 8088. Some other 8 bit processors are Zilog-80 and Motorola
M6800.
16-bit Microprocessors: The 8-bit processors were followed by 16 bit processors. They are Intel
8086 and 80286.
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32-bit Microprocessors: The 32 bit microprocessors were introduced by several companies but the
most popular one is Intel 80386.
Pentium Series : Instead of 80586, Intel came out with a new processor namely Pentium processor.
Its performance is closer to RISC performance. Pentium was followed by Pentium Pro CPU. Pentium Pro
allows multiple CPUs in a single system in order to achieve multiprocessing. The MMX extension was
added to Pentium Pro and the result was Pentium II.
Von-Neumann Architecture:
The simplest way to organize a computer is to have one processor, register and instruction code format
with two parts op-code and address/operand. The memory address tells the control where to find an
operand in memory. This operand is read from memory and used as data to be operated on together
with the data stored in the processor register. Instructions are stored in one section of same memory.
It is called stored program concept.
The task of entering and altering the programs for ENIAC was tedious. It could be facilitated if the
program could be represented in a form suitable for storing in memory alongside the data. So the
computer could get its instructions by reading from the memory and program could be set or altered
by setting the values of a portion of memory. This approach is known as 'stored- program concept' was
first adopted by John Von Neumann and such architecture is named as von-Neumann architecture and
shown in figure below.
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Fig: Von- Neumann Architecture

The main memory is used to stare both data and instructions. The arithmetic and logic unit is capable of
performing arithmetic and logical operation on binary data. The program control unit interprets the
instruction in memory and causes them to be executed. The I/O unit gets operated from the control
unit.
The Von–Neumann architecture is the fundamental basis for the architecture of modern digital
computers. It consisted of 1000 storage locations which can hold words of 40 binary digits and both
instructions as well as data are stored in it.
Microcomputer Organization:
Types Of Microprocessor:
Complex Instruction Set Microprocessors
The short term of Complex Instruction Set Microprocessors is CISM and they classify a microprocessor in
which orders can be performed together along with other low level activities. These types of processors
performs the different tasks like downloading, uploading, recalling data into the memory card and
recalling data from the memory card. Apart from these tasks, it also does complex mathematical
calculations in a single command.
Reduced Instruction Set Microprocessor
The short term of Reduced Instruction Set Microprocessor is RISC. These types of processors are made
according to the function in which the microprocessor can carry out small things in specific command.
In this way these processors completes more commands at a faster rate.
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Unit:2
Components of Microprocessor
The basic components of a microcomputer are:
Some of the common components of a microprocessor are:
• Control Unit
• I/O Units
• Arithmetic Logic Unit (ALU)
• Registers
• Cache
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Control Unit
It provides necessary timing and control signals necessary to all the operations in the microcomputer. It
controls the flow of data between microprocessor and peripherals (input, output and memory). The
control unit gets a clock which determines the speed of the microprocessor.
The CPU has three basic functions:
1. It fetches an instructions word stored in memory.
2. It determines what the instruction is telling it to do. (decodes the instruction)
3. It executes the instruction. Executing the instruction may include some of the following major
tasks.
• Transfer of data from reg. to reg. in the CPU itself.
• Transfer of data between a CPU reg. and specified memory location.
• Performing arithmetic and logical operations on data from a specified memory location.
• Directing the CPU to change a sequence of fetching instruction.
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4. It looks for control signal such as interrupts and provides appropriate responses.
5. It provides states, control, and timing signals that the memory and input/output section
can use.
I/O Units
A processor needs to be able to communicate with the rest of the computer system. This
communication occurs through the I/O ports. The I/O ports will interface with the system memory
(RAM), and also the other peripherals of a computer.
Arithmetic Logic Unit
The Arithmetic Logic Unit or ALU is the part of the microprocessor that performs arithmetic operations.
ALUs can typically add, subtract, divide, multiply, and perform logical operations of two numbers (and,
or, nor, not, etc).
Register Unit:
It contains various register. The registers are used primarily to store data temporarily during the
execution of a program.
Memory Unit:
Memory is the best essential element of a computer because computer can’t perform simple tasks. The
performance of computer mainly based on memory and CPU. Memory is internal storage media of
computer that has several names such as majorly categorized into two types, Main memory and
Secondary memory.
1. Primary Memory / Volatile Memory.
2. Secondary Memory / Non Volatile Memory.
1. Primary Memory / Volatile Memory:

Primary Memory also called as volatile memory because the memory can’t store the data permanently.
Primary memory select any part of memory when user want to save the data in memory but that may
not be store permanently on that location. It also has another name i.e. RAM.
Random Access Memory (RAM):

The primary storage is referred to as random access memory (RAM) due to the random selection of
memory locations. It performs both read and writes operations on memory. If power failures happened
in systems during memory access then you will lose your data permanently. So, RAM is volatile memory.
RAM categorized into following types.
 DRAM
 SRAM
2. Secondary Memory / Non Volatile Memory:

Secondary memory is external and permanent memory that is useful to store the external storage media
such as floppy disk, magnetic disks, magnetic tapes and etc cache devices. Secondary memory deals with
following types of components.
Read Only Memory (ROM):
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ROM is permanent memory location that offers huge types of standards to save data. But it work with
read only operation. No data lose happen whenever power failure occurs during the ROM memory work
in computers.
ROM memory has several models such names are following.
1. PROM: Programmable Read Only Memory (PROM) maintains large storage media but can’t
offer the erase features in ROM. This type of RO maintains PROM chips to write data once and
read many. The programs or instructions designed in PROM can’t be erased by other programs.
2. EPROM : Erasable Programmable Read Only Memory designed for recover the problems of
PROM and ROM. Users can delete the data of EPROM thorough pass on ultraviolet light and it
erases chip is reprogrammed.
3. EEPROM: Electrically Erasable Programmable Read Only Memory similar to the EPROM but it
uses electrical beam for erase the data of ROM.
Cache Memory: Main memory less than the access time of CPU so, the performance will
decrease through less access time. Speed mismatch will decrease through maintain cache
memory. Main memory can store huge amount of data but the cache memory normally kept
small and low expensive cost. All types of external media like Magnetic disks, Magnetic drives
and etc store in cache memory to provide quick access tools to the users.
The microprocessor MPU performs various operations with peripheral devices or a memory
location by using three sets of communication lines called buses: the address bus, the data bus
and the control bus. And these three combined lines is called as system bus.
The 8085 Bus Structure
Address bus:
The address bus is a group of 16 lines generally called as A0 – A15 to carry a 16-bit address of
memory location.
In a computer system, each peripheral or memory location is identified by a binary number
called an address. This is similar to the postal address of a house.
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The address bus is unidirectional, that means bit flow in only one direction from MPU to
peripheral.
MPU carries 16-bit address i.e. 216 = 65,536 or 64K memory locations.
Data Bus:
The data bus is a group of eight bidirectional lines used for data flow in both the directions
between MPH and peripheral devices.
The 8 data lines are manipulating 8-bit data ranging from 00 to FF i.e. (28 = 256) numbers from
0000 0000 -1111 1111
This 8 bit data is called as word length and the register size of a microprocessor and MPH is
called 8–bit microprocessor.
Control bus:
Control bus is having various single lines used for sending control signals in the form of pulse to
the memory and I/O devices.
The MPU generates specific control signals to perform a particular operations. Some of these
control signals are memory read, memory write, I/O read and I/O write.
To write a byte into a memory location

1. Places the 16-bit address on the address bus of the memory location where a byte is to
be stored .This address is decoded to select the memory chip, and the memory register
is identified.
2. Places the byte on the data bus.
3. Sends the control signal memory write to enable the input buffers of the memory and
then stores the byte.
To read from memory, the steps are similar.

1-The MPU places the 16-bit address on the address bus and sends the control signal memory
read to enable the output buffer of the memory chip.
2-The interfacing logic of the memory chip decodes the address and selects the appropriate
memory register.
3-The memory chip places the data byte on the data bus, and the MPU reads the data byte.
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Unit: 3
Instruction Cycle
Instruction cycle:
Instruction contains in the program and is pointed by the program counter. It is first moved to the
instruction register and is decoded in binary form and stored as an instruction in the memory. The
computer takes a certain period to complete this task i.e., instruction fetching, decoding and executing
on the basis of clock speed. Such a time period is called ‘Instruction cycle’ and consists two cycles
namely fetch and decode and Execute cycle.
In the fetch cycle the central processing unit obtains the instruction code the memory for its execution.
Once the instruction code is fetched from memory, it is then executed. The execution cycle consists the
calculating the address of the operands, fetching them, performing operations on them and finally
outputting the result to a specified location.
Machine cycle:
The steps performed by the computer processor for each machine language instruction
received. The machine cycle is a 4 process cycle that includes reading and interpreting the
machine language, executing the code and then storing that code.
Timing Diagram:
It is one of the best way to understand to process of micro-processor/controller. With the help of timing
diagram we can understand the working of any system, step by step working of each instruction and its
execution, etc.
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It is the graphical representation of process in steps with respect to time. The timing diagram represents
the clock cycle and duration, delay, content of address bus and data bus, type of operation i.e.
Read/write/status signals.
T-state: Each clock cycle is called as T-states.

Rules to identify number of machine cycles in an instruction:
1. If an addressing mode is direct, immediate or implicit then No. of machine cycles = No. of
bytes.
2. If the addressing mode is indirect then No. of machine cycles = No. of bytes + 1. Add +1 to the
No. of machine cycles if it is memory read/write operation.
3. If the operand is 8-bit or 16-bit address then, No. of machine cycles = No. of bytes +1.
4. These rules are applicable to 80% of the instructions of 8085.
Opcode fetch(4T):
• The microprocessor requires instructions to perform any particular action. In order to
perform these actions microprocessor utilizes Opcode which is a part of an instruction
which provides detail(i.e. Which operation µp needs to perform) to microprocessor.
Memory Read Cycle (3T):

This machine cycle is required when an operand is present in memory. This machine
cycle requires three T-states. The following are the sequence of actions performed by
microprocessor during this machine cycle.
• In the first T-state (T1) 8085 places address on address bus and issues ALE signal. And also
IO/M’ signal is made low, since it is memory related operation.
• In the second T-state (T2), processor issues RD’ control signal to memory. In response to this
memory places data on data bus.
• In the third T-state (T3), processor reads data from data bus, and de-asserts RD’ signal.
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Memory Write cycle (3T):

This machine cycle is required when the results of operation needs to store in memory. This machine
cycle requires three T-states. The following are sequence of actions performed by processor in this
machine cycle.
• In first T-state (T1), 8085 processor places 16- bit address on address bus and issues ALE signal.
And also it makes IO/M’ signal to low, indicating it is memory related operation.
• In second T-state (T2), processor places data to be written on data bus and asserts WR’ signal to
the memory.
• In the third T-state (T3), memory stores the data and processor de-asserts WR’ signal.
IO Read Machine Cycle:

This machine cycle is required, when data needs to be read from an input device. This machine cycle
requires three T-states. The following are the sequence of actions performed by processor during this
machine cycle.
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• In the first T-state (T1) 8085 places port address(for IO mapped addresses port address is 8-bit,
but for memory mapped addresses IO device address is 16-bit, but reading from such is
performed by memory read machine cycle) on address bus and issues ALE signal. And also IO/M’
signal is made high, since it is IO related operation.
• In the second T-state (T2), processor issues RD’ control signal to IO peripheral. In response to
this input device places data on data bus.
• In the third T-state (T3), processor reads data from data bus, and de-asserts RD’ signal.
IO Write Machine Cycle:

This machine cycle is required when data needs to be output to an output device. This machine cycle
requires three T-states. The following are the sequence of actions performed by processor during this
machine cycle.
• In first T-state (T1), 8085 processor places 8-bit port address on address bus (for IO mapped
addresses port address is 8-bit, but for memory mapped addresses, IO device address is 16-bit,
but writing to such is performed by memory write machine cycle) and issues ALE signal. And also
it makes IO/M’ signal to high, indicating it is IO related operation.
• In second T-state (T2), processor places data to be written on data bus and asserts WR’ signal to
the peripheral.
• In the third T-state (T3), peripheral accepts the data and processor de-asserts WR’ signal.
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Timing Diagram of following instruction:

i) MOV A,B
ii) MVI B,43H
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iii) IN C0H
iv) OUT
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v) STA 526AH
vi) LDA
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Unit : 4
Intel 8085 Microprocessor
The Intel 8085 A is a complete 8 bit parallel central processing unit. The main components of
8085A are array of registers, the arithmetic logic unit, the encoder/decoder, and timing and
control circuits linked by an internal data bus. The block diagram is shown below:
1: ALU: - The arithmetic logic unit performs the computing functions, it includes the accumulator,
the temporary register, the arithmetic and logic circuits and five flags. The temporary register is
used to hold data during an arithmetic/logic operation. The result is stored in the accumulator; the
flags (flip-flops) are set or reset according to the result of the operation.
2. Accumulator (register A): It is an 8 bit register that is the part of ALU. This register is used to
store the 8-bit data and to perform arithmetic and logic operations and 8085 microprocessor is
called accumulator based microprocessor. When data is read from input port, it first moved to
accumulator and when data is sent to output port, it must be first placed in accumulator.
3. Temporary registers(W & Z): They are 8 bit registers not accessible to the programmer. During
program execution, 8085A places the data into it for a brief period.
4. Instruction register(IR): It is a 8 bit register not accessible to the programmer. It receives the
operation codes of instruction from internal data bus and passes to the instruction decoder which
decodes so that microprocessor knows which type of operation is to be performed.
5. Register Array: (Scratch pad registers B, C, D, E): It is a 8 bit register accessible to the
programmers. Data can be stored upon it during program execution. These can be used
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individually as 8-bit registers or in pair BC, DE as 16 bit registers. The data can be directly added or
transferred from one to another. Their contents may be incremented or decremented and
combined logically with the content of the accumulator.
Register H & L: - They are 8 bit registers that can be used in same manner as scratch pad registers.
Stack Pointer (SP): - It is a 16 bit register used as a memory pointer. It points to a memory location
in R/W memory, called the stack. The beginning of the stack is defined by loading a 16bit address
in the stack pointer.
Program Counter (PC): - Microprocessor uses the PC register to sequence the execution of the
instructions. The function of PC is to point to the memory address from which the next byte is to
be fetched. When a byte is being fetched, the PC is incremented by one to point to the next
memory location.
6. Flags:
Register consists of five flip flops, each holding the status of different states separately is known as
flag register and each flip flop are called flags. 8085A can set or reset one or more of the flags and
are sign(S), Zero (Z), Auxiliary Carry (AC) and Parity (P) and Carry (CY). The state of flags indicates
the result of arithmetic and logical operations, which in turn can be used for decision making
processes. The different flags are described as:
• Carry: - If the last operation generates a carry its status will 1 otherwise 0. It can handle
the carry or borrow from one word to another.
• Zero: - If the result of last operation is zero, its status will be 1 otherwise o. It is often used
in loop control and in searching for particular data value.
• Sign: - If the most significant bit (MSB) of the result of the last operation is 1 (negative),
then its status will be 1 otherwise 0.
• Parity: - If the result of the last operation has even number of 1’s (even parity), its status
will be 1 otherwise 0.
• Auxiliary carry: - If the last operation generates a carry from the lower half word (lower
nibble), its status will be 1 otherwise 0. Used for performing BCD arithmetic.
7. Timing and Control Unit:
This unit synchronizes all the microprocessor operations with the clock and generates the control
signals necessary for communication between the microprocessor and peripherals. The control
signals are similar to the sync pulse in an oscilloscope. The signals are sync pulses indicating the
availability of data on the data bus.
8. Interrupt controls:
The various interrupt controls signals (INTR, RST 5.5, RST 6.5, RST 7.5 and TRAP) are used to
interrupt a microprocessor.
9. Serial I/O controls: Two serial I/O control signals (SID and SOD) are used to implement the serial
data transmission.
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Characteristics (features) of 8085A microprocessor and its signals
The 8085A (commonly known as 8085) is a 8-bit general purpose microprocessor capable of
addressing 64K of memory. The device has 40 pins, require a +5V single power supply and can
operate with a 3-MHZ, single phase clock.
The all the signals associated with 8085 can be classified into 6 groups:
1: Address bus: The 8085 has 16 signal lines that are used as the address bus; however, these lines
are split into two segments A15-A8 and AD7- AD0. The eight signals A15-A8 are unidirectional and
used as high order bus.
2. Data bus: The signal lines AD7- AD0 are bidirectional, they serve a dual purpose. They are used
the low order address bus as well as data bus.
3. Control and status signals: This group of signals includes two control signals ( and ), three status
signals (IO/ , S1 and S0) to identify the nature of the operation, and one special signals (ALE) to
indicate the beginning of the operation.
• ALE- Address Latch Enable: This is a positive going pulse generated every time the 8085
begins an operation (machine cycle): it indicates that the bits AD7-AD0 are address bits.
This signal is used primarily to latch the low-order address from the multiplexed bus and
generate a separate set of eight address lines A7 –A0.
• ��
𝑹𝑹𝑹𝑹 Read: this is a read control signal (active low). This signal indicates that the selected
I/O or memory device is to be read and data are available on the data bus.
�� Write: This is a write control signal (active low). This signal indicates that the data on
• 𝑾𝑾𝑾𝑾
the data bus are to be written into a selected memory or I/O location.
• 𝑰𝑰𝑰𝑰/𝑴𝑴 � : This is a status signal used to differentiate between I/O and memory operations.
When it is high , it indicates an I/O operation; When it is low indicates a memory operation.
�� (Read) and 𝑾𝑾𝑾𝑾
This signal is combined with 𝑹𝑹𝑹𝑹 �� (Write) to generate I/O and memory
signals.
• S1 and S0 : These status signals, similar to 𝑰𝑰𝑰𝑰/𝑴𝑴 � , can identify various operations, but they
are rarely used in small systems.
4. Power Supply and Clock frequency:
- VCC: +5V power supply
- VSS: Ground reference - X1 and X2: A crystal (RC or LC network) is connected at these two pins
for frequency.
- CLK OUT: It can be used as the system clock for other devices.
5. Externally Initiated signals:

-INTR (input): interrupt request, used as a general purpose interrupt.
- (Output): This is used to acknowledge an Interrupt.
-RST 7.5, 6.5, 5.5 (inputs): These are vectored interrupts that transfer the program control to
specific memory locations. They have higher priorities than INTR interrupt. Among these three,
the priority order is 7.5, 6.5, and 5.5.
- TRAP (input): This is a non-maskable interrupt with highest priority.
-HOLD (input): This signal indicates that a peripheral such as a DMA( Direct Memory Access)
controller is requesting use of Address and data bus.
-HLDA (output): Hold Acknowledge: This signal acknowledges the HOLD request
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- READY (Input) : This signal is used to delay the microprocessor Read or Write cycles until a slow-
responding peripheral is ready to send or accept data. When this signal goes low, the
microprocessor waits for an integral number of clock cycles until it goes high.
��
𝑹𝑹𝑹𝑹𝑹𝑹𝑹𝑹𝑹𝑹 𝑰𝑰𝑰𝑰- : When the signal on this pin goes low, the program counter is set to zero, the buses
are tri-stated, and MPU is reset.
-RESET OUT: This signal indicates that the MPU is being reset. The signal can be used to reset
other devices.
Serial I/O ports: The 8085 has two signals to implement the serial transmission: SID (Serial Input
Data) and SOD (Serial Output Data). In serial transmission, data bits are sent over a single line, one
bit at a time, such as the transmission over telephone lines.
Instruction description and Format:
The computer can be used to perform a specific task, only by specifying the necessary steps to
complete the task. The collection of such ordered steps forms a ‘program’ of a computer. These
ordered steps are the instructions. Computer instructions are stored in central memory locations
and are executed sequentially one at a time. The control reads an instruction from a specific
address in memory and executes it. It then continues by reading the next instruction in sequence
and executes it until the completion of the program.
An instruction manipulates the data and a sequence of instructions constitutes a program.

Generally each instruction has two parts: one is the task to be performed, called the operation
code (Op-Code) field, and the second is the data to be operated on, called the operand or address
field. The operand (or data) can be specified in various ways. It may include 8-bit (or 16-bit) data,
an internal register, a memory location, or an 8-bit (or 16-bit) address. The Op-Code field specifies
how data is to be manipulated and address field indicates the address of a data item.
For example:
ADD R1, R0
Op-code address
Here R0 is the source register and R1 is the destination register. The instruction adds the contents
of R0 with the content of R1 and stores result in R1.
8085 A can handle at the maximum of 256 instructions (28) (246 instructions are used). The sheet
which contains all these instructions with their hex code, mnemonics, descriptions and function is
called an instruction sheet. Depending on the number of address specified in instruction sheet, the
instruction format can be classified into the categories.
• One address format (1 byte instruction): Here 1 byte will be Op-code and operand will be
default. E.g. ADD B, MOV A,B
• Two address format (2 byte instruction): Here first byte will be Op-code and second byte
will be the operand/data. E.g. IN 40H, MVI A, 8-bit Data
• Three address format (3 byte instruction): Here first byte will be Op-code, second and
third byte will be operands/data. That is
2nd byte- lower order data.
3rd byte – higher order data
E.g. LXI B, 4050 H
Micro operation specifies the transfer of data into or out of a register.
Classification of an instruction
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An instruction is a binary pattern designed inside a microprocessor to perform a specific function
(task). The entire group of instructions called the instruction set. The 8085 instruction set can be
classified in to 5- different groups.
• Data transfer group: The instructions which are used to transfer data from one register to
another register or register to memory.
• Arithmetic group: The instructions which perform arithmetic operations such as addition,
subtraction, increment, decrement etc.
• Logical group: The instructions which perform logical operations such as AND, OR, XOR,
COMPARE etc.
• Branching group: The instructions which are used for looping and branching are called
branching instructions like jump, call etc.
• Miscellaneous group: The instructions relating to stack operation, controlling purposes
such as interrupt operations are fall under miscellaneous group including machine control
like HLT, NOP.
Addressing modes:
Instructions are command to perform a certain task in microprocessor. The instruction consists of
op-code and data called operand. The operand may be the source only, destination only or both of
them. In these instructions, the source can be a register, a memory or an input port. Similarly,
destination can be a register, a memory location, or an output port. The various format (way) of
specifying the operands are called addressing mode. So addressing mode specifies where the
operands are located rather than their nature. The 8085 has 5 addressing mode:
1) Direct addressing mode: The instruction using this mode specifies the effective address as part
of instruction. The instruction size either 2-bytes or 3-bytes with first byte op-code followed by 1
or 2 bytes of address of data.
E. g. LDA 9500H A [9500]
IN 80H A [80]
This type of addressing is called absolute addressing.
2) Register Direct addressing mode: This mode specifies the register or register pair that contains
the data. E g. MOV A, B Here register B contains data rather than address of the data. Other
examples are: ADD, XCHG etc.
3) Register Indirect addressing mode: In this mode the address part of the instruction specifies
the memory whose contents are the address of the operand. So in this type of addressing mode, it
is the address of the address rather than address itself. (One operand is register) e. g. MOV R, M
MOV M, R STAX, LDAX etc.
STAX B B= 95 C =00
[9500] A
4) Immediate addressing mode: In this mode, the operand position is the immediate data. For 8-
bit data, instruction size is 2 bytes and for 16 bit data, instruction size is 3 bytes.
E.g. MVI A, 32H
LXI B, 4567H
5) Implied or Inherent addressing mode: The instructions of this mode do not have operands.
E.g. NOP: No operation
HLT: Halt
EI: Enable interrupt
22
DI: Disable interrupt
Pin diagram of 8085 Microprocessor:
Address bus
A15-A8, it carries the most significant 8-bits of memory/IO address.
Data bus
AD7-AD0, it carries the least significant 8-bit address and data bus.
Control and status signals
These signals are used to identify the nature of operation. There are 3 control signal and 3
status signals.
Three control signals are RD, WR & ALE.
• RD − This signal indicates that the selected IO or memory device is to be read and is
ready for accepting data available on the data bus.
• WR − This signal indicates that the data on the data bus is to be written into a selected
memory or IO location.
• ALE − It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes
down it indicates data.
Three status signals are IO/M, S0 & S1.
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IO/M
This signal is used to differentiate between IO and Memory operations, i.e. when it is high
indicates IO operation and when it is low then it indicates memory operation.
S1 & S0
These signals are used to identify the type of current operation.
Power supply
There are 2 power supply signals − VCC & VSS. VCC indicates +5v power supply and VSS
indicates ground signal.
Clock signals
There are 3 clock signals, i.e. X1, X2, CLK OUT.
• X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set
frequency of the internal clock generator. This frequency is internally divided by 2.
• CLK OUT − This signal is used as the system clock for devices connected with the
microprocessor.
Interrupts & externally initiated signals
Interrupts are the signals generated by external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. We
will discuss interrupts in detail in interrupts section.
• INTA − It is an interrupt acknowledgment signal.
• RESET IN − This signal is used to reset the microprocessor by setting the program
counter to zero.
• RESET OUT − This signal is used to reset all the connected devices when the
microprocessor is reset.
• READY − This signal indicates that the device is ready to send or receive data. If READY
is low, then the CPU has to wait for READY to go high.
• HOLD − This signal indicates that another master is requesting the use of the address
and data buses.
• HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD request
and it will relinquish the bus in the next clock cycle. HLDA is set to low after the HOLD
signal is removed.
Serial I/O signals
There are 2 serial signals, i.e. SID and SOD and these signals are used for serial communication.
• SOD (Serial output data line) − The output SOD is set/reset as specified by the SIM
instruction.
• SID (Serial input data line) − The data on this line is loaded into accumulator whenever a
RIM instruction is executed.
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Unit:5
Programming With Intel 8085 Microprocessor
8085 instruction sets:
Arithmetic group Instructions:

The 8085 microprocessor performs various arithmetic operations such as addition, subtraction,
increment and decrement. These arithmetic operations have the following mnemonics.
1) ADD R/M
– 1 byte add instruction.
– Adds the contents of register/memory to the contents of the accumulator and stores the
result in accumulator.
– E. g. Add B; A [A] + [B]
2) ADI 8 bit data
– 2 byte add immediate instruction.
– Adds the 8 bit data with the contents of accumulator and stores result in accumulator.
– E g. ADI 9BH ; A A+9BH
3) SUB R/M
– 1 byte subtracts instruction.
– Subtracts the contents of specified register / m with the contents of accumulator and
stores the result in accumulator.
– E. g. SUB D ; A A-D
4) SUI 8 bit data
– 2 byte subtracts immediate instruction.
– Subtracts the 8 bit data from the contents of accumulator stores result in accumulator.
– E. g. SUI D3H; A A-D3H
5) INR R/M, DCR R/M
– 1 byte increment and decrement instructions.
– Increase and decrease the contents of R(register) or M(memory) by 1 respectively.

– E. g. DCR B ; B=B-1
DCR M ; [HL] = [HL]-1
INR A; A=A+1
INR M; [HL] +1
For these, all flags are affected except carry.
6) INX Rp, DCX RP

– Increase and decrease the register pair by 1.
– Acts as 16 bit counter made from the contents of 2 registers (1 byte instruction)
– E.g. INX B ;BC=BC+1
DCX D ;DE=DE+1
– No flags affected
7) ADC R/M and ACI 8-bit data ( addition with carry (1 byte))
– ACI 8-bit data= immediate (2 byte).
– Adds the contents of register or 8 bit data whatever used suitably with the
Previous carry.
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– E.g. ADC B ; A A+B+CY
ACI 70H ; A A + 70+CY
8) SBB B/M
– 1 byte instruction.
– Subtracts the contents of register or memory from the contents of accumulator and
stores the result in accumulator.
– e. g. SBB D ; A A-D-Borrow
SBI 8 bit data
– Subtracts the 8-bit immediate data from the content of the accumulator and stores the
result in accumulator.
– E.g. SBI 70H ; A A-70-Borrow
9) DAD Rp(double addition)
– Adds register pair with HL pair and store the 16 bit result in HL pair.
– E. g. LXI H, 7320H
LXI B, 4220H
DAD B; HL=HL+BC
7320+4220=B540
10) DAA (Decimal adjustment accumulator)
– Used only after addition.
– The content of accumulator is changed from binary to two 4-bit BCD digits.
– E. g MVI A, 78H ; A=78
MVI B, 42H ; B=42
ADD B ; A=A+B = BA
DAA ; A=20, CY=1
The arithmetic operation add and subtract are performed in relation to the contents of
accumulator. The features of these instructions are
1) They assume implicitly that the accumulator is one of the operands.
2) They modify all the flags according to the data conditions of the result.
3) They place the result in the accumulator.
4) They do not affect the contents of operand register or memory.
But the INR and DCR operations can be performed in any register or memory.
These instructions
1) Affect the contents of specified register or memory.
2) Affect the flag except carry flag.
Addition operation in 8085:
8085 performs addition with 8-bit binary numbers and stores the result in accumulator. If the sum
is greater than 8-bits (FFH), it sets the carry flag.
E.g. MVI A, 93H 1 0 1 1 0 1 1 1 B7

MVI C, B7H +1 0 0 1 0 0 1 1 + 93
ADD C 10 1 0 0 1 0 1 0 1 4A
CY CY
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Subtraction operation in 8085:
8085 performs subtraction operation by using 2’s complement and the steps used are:
1) converts the subtrahend (the number to be subtracted) into its 1’s complement.
2) Adds 1 to 1’s complement to obtain 2’s complement of the subtrahend.
3) Adds 2’s complement to the minuend (the contents of the accumulator).
4) Complements the carry flag.
E.g. MVI A, 97H

MVI B, 65H
SUB B
1. The memory location 2050H holds the data byte F7H. Write instructions to transfer the
data byte to accumulator using different op-codes: MOV, LDAX and LDA.
LXI H, 2050H LXI B, 2050H LDA 2050H
MOV A, M LDAX B
2. Register B contains 32H, Use MOV and STAX to copy the contents of register B in memory
location 8000H.
LXI H, 8000H LXI D, 8000H
MOV M, B MOV A, B
3. The accumulator contains F2H, Copy A into memory 8000H. Also copy F2H directly into
8000H.
STA 8000H LXI H, 8000H
MVI M, F2H
4. The data 20H and 30H are stored in 2050H and 2051H. WAP to transfer the data to
3000H and 3001H using LHLD and SHLD instructions.
MVI A, 20H
STA 2050H LHLD 2050H
MVI A, 30H SHLD 3000H
STA 2051H HLT
5. Pair B contains 1122H and pair D contains 3344H. WAP to exchange the contents of B and
D pair using XCHG instruction.
LXI B, 1122H B=11, C=22
LXI D, 3344H D=33, E=44
MOV H, B
MOV L, C
XCHG (Exchange DE pair with HL pair)
MOV B, H
MOV C, L
HLT
6. WAP to add two 4 digit BCD numbers equals 7342 and 1989 and store result in BC
register.
LXI H, 7342H
LXI B, 1989H
MOV A, L
27
ADD C
DAA
MOV C, A
MOV A, H
ADC B
DAA
MOV B, A
7. Register BC contains 2793H and register DE contain 3182H. Write instruction to add
these two 16 bit numbers and place the sum in memory locations 2050H and 2051H.
What is DAA instruction?
MOV A, C
ADD E
MOV L, A L=15
MOV A, B
ADC
MOV H, A
SHLD 2050H
Note: SHLD stores the contents of L in specified location and contents of H in next higher location.
8. Register BC contains 8538H and register DE contain 62A5H. Write instructions to subtract
the contents of DE from the contents of BC and Place the result in BC.
MOV A, C
SUB E
MOV C, A ; C=93
MOV A, B
SBB D
MOV B, A ; B=22
Logical Group Instructions:

A microprocessor is basically a programmable logic chip. It can perform all the logic functions of
the hardwired logic through its instruction set. The 8085 instruction set includes such logic
functions as AND, OR, XOR and NOT (Complement):
The following features hold true for all logic instructions:
1) The instructions implicitly assume that the accumulator is one of the operands.
2) All instructions reset (clear) carry flag except for complement where flag remain unchanged.
3) They modify Z, P & S flags according to the data conditions of the result.
4) Place the result in the accumulator.
5) They do not affect the contents of the operand register. The logical operations have the
following instructions.
1) ANA R/M (the contents of register/memory)
– Logically AND the contents of register/memory with the contents of accumulator.
– CY flag is reset and AC is set.
2) ANI 8 bit data
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– Logically AND 8 bit immediate data with the contents of accumulator.
– CY flag is reset and AC is set. Others as per result
3) ORA R/M
– Logically OR the contents of register/memory with the contents of accumulator.
– CY and AC is reset and other as per result.
4) ORI 8 bit data
– Logically OR 8 bit immediate data with the contents of the accumulator.
5) XRA R/M
– Logically exclusive OR the contents of register memory with the contents of accumulator.
6) XRI 8 bit data
– Logically Exclusive OR 8 bit data immediate with the content of accumulator.
7) CMA (Complement accumulator)
– Complements the contents of the accumulator.
– No flags are affected.
Instruction CY AC
ANA/ANI 0 1
ORA/ORI 0 0
XRA/XRI 0 0
Logically Compare instructions

CMP R/M (1 byte instruction)
CPI 8 bit data ( 2 byte instruction)
– Compare the contents of register/ memory and 8 bit data with the contents of accumulator.
– Status is shown by flags & all flags are modified.
Case CY Z
[A]<[R/M] or 8 bit 1 0 A-R<0
[A]=[R/M] or 8 bit 0 1 A-R=0
[A]>[R/M] or 8 bit 0 0 A-R>0
Used to indicate end of data.
Logical Rotate instructions
This group has four instructions, two are for rotating left and two are for rotating right. The
instructions are:
1) RLC: Rotate accumulator left
– Each bit is shifted to the adjacent left position. Bit D7 becomes D0.
– The carry flag is modified according to D7.
29
2) RAL: Rotate accumulator left through carry

– Each bit is shifted to the adjacent left position. Bit D7 becomes the carry bit and the carry
bit is shifted into D0.
3) RRC: rotate accumulator right

– Each bit is shifted right to the adjacent position. Bit D0 becomes D7.
4) RAR: Rotate accumulator right through carry
– Each bit is shifted right to the adjacent position. Bit D0 becomes the carry bit and the
carry bit is shifted into D7.
Branching Group Instructions:

The microprocessor is a sequential machine; it executes machine codes from one memory location
to the next. The branching instructions instruct the microprocessor to go to a different memory
location and the microprocessor continues executing machine codes from that new location.
30
The branching instructions are the most powerful instructions because they allow the
microprocessor to change the sequence of a program, either unconditionally or under certain test
conditions.
The branching instruction code categorized in following three groups:
• Jump instructions
• Call and return instruction
• Restart instruction
Jump Instructions:
The jump instructions specify the memory location explicitly. They are 3 byte instructions, one
byte for the operation code followed by a 16 bit (2 byte) memory address. Jump instructions can
be categorized into unconditional and conditional jump.
Unconditional Jump
8085 includes unconditional jump instruction to enable the programmer to set up continuous
loops without depending only type of conditions.
E.g. JMP 16 bit address: loads the program counter by 16 bit address and jumps to specified
memory location.
E.g. JMP 4000H
Here, 40H is higher order address and 00H is lower order address. The lower order byte enters
first and then higher order.
– The jump location can also be specified using a label or name.
E.g.
MVI A, 80H START: IN 00H
OUT 43H OUT 01H
MVI A, 00H JMP START
L1: OUT 40H
INR A
JMP L1
HLT
Conditional Jump
The conditional jump instructions allow the microprocessor to make decisions based on certain
conditions indicated by the flags. After logic and arithmetic operations, flags are ser or reset to
reflect the condition of data. These instructions check the flag conditions and make decisions to
change or not to change the sequence of program. The four flags namely carry, zero, sign and
parity used by the jump instruction.
Mnemonics Description
JC 16 bit Jump on carry (if CY=1)
JNC 16 bit Jump on if no carry (if CY=0)
JZ 16bit Jump on zero (if Z=1)
JNZ 16bit jump on if no zero (if Z=0)
JP 16bit jump on positive (if S=0)
JM 16bit jump on negative (if S=1)
JPE 16bit Jump on parity even (if P=1)
JPO 16bit Jump on parity odd (if P=0)
E.g. WAP to move 10 bytes of data from starting address 9500 H to 9600H
31
2000 MVI B, 0AH
2002 LXI H, 9500H
2005 LXI D, 9600H
2008 MOV A, M
2009 STAX D ; Store the contents of accumulator to register pair.
200A INX H ; Increment the register pair by 1.
200B INX D
200C DCR B
200D JNZ 2008
2010 HLT
Q .Write to transfer 30 data starting from 8500 to 9500H if data is odd else store 00H.
MVI B, 1EH
LXI H, 8500H
LXI D, 9500H
L2: MOV A, M
ANI 01H
JNZ L1 ; If data is odd then go to L1.
MVI A, 00H
JMP L3
L1: MOV A, M
L3: STAX D
INX D
INX H
DCR B
JNZ L2
HLT
Call and return instructions: (Subroutine)

Call and return instructions are associated with subroutine technique. A subroutine is a group of
instructions that perform a subtask. A subroutine is written as a separate unit apart from the main
program and the microprocessor transfers the program execution sequence from main program
to subroutine whenever it is called to perform a task. After the completion of subroutine task
microprocessor returns to main program. The subroutine technique eliminates the need to write a
subtask repeatedly, thus it uses memory efficiently. Before implementing the subroutine, the
stack must be defined; the stack is used to store the memory address of the instruction in the
main program that follows the subroutines call.
To implement subroutine there are two instructions CALL and RET.
1. CALL 16 bit memory

– Call subroutine unconditionally.
– Saves the contents of program counter on the stack pointer. Loads the PC by jump
address (16 bit memory) and executes the subroutine.
2. RET
32
– Returns from the subroutine unconditionally.
– 1 byte instruction – Inserts the contents of stack pointer to program counter.
3. CC, CNC, CZ, CNZ, CP, CM, CPE, CPO
– Call subroutine conditionally.
– Same as CALL except that it executes on the basis of flag conditions.
4. RC, RNC, RZ, RNZ, RP, RM, RPE, RPO
– Return subroutine conditionally.
– Same as RET except that if executes on the basis of flag conditions.
Miscellaneous Group Instructions:

STACK
The stack is defined as a set of memory location in R/W memory, specified by a programmer in a
main memory. These memory locations are used to store binary information temporarily during
the execution of a program.
The beginning of the stack is defined in the program by using the instruction LXI SP, 16 bit address.
Once the stack location is defined, it loads 16 bit address in the stack pointer register. Storing of
data bytes for this operation takes place at the memory location that is one less than the address
e.g. LXI SP, 2099H
Here the storing of data bytes begins at 2098H and continuous in reverse order i.e 2097H.
Therefore, the stack is initialized at the highest available memory location to prevent the program
from being destroyed by the stack information. The stack instructions are:
1. PUSH Rp/PSW (Store register pair on stack)
– 1 byte instruction. – Copies the contents of specified register pair or program status word
(accumulator and flag) on the stack.
– Stack pointer is decremented and content of high order register is copied. Then it is
again decremented and content of low order register is copied.
2. POP Rp/PSW (retrieve register pair from stack)
– Copies the contents of the top two memory locations of the stack into specified register
pair or program status word.
– A content of memory location indicated by SP is copied into low order register and SP is
incremented by 1. Then the content of next memory location is copied into high order
register and SP is incremented by 1.
3. XTHL – exchanges top of stack (TOS) with HL

4. SPHL – move HL to SP
5.PCHL – move HL to PC Some instructions related to interrupt DI
– disable interrupt EI
– Enable interrupt SIM
– set interrupt mask RIM
– read interrupt mask
E.g. LXI SP, 1FFFH
LXI H, 9320H
LXI B, 4732H
LXI D, ABCDH
33
MVI A, 34H
PUSH H
PUSH B
PUSH D
PUSH PSW
POP H
POP B
POP D
POP PSW
HLT
BEORE EXECUTION
H= 93 L= 20
B= 47 C=32
D= AB E=CD
A= 34 F= 10
AFTER EXECUTION
H= 34 L=10
B=AB C=CD
D= 47 E=32
A= 93 F=20
Note: STACK Works in LIFO (Last In First Out) manner.
5. WAP to sort in ascending order for 10 bytes from 1120H.
START: LXI H, 1120H
MVI D, 00H
MVI C, 09H
L2: MOV A, M
INX H
CMP M
JC L1 ; if A<M
MOV B, M
MOV M, A
DCX H
MOV M, B
INX H
MVI D, 01H
L1: DCR C
JNZ L2
MOV A, D
RRC
JC START
HLT
BCD to binary conversion:

In most microprocessor-based products. Data are entered and displayed in decimal numbers. For
example, in an instrumentation laboratory, readings such as voltage and current are maintained in
34
decimal numbers, and data are entered through decimal keyboard. The system monitor program
of the instrument converts each key into an equivalent 4-bit binary number and stores two BCD
numbers in an 8-bit register or a memory location. These numbers are called packed BCD.
Conversion of BCD number into binary number employs the principle of positional weighting in a
given number.
E.g. 7210 =7 x 10+2
converting an 8-bit BCD number into its binary equivalent requires.
– Separate an 8- bit packed BCD number into two 4 bit unpacked BCD digits i.e. BCD1 and BCD2.
– Convert each digit into its binary value according to its position.
– Add both binary numbers to obtain the binary equivalent of the BCD number.
E.g.
7210 = 0111 0010 BCD
Step 1: 0111 0010 0000 0010 Unpacked BCD1
 0000 0111 Unpacked BCD2
Step 2: Multiply BCD2 by 10 (7 10)

Step 3: Add BCD1 to answer of step 2
Program: 2-digit BCD- to- Binary Conversion
A BCD number between 0 and 99 is stored in an R/W memory location called the Input Buffer
(INBUF). Write a main program and a conversion subroutine (BCDBIN) to convert the BCD number
into its equivalent binary number. Store the result in a memory location defined as the Output
Buffer (OUTBUF).
LXI H, 2020H
MVI E, 0A H
MOV A, M ; 0111 0010
ANI F0H ; 0111 0000
RRC
RRC
RRC
RRC
MOV B,A
XRA A
L1: ADD B ; 7 10+2
DCR E
JNZ L1
MOV C, A
MOV A, M
ANI 0FH
ADD C
STA 2030H
HLT
Program to convert 8-bit binary to BCD

LXI SP, 1999H
LXI H, 2020H ; Source
35
MOV A, M
CALL PWRTEN
HLT
PWRTEN: LXI H, 2030H ; Destination
MVI B, 64H
CALL BINBCD
MVI B, 0AH
CALL BINBCD
MOV M, A
RET
BINBCD: MVI M, FFH
NEXT: INR M
SUB B
JNC NEXT
ADD B
INX H
RET
ASCII to Binary Conversion

Step 1: Subtract 30H
Step 2: If < 0AH, then binary as it is
Else subtract 07H
For example: If ASCII is 41H, then 41H – 30H = 11H; 11H – 07H = 0AH
Program to convert ASCII number to Binary:

LXI SP, 1999H
LXI H, 1040H ; Source
LXI D, 1050H ; Destination
MOV A, M
CALL ASCBIN
STAX D
HLT
ASCBIN: SUI 30H
CPI 0AH
RC
SUI 07H
RET
Program to multiply two 8 bit binary numbers.

LXI SP, 1999H
LHLD 2050H ; Two numbers
XCHG ; Multiplier on D, Multiplicand on E
CALL MULT
SHLD 2090H ; Store the product
HLT
MULT: MOV A, D
36
MVI D, 00H
LXI H, 0000H
MVI B, 08H ; Counter
NEXT: RAR ; Check multiplier bit is 1 or 0
JNC BELOW
DAD D ; Partial result in HL
BELOW: XCHG
DAD H ; Shift left multiplicand
XCHG ; Retrieve shifted multiplicand
DCR B
JNZ NEXT
RET
37
Unit: 6
Basic I/O, Memory R/W and Interrupt Operations
Introduction to Direct Memory Access (DMA) & DMA Controllers
During any given bus cycle, one of the system components connected to the system bus is given
control of the bus. This component is said to be the master during that cycle and the component it
is communicating with is said to be the slave. The CPU with its bus control logic is normally the
master, but other specially designed components can gain control of the bus by sending a bus
request to the CPU. After the current bus cycle is completed the CPU will return a bus grant signal
and the component sending the request will become the master.
Taking control of the bus for a bus cycle is called cycle stealing. Just like the bus control logic, a
master must be capable of placing addresses on the address bus and directing the bus activity
during a bus cycle. The components capable of becoming masters are processors (and their bus
control logic) and DMA controllers. Sometimes a DMA controller is associated with a single
interface, but they are often designed to accommodate more than one interface.
This is a process where data is transferred between two peripherals directly without the
involvement of the microprocessor. This process employs the HOLD pin on the microprocessor.
The external DMA controller sends a signal on the HOLD pin to the microprocessor. The
microprocessor completes the current operation and sends a signal on HLDA and stops using the
buses. Once the DMA controller is done, it turns off the HOLD signal and the microprocessor takes
back control of the buses.
Basic DMA operation
• The direct memory access (DMA) technique provides direct access to the memory while
the microprocessor is temporarily disabled.
• A DMA controller temporarily borrows the address bus, data bus, and control bus from
the microprocessor and transfers the data bytes directly between an I/O port and a series
of memory locations.
• The DMA transfer is also used to do high-speed memory-to memory transfers.
• Two control signals are used to request and acknowledge a DMA transfer in the
microprocessor-based system.
• The HOLD signal is a bus request signal which asks the microprocessor to release control
of the buses after the current bus cycle.
• The HLDA signal is a bus grant signal which indicates that the microprocessor has indeed
released control of its buses by placing the buses at their high-impedance states.
• The HOLD input has a higher priority than the INTR or NMI interrupt inputs.
DMA Data Transfer scheme
• Data transfer from I/O device to memory or vice-versa is controlled by a DMA controller.
• This scheme is employed when large amount of data is to be transferred.
• The DMA requests the control of buses through the HOLD signal and the MPU
acknowledges the request through HLDA signal and releases the control of buses to DMA.
• It’s a faster scheme and hence used for high speed printers.
Interrupt Operations
• Interrupt is signals send by an external device to the processor, to request the processor
to perform a particular task or work.
38
• Mainly in the microprocessor based system the interrupts are used for data transfer
between the peripheral and the microprocessor.
• The processor will check the interrupts always at the 2nd T-state of last machine cycle.
• If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the
peripheral.
• The vectored address of particular interrupt is stored in program counter.
• The processor executes an interrupt service routine (ISR) addressed in program counter.
• It returned to main program by RET instruction.
Need for Interrupt: Interrupts are particularly useful when interfacing I/O devices that provide or
require data at relatively low data transfer rate.
Interrupt Operations The transfer of data between the microprocessor and input /output devices
takes place using various modes of operations like programmed I/O, interrupt I/O and direct
memory access. In programmed I/O, the processor has to wait for a long time until I/O module is
ready for operation. So the performance of entire system degraded. To remove this problem CPU
can issue an I/O command to the I/O module and then go to do some useful works. The I/O device
will then interrupt the CPU to request service when it is ready to exchange data with CPU. In
response to an interrupt, the microprocessor stops executing its current program and calls a
procedure which services the interrupt. The interrupt is a process of data transfer whereby an
external device or a peripheral can inform the processor that it is ready for communication and it
requests attention. The response to an interrupt request is directed or controlled by the
microprocessor.
Process of interrupt Operation
From the point of view of I/O unit
• I/O device receives command from CPU
• The I/O device then processes the operation
• The I/O device signals an interrupt to the CPU over a control line.
• The I/O device waits until the request from CPU.
From the point of view of processor
• The CPU issues command and then goes off to do its work.
• When the interrupt from I/O device occurs, the processor saves its program counter &
registers of the current program and processes the interrupt.
• After completion for interrupt, processor requires its initial task.
Polling versus Interrupt
• Each time the device is given a command, for example ``move the read head to sector 42
of the floppy disk'' the device driver has a choice as to how it finds out that the command
has completed. The device drivers can either poll the device or they can use interrupts.
• Polling the device usually means reading its status register every so often until the device's
status changes to indicate that it has completed the request.
• Polling means the CPU keeps checking a flag to indicate if something happens.
• An interrupt driven device driver is one where the hardware device being controlled will
cause a hardware interrupt to occur whenever it needs to be serviced.
• With interrupt, CPU is free to do other things, and when something happens, an interrupt
is generated to notify the CPU. So it means the CPU does not need to check the flag.
• Polling is like picking up your phone every few seconds to see if you have a call. Interrupts
are like waiting for the phone to ring.
39
• Interrupts win if processor has other work to do and event response time is not critical.
• Polling can be better if processor has to respond to an event ASAP; may be used in device
controller that contains dedicated secondary processor.
Advantages of interrupt over Polling
• Interrupts are used when you need the fastest response to an event. For example, you
need to generate a series of pulses using a timer. The timer generates an interrupt when it
overflows and within 1 or 2 sec, the interrupt service routine is called to generate the
pulse. If polling were used, the delay would depend on how often the polling is done and
could delay response to several msecs. This is thousands times slower.
• Interrupts are used to save power consumption. In many battery powered applications,
the microcontroller is put to sleep by stopping all the clocks and reducing power
consumption to a few micro amps. Interrupts will awaken the controller from sleep to
consume power only when needed. Applications of this are hand held devices such as
TV/VCR remote controllers.
• Interrupts can be a far more efficient way to code. Interrupts are used for program
debugging.
Interrupt structures:
A processor is usually provided with one or more interrupt pins on the chip. Therefore a special
mechanism is necessary to handle interrupts from several devices that share one of these
interrupt lines. There are mainly two ways of servicing multiple interrupts which are polled
interrupts and daisy chain (vectored) interrupts.
1. Polled interrupts
Polled interrupts are handled by using software which is slower than hardware interrupts.
Here the processor has the general (common) interrupt service routine (ISR) for all devices.
The priority of the devices is determined by the order in which the routine polls each
device. The processor checks the starting with the highest priority device. Once it
determines the source of the interrupt, it branches to the service routine for that device.
Here several eternal devices are connected to a single interrupt line (INTR) of the
microprocessor. When INTR signal goes up, the processor saves the contents of PC and
other registers and then branches to an address defined by the manufactures of the
processor. The user can write a program at this address to find the source of the interrupt
by starting the polled from highest priority device.
2. Daisy chain (vectored) interrupt

In polled interrupt, the time required to poll each device may exceed the time to service
the device through software. To improve this, the faster mechanism called vectored or
daisy chain interrupt is used. Here the devices are connected in chain fashion. When INTR
40
pin goes up, the processor saves its current status and then generates INTA �� signal to the
highest priority device. If this device has generated the interrupt, it will accept the INTA;
�� to the next priority device until the INTA
otherwise it will push INTA �� is accepted by the
interrupting device.
�� is accepted, the device provides a means to the processor for findings the
When INTA
interrupt address vector using external hardware. The accepted device responds by placing
a word on the data lines which becomes the vector address with the help of any hardware
through which the processor points to appropriate device service routine. Here no general
interrupt service routine need first that means appropriate ISR of the device will be called.
Interrupt priority:
Microcomputers can transfer data to or from an external devices using interrupt through
INTR pin. When device wants to communicate with the microcomputer, it connects to INTR
pin and makes it high or low depending on microcomputer. The microcomputer responds
by sending signal via its pin called interrupt acknowledgement INTA. In differentiation with
the occurrence of interrupts, basically following interrupts exist.
1. External interrupts:
These interrupts are initiated by external devices such as A/D converters and classified
on following types.
Maskable interrupt : It can be enabled or disabled by executing instructions such as EI and DI. In
8085, EI sets the interrupt enable flip flop and enables the interrupt process. DI resets the
interrupt enable flip flop and disables the interrupt.
Non-maskable interrupt: It has higher priority over maskable interrupt and cannot be enabled or
disabled by the instructions.
2. Internal interrupts:
• These are indicated internally by exceptional conditions such as overflow, divide by zero, and
execution of illegal op-code. The user usually writes a service routine to take correction measures
and to provide an indication in order to inform the user that exceptional condition has occurred.
• There can also be activated by execution of TRAP instruction. This interrupt means TRAP is useful
for operating the microprocessor in single step mode and hence important in debugging.
• These interrupts are used by using software to call the function of an operating system. Software
interrupts are shorter than subroutine calls and they do not need the calling program to know the
operating system’s address in memory.
41
Types of Interrupts:
It supports two types of interrupts.
1. Hardware 2. Software
Software interrupts: The software interrupts are program instructions. These instructions are
inserted at desired locations in a program. The 8085 has eight software interrupts from RST 0 to
RST 7. The vector address for these interrupts can be calculated as follows.
Interrupt number * 8 = vector address
For RST 5; 5 * 8 = 40 = 28H
Vector address for interrupt RST 5 is 0028H
The Table shows the vector addresses of all interrupts.
Interrupt Pins and Priorities (Hardware interrupts)

An external device initiates the hardware interrupts and placing an appropriate signal at the
interrupt pin of the processor. If the interrupt is accepted then the processor executes an
interrupt service routine. The 8085 has five hardware interrupts
(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR
TRAP:
• This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt
enable.
• TRAP bas the highest priority and vectored interrupt.
• TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and
remain high until it is acknowledged.
• In sudden power failure, it executes a ISR and send the data from main memory to backup
memory.
• The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD
and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).
• There are two ways to clear TRAP interrupt.
1. By resetting microprocessor (External signal) 2. By giving a high TRAP
ACKNOWLEDGE (Internal signal)
RST 7.5:
The RST 7.5 interrupt is a maskable interrupt.
• It has the second highest priority.
• It is edge sensitive. ie. Input goes to high and no need to maintain high state until it
recognized.
• Maskable interrupt. It is disabled by,
1. DI instruction
2. System or processor reset.
3. After reorganization of interrupt.
• Enabled by EI instruction.
RST 6.5 and 5.5:
• The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay high until
it recognized.
• Maskable interrupt. It is disabled by,
42
1. DI, SIM instruction
• The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
INTR:
• INTR is a maskable interrupt.
• It is disabled by,
1. DI, SIM instruction
• Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply
the address of ISR.
• It has lowest priority.
• It is a level sensitive interrupts. i.e. Input goes to high and it is necessary to
maintain high state until it recognized.
• The following sequence of events occurs when INTR signal goes high.
1. The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends active
low interrupt acknowledge signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic places an instruction
OPCODE on the data bus. In the case of multi-byte instruction, additional interrupt
acknowledge machine cycles are generated by the 8085 to transfer the additional
bytes into the microprocessor.
4. On receiving the instruction, the 8085 save the address of next instruction on
stack and execute received instruction.
8259 operations:
Features:
1. It is a LSI chip which manages 8 levels of interrupts i.e. it is used to implement 8 level
interrupt systems.
2. It can be cascaded in a master slave configuration to handle up to 64 levels of interrupts.
3. It can identify the interrupting device.
4. It can resolve the priority of interrupt requests i.e. it does not require any external
priority resolver.
5. It can be operated in various priority modes such as fixed priority and rotating priority.
6. The interrupt requests are individually mask-able.
7. The operating modes and masks may be dynamically changed by the software at any
time during execution of programs.
8. It accepts requests from the peripherals, determines priority of incoming request,
checks whether the incoming request has a higher priority value than the level currently
being serviced and issues an interrupt signal to the microprocessor.
43
9. It provides 8 bit vector number as an interrupt information.
10. It does not require clock signal.
11. It can be used in polled as well as interrupt modes.
12. The starting address of vector number is programmable.
13. It can be used in buffered mode.
The block diagram of 8259 is shown in the figure below:
It contains following blocks-
1. Data bus buffer-
• It is used to transfer data between microprocessor and internal bus.
1. Read/write logic-
• It sets the direction of data bus buffer.

• It controls all internal read/write operations.
• It contains initialization and operation command registers.
Cascaded buffer and comparator-
• In master mode, it functions as a cascaded buffer. The cascaded buffers outputs slave
identification number on cascade lines.
• In slave mode, it functions as a comparator. The comparator reads slave identification
number from cascade lines and compares this number with its internal identification
number.
• In buffered mode, it generates an (EN) ̅ signal.
44
Control logic-
• It generates an INT signal. In response to an (INTA) ̅ signal, it releases three byte CALL
address or one byte vector number.
• It controls read/write control logic, cascade buffer/comparator, in service register,
priority resolver and IRR.
Interrupt request register-
• It is used to store all pending interrupt requests.

• Each bit of this register is set at the rising edge or at the high level of the corresponding
interrupt request line.
• The microprocessor can read contents of this register by issuing appropriate command
word.
In service register (InSR)-
• It is used to store all interrupt levels currently being serviced.

• Each bit of this register is set by priority resolver and reset by end of interrupt command
word.
• The microprocessor can read contents of this register by issuing appropriate command
word.
Priority resolver-
• It determines the priorities of the bit set in the IRR. To make decision, the priority
resolver looks at the ISR.
• If the higher priority bit in the InSR is set then it ignores the new request.
• If the priority resolvers find that the new interrupt has a higher priority than the highest
priority interrupt currently being serviced and the new interrupt is not in service, then it
will set appropriate bit in the InSR and send the INT signal to the microprocessor for
new interrupt request.
Interrupt mask register (IMR)-
• It is a programmable register.
• It is used to mask unwanted interrupt request by writing appropriate command word.
• The microprocessor can read contents of this register without issuing any command
word.
45
Unit : 7
Input/output Interface
Method of communicating:
Serial communication is the method of transferring one bit at a time.
Data can be transmitted between a sender and a receiver in two main ways: serial and parallel
through a medium.
Parallel communication is the method of transferring blocks, e.g.: BYTEs, of data at the same time.
Serial data transmission
In serial data transmission, bits are sent sequentially (one after the other) down the same wire
(channel).
Using a single wire reduces costs but slows down the speed of transmission.
Sending data sequentially is perfect for transmitting over longer distances as there are no
synchronization issues.
Typical applications
• Transmission to another computer or to external devices

• Medium to long distances
• Universal Serial Bus (USB)
Parallel data transmission
In parallel data transmission, multiple bits are sent simultaneously down different wires
(channels) within the same cable.
Data is synchronized by a clock, however this becomes problematic over longer distances
where synchronization errors may start to occur.
Using parallel wires is more expensive but transmission is faster.
Typical applications
• Fast transmission within a computer system

• Short distances
• Integrated Circuits (IC), Busses
46
Introduction to Programmable Communication Interface 8251

The intel 8251A is the Industry Standard Universal Synchronous /Asynchronous
Receiver/Transmitter(USART), design for the data communication with Intel
microprocessors families such as 8080,85,86,88 etc. The 8251 A converts the parallel data
received from the processor on the D7-D0 data pins into the serial data and transmit it on
TxD(Transmit Data) out pin of 8251A . Similarly , it covert the serial data received on
RxD(received data ) into parallel data and processor reads it using the pins D7-D0 .
Features:
• Compatible with extended range of Intel microprocessor.
• It provides the both synchronous and asynchronous data transmission.
• Synchronous 5-8 bit of characters.
• Asynchronous 5-8 bits of characters.
• It has full duplex, double buffered transmitter and receiver.
Architecture:
Sections of 8251A
• Data Bus buffer
• Read/Write Control Logic
• Modem Control
• Transmitter
• Receiver
47
Data Bus Buffer D0-D7:

• 8-bit data bus used to read or write status, command word or data from or to the 8251A.
Read/Write Control logic

• Includes a control logic, six input signals & three buffer registers: Data register, control
register & status register.
• Control logic : Interfaces the chip with MPU, determines the functions of the chip
according to the control word in the control register & monitors the data flow.
Input signals
��– Chip Select: When signal goes low, the 8251A is selected by the MPU for communication.
𝑪𝑪𝑪𝑪
� – Control/Data: When signal is high, the control or status register is addressed; when it is low, data
C/𝑫𝑫
buffer is addressed. (Control register & status register are differentiated by WR and RD signals)
��: When signal is low, the MPU either writes in the control register or sends output to the data buffer.
𝑾𝑾𝑾𝑾
��
𝑹𝑹𝑹𝑹: When signal goes low, the MPU either reads a status from the status register or accepts data from
data buffer.
RESET: A high on this signal reset 8252A & forces it into the idle mode.
CLK: Clock input, usually connected to the system clock for communication with the microprocessor.
48
Control Register
• 16-bit register for a control word consist of two independent bytes namely mode word & command
word.
• Mode word : Specifies the general characteristics of operation such as baud, parity, number of bits
etc.
• Command word : Enables the data transmission and reception.
• Register can be accessed as an output port when the Control/Data pin is high.
Status register
• Checks the ready status of the peripheral.
• Status word in the status register provides the information concerning register status and
transmission errors.
Data register
Used as an input and output port when the C/D is low.
CS C/D WR RD Operation
0 0 0 0 MPU reads data from data buffer
1 0 0 1 MPU writes data from data buffer
1 × 1 0 MPU writes a word to control register
0 1 × 0 MPU reads a word from status register
1 1 0 × Chip is not selected for any operation
3. Modem Control
��
𝑫𝑫𝑫𝑫𝑫𝑫 - Data Set Ready : Checks if the Data Set is ready when communicating with a modem.
��
𝑫𝑫𝑫𝑫𝑫𝑫 - Data Terminal Ready: Indicates that the device is ready to accept data when the 8251 is
communicating with a modem.
��
𝑪𝑪𝑪𝑪𝑪𝑪 - Clear to Send: If its low, the 8251A is enabled to transmit the serial data provided the enable bit in
the command byte is set to ‘1’.
��
𝑹𝑹𝑹𝑹𝑹𝑹 - Request to Send Data: Low signal indicates the modem that the receiver is ready to receive a data
byte from the modem.
Transmitter section
• Accepts parallel data from MPU & converts them into serial data.
• Has two registers:
• Buffer register : To hold eight bits
• Output register : To convert eight bits into a stream of serial bits.
Receiver Section
• Accepts serial data on the RxD pin and converts them to parallel data.
• Has two registers :
• Receiver input register
49
• Buffer register
Basic concept of synchronous and asynchronous modes
Synchronous
The term synchronous is used to describe a continuous and consistent timed transfer of data blocks.
The following is a list of characteristics specific to synchronous communication:
• There are no gaps between characters being transmitted.

• Timing is supplied by modems or other devices at each end of the connection.
• Special syn characters precede the data being transmitted.
• The syn characters are used between blocks of data for timing purposes.
Asynchronous
In contrast, asynchronous transmission works in spurts and must insert a start bit before each data
character and a stop bit at its termination to inform the receiver where it begins and ends.
The following is a list of characteristics specific to asynchronous communication:
• Each character is preceded by a start bit and followed by one or more stop bits.
• Gaps or spaces between characters may exist.
i) Simple I/O
• When you need to get digital data from simple switch, such as thermostat, into
microprocessor, all you have to do is connect the switch to an I/O port line and read the port.
50
• Likewise, when you need to output data to simple display device, such as LED, all you
have to do is connect the input of the LED buffer on an output port pin and output the logical
level required to turn on the light.
Fig: Simple I/O

• The timing waveform represents the situation.
• The crossed lines on the waveform represent the time at which a new data byte
becomes valid on the output lines of the port.
• The absence of other waveforms indicates that this output operation is not directly
dependant on any other signal.
ii) Strobe I/O
• In many applications, valid data is present on an external device only at a certain time,
so it must be read in at that time.
• E.g. the ASCII-encoded keyboard. When a key is pressed, circuitry on the keyboard sends
out the ASCII code for the pressed key on eight parallel data lines, and then sends out a strobe
signal on another line to indicate that valid data is present on the eight data lines.
Fig: Strobe I/O

• This timing waveform represents strobe I/O.
• The sending device, such as a keyboard, outputs a parallel data on the data lines, and
then outputs an STB signal to let you know that valid data is present.
• For low rates of data transfer, such as from a keyboard to a MP, a simple strobe transfer
works well.
• However, for higher speed data transfer, this method does not work because there is no
signal which tells the sending device when it is safe to send the next data byte.
• In other words, the sending system might send data bytes faster than the receiving
system could read them.
• To prevent this problem, a handshake data transfer scheme is used.
iii) Single handshake I/O
51
Fig: Single Handshake I/O

• It shows the timing waveform for a handshake data transfer from a peripheral device to
a MP.
• The peripheral outputs some parallel data and sends an STB signal to the MP.
• The MP detects the asserted STB signal on a polled or interrupts basis and reads in the
bytes of data.
• Then, the MP sends ACK (acknowledge) signal to the peripheral to indicate that the data
has been read and that the peripheral can send next byte of data.
• The point of this method is that the sending device or system is designed so that it does
not send the next byte until the receiving device or system indicates with an ACK signal that it is
ready to receive the next byte.
iv) Double handshake I/O
Fig: Double Handshake I/O

• For data transfer where even more coordination is required between the sending
system and the receiving system, a double handshake is used.
• The sending (peripheral) device asserts its STB line low to ask the receiving device
whether it is ready or not for data reception.
• The receiving system raises its ACK line high to indicate that it is ready.
• The peripheral device then sends the byte of data and raises its STB line high to assure
that the valid data is available for the receiving device (MP).
• When MP reads the data, it drops its ACK line low to indicate that it has received the
data and requests the sending system to send next byte of data.
52
8255A and its working
• The 8255A is a general purpose programmable I/O device designed to transfer the data
from I/O to interrupt I/O under certain conditions as required. It can be used with
almost any microprocessor.
• It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as
per the requirement.
Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.
• Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
• Port B is similar to PORT A.
• Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-
PC4) by the control word.
These three ports are further divided into two groups, i.e. Group A includes PORT A and upper
PORT C. Group B includes PORT B and lower PORT C. These two groups can be programmed in
three different modes, i.e. the first mode is named as mode 0, the second mode is named as
Mode 1 and the third mode is named as Mode 2.
Operating Modes
8255A has three different operating modes −
• Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit
ports. Each port can be programmed in either input mode or output mode where
outputs are latched and inputs are not latched. Ports do not have interrupt capability.
• Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be configured
as either input or output ports. Each port uses three lines from port C as handshake
signals. Inputs and outputs are latched.
• Mode 2 − In this mode, Port A can be configured as the bidirectional port and Port B
either in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals
for data transfer. The remaining three signals from Port C can be used either as simple
I/O or as handshake for port B.
Features of 8255A
The prominent features of 8255A are as follows −
• It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
• Address/data bus must be externally Demux.
• It is TTL compatible.
• It has improved DC driving capability.
8255 Architecture
The following figure shows the architecture of 8255A :
53
Control Word For 8255A
RS-232: Introduction, pin configuration (9 pin and 25 pin)
54
The RS-232(X) is a communication cable, commonly used for transferring and receiving the serial
data between two devices. It supports both synchronous and asynchronous data transmissions.
Many devices in the industrial environment are still using RS-232 communication cable. Rs-232
cable is used to identify the difference of two signal levels between logic 1 and logic 0. The logic 1
is represented by the -12V and logic 0 is represented the +12V. The RS-232 cable works at
different baud rates like 9600 bits/s, 2400bits/s, 4800bits/s etc. The RS-232 cable has two terminal
devices namely Data Terminal Equipment and Data communication Equipment. Both device will
sends and receives the signals. The data terminal equipment is computer terminal and data
communication Equipment is modems, or controllers etc.
Now a day’s most of personal computers have two serial ports and one parallel port (RS232).
These two types of ports are used for communicating with external devices and they work in
different ways. The parallel port sends and receives the 8-bit data at a time over eight separate
wires and this transfers the data very quickly, the parallel ports are typically used to connect a
printer to a PC.
A serial port sends and receives one bit data at a time over one wire and it transfer data very
slowly. The RS-232 stands for recommended slandered and 232 is a number X is indicates the
latest version like RS-232c, RS232s.
The most commonly used type of serial cable connectors are 9-pin connector DB9 and 25-pin
connector DB-25. Each of them may be male or female type. Now a days most of computers
use DB9 connector for asynchronous data exchange. The maximum length of RS-232 cable is
50ft.
55
Fig Pin Configuration of 9 pin and 25 pin RS-232
SAP-I and SAP-II

SAP is Simple-As-Possible Computer. The type of computer is specially designed for the
academic purpose and nothing has to do with the commercial use. The architecture is 8 bits and
comprises of 16 X 8 memory i.e. 16 memory location with 8 bits in each location, therefore,
need 4 address lines which either comes from the PC (Program Counter which may be called
instruction pointer) during computer run phase or may come from the 4 address switches
during the program phase. All instructions (5 only) get stored in this memory. It means SAP
cannot store program having more than 16 instructions.
SAP can only perform addition and subtraction and no logical operation. These arithmetic
operations are performed by an adder/subtractor unit.
There is one general purpose register (B register) used to hold one operand of the arithmetic
operation while another is kept by the accumulator register of the SAP-1.
In addition, there are 8 LEDs which work as output unit and connected with the 8 bit output
register.
All timely moment of data or activities are performed by the controller/sequencer part of the
SAP-1.
Program Counter
• It counts from 0000 to 1111.
• It signals the memory address of next instruction to be fetched and executed.
Inputs and MAR (Memory Address Register)
• During a computer run, the address in PC is latched into Memory Address Register
(MAR).
The RAM
• The program code to be executed and data for SAP-1 computer is stored here.
• During a computer run, the RAM receives 4-bit addresses from MAR and a read
operation is performed. Hence, the instruction or data word stored in RAM is placed on the W
bus for use by some other part of the computer.
• It is asynchronous RAM, which means that the output data is available as soon as valid
address and control signal are applied.
56
Instruction Register
• IR contains the instruction (composed of OPCODE+ADDRESS) to be executed by SAP1
computer.
Controller-Sequencer
• It generates the control signals for each block so that actions occur in desired sequence.
CLK signal is used to synchronize the overall operation of the SAP1 computer.
• A 12-bit word comes out of the Controller-Sequencer block. This control word
determines how the registers will react to the next positive CLK edge.
Accumulator
• It is a 8-bit buffer register that stores intermediate results during a computer run.
• It is always one of the operands of ADD, SUB and OUT instructions.
Adder/Subtractor
• It is a 2's complement adder-subtractor.
• This module is asynchronous (unclocked), which means that its contents can change as
soon as the input words change.
B-register
• It is 8-bit buffer register which is primarily used to hold the other operand (one operand
is always accumulator) of mathematical operations.
Output Register
• This registers hold the output of OUT instruction.
Binary Display
• It is a row of eight LEDs to show the contents of output register.
• Binary display unit is the output device for the SAP-1 microprocessor.
57
SAP-II
• Hexadecimal Keyboard Encoder: The hexadecimal keyboard encoder receives the data
from outer environment and converts it into hexadecimal form. The system can understand and
send them to the input port.
• Input Ports: The SAP-2 contains two input ports which input the data in the system in
the most convenient way.
• PC: PC is the program counter that holds the address of the next instruction to be
fetched. It initializes from 0000H to 1111H during the execution.
• MAR: MAR is the memory address register that stores the complete format of the
address sent by the program counter. It stores the final address of the memory word that needs
some computations.
• 64K Memory: It contains 64 K memory where data and instruction reside. All the
computations are performed relative to the memory.
• MDR: MDR is the Memory Data Register which stores the data or operand that is
fetched from the memory which is needed for computation.
58
• IR: The IR is the Instruction Register that holds the complete format of the Instruction
that is to be executed.
• Control Sequencer: It provides necessary timing signals like T0, T1, T2, ….. and control
signals providing the direction for executing the program.
• Accumulator: The result of all the mathematical operations is stored in accumulator. It
is one of the operand of ADD, OUT, SUB instruction. It is also known as processor register.
• ALU and Flag: The ALU perform all the arithmetic and logical calculations. The flag
reflect the intermediate changes on the values during execution.
• Temporary register, B, C: They are the second operand of the mathematical operations.
The register B and C is accessible to the programmer.
• Output Ports: It consists of two output ports to show the result of OUT instruction.
• Hexadecimal Display: Unlike Sap-1 which has binary display, Sap-2 has a hexadecimal
display to show outputs in the LEDs.
59

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Prepared BY: BP BHATTA

Fig: Block Diagram of Microprocessor

Fig: Von- Neumann Architecture

Some of the common components of a microprocessor are:

1. Primary Memory / Volatile Memory:

Random Access Memory (RAM):

2. Secondary Memory / Non Volatile Memory:

Read Only Memory (ROM):

The 8085 Bus Structure

To write a byte into a memory location

To read from memory, the steps are similar.

T-state: Each clock cycle is called as T-states.

4. These rules are applicable to 80% of the instructions of 8085.

Memory Read Cycle (3T):

Memory Write cycle (3T):

IO Read Machine Cycle:

IO Write Machine Cycle:

Timing Diagram of following instruction:

ii) MVI B,43H

Characteristics (features) of 8085A microprocessor and its signals

5. Externally Initiated signals:

An instruction manipulates the data and a sequence of instructions constitutes a program.

Pin diagram of 8085 Microprocessor:

Arithmetic group Instructions:

– Increase and decrease the contents of R(register) or M(memory) by 1 respectively.

6) INX Rp, DCX RP

E.g. MVI A, 93H 1 0 1 1 0 1 1 1 B7

E.g. MVI A, 97H

Logical Group Instructions:

Logically Compare instructions

2) RAL: Rotate accumulator left through carry

3) RRC: rotate accumulator right

Branching Group Instructions:

Call and return instructions: (Subroutine)

1. CALL 16 bit memory

Miscellaneous Group Instructions:

3. XTHL – exchanges top of stack (TOS) with HL

BCD to binary conversion:

Step 2: Multiply BCD2 by 10 (7 10)

Program to convert 8-bit binary to BCD

ASCII to Binary Conversion

Program to convert ASCII number to Binary:

Program to multiply two 8 bit binary numbers.

2. Daisy chain (vectored) interrupt

Interrupt Pins and Priorities (Hardware interrupts)

The block diagram of 8259 is shown in the figure below:

It contains following blocks-

1. Data bus buffer-

• It is used to transfer data between microprocessor and internal bus.

• It sets the direction of data bus buffer.

Cascaded buffer and comparator-

Interrupt request register-

• It is used to store all pending interrupt requests.

In service register (InSR)-

• It is used to store all interrupt levels currently being serviced.

Interrupt mask register (IMR)-

Serial data transmission

• Transmission to another computer or to external devices

Parallel data transmission

Using parallel wires is more expensive but transmission is faster.