Experiment 1: Cmos Inverter: Objective: Design A Schematic of A CMOS Inverter in Cadence

EXPERIMENT 1: CMOS INVERTER
Objective: Design a schematic of a CMOS Inverter in Cadence

Virtuoso Schematic Editor. Obtain the DC transfer characteristics and
transient response for different widths and temperature conditions
using parametric analysis.
Theory: A CMOS inverter contains a PMOS and a NMOS transistor connected
at the drain and gate terminals, a supply voltage VDD at the PMOS source terminal,
and a ground connected at the NMOS source terminal, where VIN is connected to
the gate terminals and VOUT is connected to the drain terminals. It is important to
notice that the CMOS does not contain any resistors, which makes it more power
efficient that a regular resistor-MOSFET inverter.As the voltage at the input of
the CMOS device varies between 0 and 5 volts, the state of the NMOS and PMOS
varies accordingly.
Figure1 (a) Inverter Schematic 3

Assignment:
Note: Use 180 nm CMOS model from GPDK available in the library. Assume
maximum supply voltage for this technology is 1.8 V. The nominal conditions
are: wn = 1 µm, wp = 2 µm and channel length is 180 nm, Temperature is 27 ˚C.
1. Draw the schematic of a CMOS inverter. Obtain its DC transfer characteristics

and Transient response for nominal conditions.
2. Do the parametric analysis for different W/L ratios of the inverter circuit.
[Hint: Vary wp from 2 µm to 10 µm in step size of 1 µm]
3. Do the parametric analysis for different temperature conditions. Take the

temperature values as -40˚C, 27˚C, and 100˚C.
i) Plot the DC transfer characteristics and tabulate transition voltages
for nominally sized inverter.
ii) Tabulate the rising and falling delay for nominally sized inverter.
[Hint: Use expressions in calculator]
Comment on the results obtained.
Observation table:
Wp(microns) Vinv(V)
4
Conclusion:
Practice Questions:
1. What is noise margin of a CMOS inverter?
2. Explain sizing of an inverter?
3. Draw and explain the transfer curve of an inverter?
5
EXPERIMENT 2: Layout Design
Objective: Perform Layout design of a CMOS Inverter in Cadence
Virtuoso Layout Editor. Perform DRC, LVS and RCX. Obtain the DC
transfer characteristics and transient response for different widths and
temperature conditions and compare with the values obtained in
Experiment 1.
Theory: Design rule checking or check(s) (DRC) is the area of electronic design
automation that determines whether the physical layout of a particular chip layout
satisfies a series of recommended parameters called design rules.
The Layout Versus Schematic (LVS) is the class of electronic design automation
(EDA) verification software that determines whether a particular integrated circuit
layout corresponds to the original schematic or circuit diagram of the design.
Pre Layout simulation: It is the functional verification of the design without

including the parasitics, which gets added to the design when the design is
physically implemented or laid out.
Post Layout Simulation: The parasitic capacitances extracted according to how

layout is designed might be critical in affecting the actual performance of the
design. In order to get an idea of how the design would work from the layout, you
should perform a post-layout simulationfrom the extracted view.
6
LAYOUT VIEW OF AN INVERTER
Figure 2: Inverter layout Schematic
Observation:
7
Calculation:
Pre-Layout Simulation value of rise and fall time=_____ps
Post- Layout Simulation value of rise and fall time= ____ps
Pre-Layout Simulation value of propagation Delay = ____ps
Post-Layout Simulation value of propagation Delay = ____ps
Conclusion:
Practice Questions:
1. Give five important design technique to follow when doing a layout design of
digital circuit?
2.What do you mean by FEOL and BEOL process?
3. What should be the n-diffusion and p-diffusion layer in lambda rule?
8
EXPERIMENT 3:
Objective: Extraction of Logical effort and parasitic delay of a CMOS
inverter.
Theory: Logical effort of a logic gate is defined as the ratio of its input
capacitance to that of an inverter that delivers equal output current. The method
of logic effort is an easy way to estimate delay in a CMOS circuit. We can select
the fastest candidate by comparing delay estimates of different logic structures.
The method also specifies the proper number of logic stages on a path and the
best transistor sizes for the logic gates.
Parasitic delay is the delay due to intrinsic delay of gate mostly the drain
capacitance. It is independent of output load and sizing.
The delay incurred by a logic gate is comprised of two components:
• A fixed part called as the parasitic delay, p.
• A part that is proportional to the load on the gate’s output, called the effort
delay or stage effort, f.
d=f+p
The effort delay depends on the load and on properties of the logic gate driving
the load. We introduce two related terms for these effects:
• The logical effort, g captures properties of the logic gate.
• The electrical effort h characterizes the load.
f = gh
Therefore, d = gh +p.
9
Multi-stage Inverter with a FAN-OUT-4
Figure 3(a): Schematic Representation of Multi-stage inverter logic network

with a fan-out- 4.
Observation:
Rising propagation delay time (tpdr1) = ____ps
Falling propagation delay time (tpdf1) = ____ps
Calculation:
FO4 delay = (tpdr1 + tpdf1)/2 = 5τ
τ= time constant in ps
10
Multi-stage Inverter with a FAN-OUT-1 :
Figure 3(b): Schematic Representation of Multi-stage inverter logic network

with a fanout-of-1
Observation:
Rising propagation delay time (tpdr2) = ___ps

Falling propagation delay time (tpdf2) = ___ps
Calculation:
According to d = gh +p, now we have two equations,
𝑡𝑝𝑑𝑟1 + 𝑡𝑝𝑑𝑓1
= 𝑔𝑥4 + 𝑝
2
𝑡𝑝𝑑𝑟2 + 𝑡𝑝𝑑𝑓2
= 𝑔𝑥1 + 𝑝
2
11
By solving above 2 equations,
g=
p=
Conclusion:
Practice Questions:
1. What is propagation delay?
2.What happens to delay if load capacitance is increased?
3.Why is rise time greater than fall time?
12
EXPERIMENT 4: D-latch and D-Flip Flop.
Objective: Design and characterization of D-Latch and D-FlipFlop in
CMOS Technology.
Theory:
D-latch: Latch is an electronic device that can be used to store one bit of
information. The D latch is used to capture, or 'latch' the logic level which is
present on the Data line when the clock input is high or low depending on the
type of level triggering.
High level triggering: If the data on the D line changes state while the clock pulse
is high, then the output, Q, follows the input, D. When the CLK input falls to
logic 0, the last state of the D input is trapped and held in the latch.
Low level triggering: If the data on the D line changes state while the clock pulse
is low, then the output, Q, follows the input, D. When the CLK input rises to logic
1, the last state of the D input is trapped and held in the latch.
D-flipflop: The working of D flip flop is similar to the D latch except that the
output of D Flip Flop takes the state of the D input at the moment of a positive
edge at the clock pin (or negative edge if the clock input is active low) and delays
it by one clock cycle. That's why, it is commonly known as a delay flip flop. The
D flipflop can be interpreted as a delay line or zero order hold. The advantage of
the D flip-flop over the D-type "transparent latch" is that the signal on the D input
pin is captured the moment the flip-flop is clocked, and subsequent changes on
the D input will be ignored until the next clock event.
13
Assignment:
1. To Design a D latch using transmission gates as shown in fig.4 (a).
2. To Design a D flip-flop using transmission gates as shown in fig.4 (b).
Conditions for Modelling:
• 180 nm CMOS model from GPDK

• wn = 1μm, wp = 2μm, channel length = 180 nm, temperature = 27 ˚C.
Figure 4(a): D-latch
Figure 4(b): D-flipflop 14

Observation:
Clock Parameters: Rise time =___ ps

Fall time = ___ps,
Pulse width = ___ ns,
Period = ___ ns,
Input Parameters: Rise time = ___ ps

Fall time =___ps,
Pulse width = ___ ns,
Period =___ ns,
Output Parameters: Rise time = ___ ps

Fall time =___ps,
Propagation delay = ___ ns,
Conclusion:
Practice Questions:
1. What is the difference between D latch and D flip-flop?
2. Write down the characteristic equation of D flip-flop?
3. Describe the operation of a negative edge triggered D flip-flop?
15

Experiment 1: Cmos Inverter: Objective: Design A Schematic of A CMOS Inverter in Cadence

Uploaded by

Copyright:

Available Formats

Experiment 1: Cmos Inverter: Objective: Design A Schematic of A CMOS Inverter in Cadence

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Experiment 1: Cmos Inverter: Objective: Design A Schematic of A CMOS Inverter in Cadence

Uploaded by

Copyright:

Available Formats

EXPERIMENT 1: CMOS INVERTER

Objective: Design a schematic of a CMOS Inverter in Cadence

Figure1 (a) Inverter Schematic 3

1. Draw the schematic of a CMOS inverter. Obtain its DC transfer characteristics

3. Do the parametric analysis for different temperature conditions. Take the

Pre Layout simulation: It is the functional verification of the design without

Post Layout Simulation: The parasitic capacitances extracted according to how

Figure 2: Inverter layout Schematic

Post- Layout Simulation value of rise and fall time= ____ps

Pre-Layout Simulation value of propagation Delay = ____ps

Post-Layout Simulation value of propagation Delay = ____ps

Figure 3(a): Schematic Representation of Multi-stage inverter logic network

Figure 3(b): Schematic Representation of Multi-stage inverter logic network

Rising propagation delay time (tpdr2) = ___ps

2. To Design a D flip-flop using transmission gates as shown in fig.4 (b).

Conditions for Modelling:

• 180 nm CMOS model from GPDK

Figure 4(a): D-latch

Figure 4(b): D-flipflop 14

Clock Parameters: Rise time =___ ps

Input Parameters: Rise time = ___ ps

Output Parameters: Rise time = ___ ps

You might also like