IO LAYOUT AND AUTOMATION

SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE

AWARD OF DEGREE OF

BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION

Submitted by

Name: Manalika Sharma

University Roll No: 1903748

Under the supervision of

Company Name: ST Microelectronics PVT. LTD

Project Manager: Mr. Manish

DEPARTMENT OF INFORMATION TECHNOLOGY

DAV INSTITUTE OF ENGINEERING & TECHNOLOGY

Jalandhar – 144008

June 2023
 CERTIFICATE OF COMPLETION OF TRAINING

This is to certify that Miss Manalika Sharma (Student of B. Tech. E.C.E of DAV Institute of
Engineering and Technology, Jalandhar) is successfully completing his Industrial Training
from “28/07/2022” to “16/06/2023”. During this training, she has worked as Layout
Engineer in TRD under the guidance of Mr. Manish.

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 ABSTRACT
ST Microelectronics Private Limited is a global, semiconductor company that designs, develops,
manufactures and markets a broad range of semiconductor integrated circuits and discrete devices.
Company has many customers with whom business transactions occur across the globe, the customer list
includes electronic giants like Seagate, Samsung, Apple and Ericsson. Communication with the customer
is obviously the key to have relationship with them. Clear, timely, transparent communication will gain
and maintain a customer’s trust and respect.

This report will serve as literary piece written for the purpose of acquainting the reader with the technical
background required to understand the report, what the problem is, how this project has been planned to
develop, how the project development is proceeding and how the results will help to eradicate the related
problems to application release.

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 ACKNOWLEDGEMENT

I am highly grateful to the Dr. Sanjeev Naval, Principal, DAV Institute of Engineering & Technology,
Jalandhar, for providing this opportunity to carry out the eleven months Industrial Training at ST
Microelectronics.

The constant guidance and encouragement received from Mrs. Neeru Malhotra, HOD Department of
Electronics and Communication, DAVIET Jalandhar has been of great help in carrying out the project
work and is acknowledged with reverential thanks.

I would like to express a deep sense of gratitude and thanks profusely to Jean-Marc Chery (CEO) of ST
Microelectronics. Without wise counsel and able guidance, it would have been impossible to complete the
report in this manner.

The help rendered by Mr. Manish (ST Microelectronics) for experimentation is greatly acknowledged. I
would like to thank him for being a beacon of guidance and inspiration throughout the internship tenure. I
would like to thank my team members who were both a friend and a teacher for me.

I express gratitude to other faculty members of ECE department of DAVIET for their intellectual support
throughout the course of this work. I extend my deep gratitude to Mrs. Neeru for smoothening the whole
training semester experience and being available to resolve my problems at all times.

Manalika

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 LIST OF FIGURES

Fig. No. Figure Description Page No.

1.1 ST Logo 1
1.2 ST Leadership Model 2
2.1 WWDC environment 3
4.1 Detail process used in the operations automation 13
4.2 DTIT Remedy Status Flow 14
4.3 Interaction between Incident & Change 15
Management Process
5.1 BASH Logo 16
5.2 Python logo 17
5.3 BASH script format 19
5.4 Schedule Format 22

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 TABLE OF CONTENTS

Contents Page No.

Certificate i
Abstract ii
Acknowledgement iii
List of Figures iv
Table of Contents v

Chapter 1 Introduction
1.1 Introduction to Organization
1.2 Introduction to Project
1.3 Project Category
1.4 Objectives
1.5 Problem Formulation
1.6 Identification/Reorganization of Need
1.7 Existing System
1.8 Unique Features of the System

Chapter 2. Requirement Analysis and System Specification

2.1 Feasibility study
2.2 Software Requirement Specification Document
2.3 Validation
2.4 Expected hurdles
2.5 SDLC model to be used

Chapter 3. System Design

3.1 Design Approach
3.2 Detail Design
3.3 System Design
3.4 User Interface Design
3.5 Database Design
3.5.1 ER Diagrams
3.5.2 Normalization
3.5.3 Database Connection Controls and Strings
3.6 Methodology of system

Chapter 4. Implementation, Testing and Maintenance

4.1 Introduction to Languages, IDE’s, Tools and Technologies used for
Implementation
4.2 Coding standards of Language used
4.3Testing Techniques and Test Plans

Chapter 5. Results and Discussions

5.1 User Interface Representation (Of Respective Project)
5.1.1 Brief Description of Various Modules of the system

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5.2 Snapshots of system with brief detail of each
5.3 Back Ends Representation (Database to be used)
5.3.1 Snapshots of Database Tables with brief description
Chapter 6. Conclusion and Future Scope

References/Bibliography

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 CHAPTER1: INTRODUCTION

1.1 Introduction to Organization

STMicroelectronics is a global independent semiconductor company and a leader in developing

and delivering semiconductor solutions across the spectrum of microelectronics applications.
An unrivalled combination of silicon and system expertise, manufacturing strength, Intellectual
Property (IP) portfolio and strategic partners positions the Company at the forefront of System-
on-Chip (SOC) technology and its products play a key role in enabling today’s convergence
trends.

STM has developed FDSOI Technology, for 28nm it has given the best result among the best
leading semiconductor companies. STM recent projects are on IOT (Internet of Things) and
Smart Driving. Other than this also there are multiple things like MEMS leadership, smart
sensors and provide multiple IPs with full custom flow or ASIC Flow. There are multiple
groups like TRD which works on IP Libs, ADC/DAC, I/O etc. APG department works at SOC
level, Smart Driving projects, IOT. The ICT Department helps regarding tool support,
information security and much more.

Fig1.1 Logo of ST Microelectronics

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1.2 Introduction to Project
The internship program extending from July 2022 to June 2023 includes work on quality
oriented and productivity-oriented automations as well as designing and validating I/O
(input/output circuits) layouts. Internally focused quality-oriented automation solutions have
been developed, in addition to the understanding and development of layout designs.
Automation solutions were built using shell scripting. Layout design began with a thorough
understanding of the top and cross-sectional views of basic devices such as MOSFETs, BJTs,
capacitors, and resistors. Following that, the complexities of the various layers involved in
layout design were comprehended. Subsequently, the layout design of fundamental devices
was practiced before going on to the layout design of an actual leaf cell circuit. Next, the many
validation checks performed on a layout circuit, such as DRC, LVS, ESD, and DFM, were
understood. Validation checks were performed using tools such as LIBBE, DIOT, and ADOC.
A fundamental grasp of top-level circuit integration was developed while updating the existing
layouts along with creating the layout designs for leaf cells including inverters, buffers, level
shifters, and multiplexers from scratch.

One of the highlights of my internship was the opportunity to develop a Graphical User
Interface (GUI) using Python. Recognizing the need for an intuitive and interactive
environment to streamline the design process, I took the initiative to create a sleek and modern
GUI that would enhance efficiency and facilitate seamless experimentation with different
design elements. With the GUI in place, I was able to efficiently manipulate and arrange
content, fine-tuning the overall look and feel of the layouts. The intuitive controls and
functionalities offered by the GUI empowered me to iterate quickly, making real-time
adjustments and experimenting with various design options. This iterative process allowed me
to explore different color schemes, typography, and visual hierarchy, ensuring that each layout
I created was visually striking and user-friendly.

Overall, my experience as a layout design intern and my contribution in developing a Python-

based GUI were invaluable. This project allowed me to further hone my skills in layout design,
programming, and collaboration. It also highlighted the importance of merging technical
expertise with artistic sensibilities to create visually stunning and user-friendly digital layouts.
I am grateful for the opportunity to have worked on this project, as it has provided me with a
solid foundation for future endeavors in the field of design and technology.

1.3 Project Category

Semiconductor wafer on which thousands or millions of small resistors, capacitors, diodes, and
transistors are manufactured is known as an integrated circuit (IC), also known as a chip,
microchip, or microelectronic circuit. The cornerstone of all contemporary electronic gadgets
is an integrated circuit (IC) [1]. As implied by the name, it is an integrated system made up of
numerous connected, tiny components that are implanted in a thin semiconductor substrate
(usually silicon crystal) [2]. Due to its tiny size, excellent reliability, and high efficiency, ICs
are used in nearly all modern electronic devices, including computers, cell phones,

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automobiles, televisions, and digital watches. Electronic devices would be much slower and
bulkier without ICs. The Layout view of these circuitries refers to the CAD view representation
of a chip that has polygons or geometries indicating the physical view of devices and their
interconnections. Various intellectual properties(IP) might be present on a chip, such as I/O,
ADC, PLL Memory, etc. This work is focused on designing and validating I/O(input/output
circuits) layouts as well as developing and upgrading quality oriented and productivity-oriented
flow facilitating automations that enhances the development and deliverance of the I/O
products. 1.1 Integrated Circuits of I/Os (input/output) The chip or integrated circuit that houses
a number of computer parts on a single substrate, such as silicon, typically the CPU (via a
microprocessor or microcontroller), memory, input/output (I/O) ports, and secondary storage
is known as a SoC(System on a Chip) [3]. Core and I/O controllers are the two functional
sections that make up any SoC. The logic for which the chip was intended is carried out by the
core, and the link between that logic and the system components is made possible by the I/O
circuits, which are cells in the chip. Fig. 1.1 shows the components of a typical I/O circuit [4].
7 Figure 1.1: Components of a typical IO circuit In this work the focus will be on creating the
layouts of I/O components of the I/O blocks shown in the fig. 1.1 which includes inverter,
buffer, multiplexer and level shifters etc. 1.2 Layout Design: Integrated circuit layout,
sometimes referred to as IC layout, IC mask layout, or mask design, is the modeling of an
integrated circuit using planar geometric shapes that corresponds to the patterns of
semiconductor, metal, or oxide layers that make up the components of the integrated circuit
[5]. On the circuit layout many checks including DRC, LVS, ESD, and DFM are carried out
using various tools in order to make sure that any deliverable in efficient and reliable. 1.3
Quality-Oriented and Productivity-Oriented Automations The final deliverable layout of an I/O
circuit is a collection of all the files required to access and use the I/O and not just the layout
circuit itself. Some of these files contain the information needed to open the cadence window
for a specific technology, while others contain vital details about the circuit itself, such as the
technology name, the name of the process design kit, the name of the library, the version of the
library, the name of the package, etc. Some of these files are created as reports when various
checks are performed on the circuit in question. All of these files are kept in a library structure
that is well defined. The cds.lib and ucd.prod files are two crucial ones that are needed to start
the cadence. Information about all the libraries to be used for design is contained in the file
cds.lib. The specifics of the tools that will be applied to the design are of interest to. ucdprod.
As a result, a delivery needs to provide the back-end path to these files. It is now crucial to
check whether all the required files are present before launching a 8 product. A redundant
library, file, or piece of data should be checked for and eliminated from the deliverables. These
procedures were traditionally performed manually and so were prone to human errors. Even
though these manual inspections were cross-checked numerous times, there was still a chance
of missing something. Here, the deployment of productivity- and quality-focused automations
can not only minimize manual labor but also increase the task’s effectiveness and reliability.
These automation products, which primarily deal with file management, are executed using
shell scripting. Also, aspects of layout design can be automated with SKILL. Layout
automations include improving the cadence menu, integrating various tools, and even
automatically creating preliminary layouts.

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 Fig 1.2

1.4 Objectives
Being a layout intern I had certain objectives for myself which included the following :

1. Provide a comprehensive overview of the internship experience as a Semiconductor

Layout Intern, showcasing the knowledge and skills gained during the period.

2. Demonstrate proficiency in semiconductor layout design, highlighting the ability to

create effective and efficient layouts for integrated circuits.

3. Showcase expertise in shell scripting and Linux, emphasizing the utilization of these
skills in automating layout design tasks and improving productivity.

4. Highlight the development of a Graphical User Interface (GUI) using Tkinter in

Python, showcasing the ability to create intuitive and user-friendly tools for layout
design.

5. Discuss the challenges faced during the internship, such as complex layout
requirements or technical limitations, and demonstrate the problem-solving skills
employed to overcome these challenges.

6. Present the accomplishments and deliverables achieved during the internship,

including completed layout designs, successful script implementations, and the
functional GUI developed.

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 7. Reflect on personal and professional development throughout the internship,
emphasizing the growth in technical skills, collaboration abilities, adaptability, and
time management.

8. Evaluate the impact of the internship experience on the understanding of

semiconductor layout design principles, industry insights, and best practices.

9. Provide recommendations for future improvements in the field of semiconductor

layout design, including advancements in design tools, automation techniques, and
integration of emerging technologies.

1.5 Problem Formulation

The problem formulation aims to define and outline these challenges concisely and
accurately. The following problem areas were identified:

1. Complex Layout Requirements: The intricate nature of semiconductor layout design

often involves intricate specifications and requirements. This complexity can pose
challenges in terms of achieving design accuracy, optimizing performance, and
ensuring adherence to design rules and guidelines.

2. Technical Limitations: The design software and tools used in semiconductor layout
design may have limitations in terms of functionality, speed, or compatibility. These
limitations can impact the efficiency and effectiveness of the design process,
hindering the ability to meet project deadlines and deliver high-quality layouts.

3. Automation and Scripting: Developing efficient and robust scripts for automation in
layout design tasks can be challenging. Creating scripts that handle various design
scenarios, ensure error-free outputs, and enhance productivity requires a deep
understanding of scripting languages and familiarity with layout design concepts.

4. GUI Development: Developing a user-friendly and intuitive Graphical User Interface

(GUI) for layout design using Tkinter in Python poses challenges in terms of interface
design, functionality implementation, and ensuring compatibility across different
operating systems. Balancing aesthetics, usability, and responsiveness in the GUI
design is crucial for an optimal user experience.

5. Collaboration and Communication: Effective collaboration and communication within

the design team and with other stakeholders are essential for successful layout design
projects. Challenges may arise in terms of coordinating design efforts, incorporating
feedback and changes, and maintaining clear and concise communication throughout
the design process.

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 6. Time Management: Efficiently managing time and resources is critical in meeting
project deadlines and ensuring timely completion of layout design tasks. Balancing
multiple projects, prioritizing tasks, and effectively allocating time for problem-
solving and refinement can present challenges, especially in a fast-paced and
demanding work environment.

By clearly formulating and addressing these problems, the internship report will provide a
comprehensive understanding of the challenges faced during the semiconductor layout
internship and demonstrate the problem-solving approaches employed to overcome them.

1.6 Identification/Reorganization of Need

During the semiconductor layout internship, certain needs were identified that required
attention and reorganization to optimize the design process and improve overall efficiency.
The identification and reorganization of these needs are crucial for enhancing productivity,
reducing errors, and ensuring the successful completion of layout design projects. The
following needs were identified:

1. Streamlined Design Workflow: There is a need for a more streamlined and efficient
design workflow that minimizes redundant tasks, reduces manual intervention, and
improves overall productivity. This involves identifying bottlenecks in the current
workflow, exploring automation opportunities, and optimizing the sequence of design
tasks to maximize efficiency.

2. Enhanced Collaboration and Communication: Improving collaboration and

communication among team members and other stakeholders is vital for successful
layout design projects. This includes the need for effective project management tools,
clear communication channels, and streamlined feedback processes to ensure
seamless coordination, timely sharing of information, and efficient resolution of
design-related queries.

3. Advanced Design Tools and Technologies: Upgrading and leveraging advanced

design tools and technologies is crucial to stay at the forefront of semiconductor
layout design. This involves identifying opportunities to incorporate state-of-the-art
design software, simulation tools, and methodologies that enhance accuracy, speed up
the design process, and enable the exploration of innovative design solutions.

4. Standardization and Design Reusability: Establishing standardized design

methodologies and promoting design reusability can significantly improve efficiency
and consistency in layout design. This includes the need for creating and maintaining
a library of reusable design components, templates, and guidelines that facilitate faster
layout generation and ensure adherence to design standards.

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 5. Continuous Learning and Skill Development: Given the rapidly evolving nature of
semiconductor layout design, there is a need to foster a culture of continuous learning
and skill development among layout design professionals. This involves providing
access to training programs, workshops, and resources that enable designers to stay
updated with the latest industry trends, emerging technologies, and design
methodologies.

6. Quality Assurance and Error Prevention: Enhancing quality assurance processes and
implementing measures to prevent errors are critical to ensuring the delivery of
accurate and reliable layout designs. This includes the need for comprehensive design
verification techniques, thorough error checking procedures, and rigorous quality
control measures to minimize design flaws and reduce the need for rework.

1.7 Existing System

When analyzing the existing system in semiconductor layout design, it can be categorized
into several key areas. Understanding these categories provides insight into the current state
of the layout design process and the technologies employed. The existing system can be
classified into the following categories:

1. Layout Design Tools: This category includes the software tools and applications used
for semiconductor layout design. These tools range from industry-standard Electronic
Design Automation (EDA) software suites to specialized tools for specific design
aspects, such as physical layout editors, schematic capture tools, and verification
tools.
2. Design Methodologies: This category encompasses the design methodologies
employed in semiconductor layout design. It includes approaches like custom layout
design, standard cell-based design, and various integration techniques for analog,
digital, and mixed-signal designs. Design methodologies may also incorporate
specific techniques for power optimization, signal integrity, and Design for
Manufacturability (DFM).
3. Scripting and Automation: Semiconductor layout design often involves scripting and
automation to improve productivity and efficiency. This category covers scripting
languages, such as Tcl, Perl, and Python, used to automate repetitive tasks, generate
layout templates, and perform design rule checks (DRC) and layout versus schematic
(LVS) checks.
4. Design Libraries and IP Cores: Design libraries and Intellectual Property (IP) cores
provide a repository of pre-designed and verified building blocks for semiconductor
layout design. These components include standard cells, memory cells, analog blocks,
and interface IP cores. Designers can leverage these libraries to speed up the layout
process and ensure design consistency.

1.8 Unique Features of the System

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While analyzing the existing system in semiconductor layout design, several unique features
and capabilities set it apart from other domains. These distinctive characteristics contribute to
the efficiency, accuracy, and advancement of the layout design process. The unique features
of the system include:
1. Customization for Integrated Circuit (IC) Design: The system offers extensive
customization options to cater to the specific requirements of IC design. It allows
designers to create layouts tailored to the target application, optimizing factors like
performance, power consumption, area utilization, and manufacturability.
2. Design Rule Checks (DRC) and Design for Manufacturability (DFM): The system
incorporates sophisticated DRC tools and DFM techniques to ensure that the layout
design adheres to the manufacturing constraints and standards. These features identify
potential manufacturing issues early in the design process, reducing the risk of yield
loss and enhancing the manufacturability of the final product.
3. Parasitic Extraction and Analysis: The system provides robust tools for parasitic
extraction and analysis, allowing designers to accurately model and simulate the
parasitic effects that can impact circuit performance. This enables designers to
optimize their layouts by considering parasitic elements such as resistance,
capacitance, and inductance.
4. Integration of Analog and Digital Designs: The system offers seamless integration of
analog and digital designs within a single layout. This feature enables the efficient
integration of various circuit blocks, such as analog front-ends, digital signal
processing units, and memory elements, into a unified layout, ensuring optimal
performance and functionality.
5. Advanced Power Optimization Techniques: Power optimization is a critical concern
in modern semiconductor designs. The system incorporates advanced power
optimization techniques, such as power gating, voltage scaling, and clock gating, to
minimize power consumption while maintaining the desired functionality and
performance.
6. Design Reuse and Intellectual Property (IP) Integration: The system facilitates design
reuse through the integration of Intellectual Property (IP) cores and pre-designed
building blocks. Designers can leverage a wide range of IP cores for standard
functions, reducing design time, and ensuring consistency in design quality across
projects.
7. Cross-Platform Collaboration: The system supports cross-platform collaboration,
enabling design teams to work seamlessly across different operating systems and
environments. This feature promotes efficient teamwork, allowing designers to
collaborate on layouts, exchange design files, and track revisions using version
control systems.
8. Integration with Process Design Kits (PDKs): The system seamlessly integrates with
Process Design Kits (PDKs) provided by semiconductor foundries. PDKs contain
process-specific information, such as transistor models, layout rules, and device
parameters, enabling designers to ensure compliance with foundry-specific design
guidelines.

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 9. Continuous Updates and Support: The system benefits from continuous updates and
support from vendors, ensuring that designers have access to the latest features, bug
fixes, and advancements in layout design methodologies. This enables designers to
stay at the forefront of technology and leverage the most up-to-date tools and
techniques.
These unique features of the system contribute to its effectiveness and efficiency in
semiconductor layout design. By leveraging these capabilities, designers can optimize their
layouts, improve design quality, reduce time-to-market, and achieve superior performance for
integrated circuits.

Chapter 2: Requirement Analysis and System Specification

2.1 Feasibility study

i. Unix and Layout Design Training:
During my three-week Unix training, I had the privilege of receiving personalized
guidance from my mentor. The training focused on equipping me with a solid
understanding of basic Unix concepts and fabrication principles, which I can apply to
my future projects.

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 Fig2.1

What made this training experience exceptional was the approach taken by my
mentor. Instead of following a rigid curriculum, my mentor customized the sessions to
address my specific needs and learning style. This personalized approach ensured that
I received targeted instruction and support tailored to my individual requirements.

I am grateful for the personalized guidance and mentorship I received during this
training. The knowledge and skills gained will undoubtedly prove valuable as I
embark on future projects, where a strong foundation in Unix and fabrication concepts
is essential.

The training covered the following modules.

• Unix Fundamentals
• CSH scripting
• PERL scripting
• Cadence Virtuoso tool Overview
• IO Layout Architecture Overview
• IC Fabrication steps

Result/Outcomes:
• Understood the LINUX environment. Got familiar with CLI (Command Line
Interface).

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 • Learnt various UNIX commands and applied them in the terminal. E.g. Awk, grep,
sed.
• Learnt new scripting languages, SHELL and PERL.
• Worked on error flow check and updates on an ongoing script in SHELL
comprising of 2000+ lines of code.
• Understood the fabrication steps and various industry level techniques.
• Understanding of Layout Design of analog IP’s using Cadence Virtuoso tool.

ii. Project Oriented Training

This training was more project oriented, and the concepts taught in this training would be
required for the project point of view.
The modules in this training were:
• Python Scripting:

One of the modules covered during the training was Python scripting. This module aimed to
provide a comprehensive understanding of Python programming, specifically tailored for
project-related tasks. The training likely covered essential concepts and techniques in Python,
such as variables, data types, control structures, functions, and file handling in Python.

During this module, I actively engaged in various hands-on exercises and

assignments to strengthen my Python skills. I learned how to leverage
Python's capabilities for file handling, enabling efficient data processing and
manipulation. This knowledge equipped me with a valuable tool for
automating repetitive tasks and enhancing project efficiency.

• Knowledge of DRC, LVS, and Post Layout Extraction Tools:

During the training program, a significant module focused on developing a

deep understanding of Design Rule Checking (DRC), Layout Versus
Schematic (LVS), and post layout extraction tools. These tools play a crucial
role in the semiconductor industry for ensuring design integrity, verifying the
accuracy of layouts, and analyzing electrical properties.

Design Rule Checking (DRC):

Design Rule Checking (DRC) is a critical step in the physical design process.
It involves verifying whether a layout design adheres to a set of predefined
design rules and manufacturing constraints. These rules ensure that the design
can be successfully fabricated and that it meets the performance and reliability
requirements.

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 DRC checks the geometry, spacing, and alignment of layout elements to detect
potential issues such as shorts, opens, or violations of minimum/maximum
dimensions. By detecting and resolving these errors early in the design phase,
DRC helps prevent costly and time-consuming rework during fabrication.

Layout Versus Schematic (LVS):

Layout Versus Schematic (LVS) is a verification process that compares the

geometric layout of a design with its corresponding electrical schematic. LVS
ensures that the layout accurately represents the intended circuit functionality
and that there are no discrepancies between the two representations.

The LVS tool analyzes the connectivity and properties of the layout's
transistors, resistors, capacitors, and other components and compares them
against the netlist generated from the schematic. It verifies that the electrical
connections and properties match, identifying any errors or inconsistencies
that could affect circuit performance.

Post Layout Extraction Tools:

Post layout extraction tools extract various electrical properties and

characteristics from the layout design. These tools analyze the layout and
provide important information such as parasitic capacitance, resistance, and
interconnect delay. This extracted data is used for accurate circuit simulation,
timing analysis, and optimization.

Post layout extraction enables designers to understand the impact of parasitic

elements and interconnect on the circuit's performance. It helps identify potential
signal integrity issues, timing violations, and power consumption concerns, enabling
designers to fine-tune and optimize the design for better performance.

Table 2.2

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 Fig 2.2
2.2 Expected Hurdles

1. Changing Requirements: Requirements are subject to change throughout the project

lifecycle due to evolving business needs, market dynamics, or technological advancements.
This dynamic nature of requirements poses a challenge as it can impact project timelines,
resources, and overall project scope. The report should acknowledge the possibility of
changing requirements and suggest approaches for managing requirements changes
effectively, such as implementing change control processes and conducting impact
assessments.

2. Technical Constraints and Limitations: Requirement analysis may encounter technical

constraints or limitations, such as compatibility issues with existing systems, resource
limitations, or budgetary constraints. These factors can impact the feasibility and
implementation of certain requirements. The report should highlight the potential technical
challenges and propose strategies to address them, such as conducting technical assessments,
exploring alternative solutions, or seeking expert consultation.

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3. Communication and Documentation: Effective communication and documentation are vital
for successful requirement analysis. However, challenges may arise due to communication
gaps, misinterpretation of requirements, or inadequate documentation. The report should
emphasize the importance of clear and concise communication, standardized documentation
practices, and the use of visual aids (such as diagrams or prototypes) to enhance
understanding and mitigate communication-related hurdles.

CHAPTER 3 SYSTEM DESIGN

During my internship of 11 months, I have been mostly focused on two approaches which are
as follows:
1. The first approach was working on the layout of different basic semiconductor devices like
pmos, nmos, buffer etc. and then moving on with layout of different blocks of an IP.
2. The second approach included Scripting. Scripting was mostly done in 2 languages shell
and python.

So, in this chapter I will be discussing the first part of my project. It will show the detailed
system design of small semiconductor devices and then explaining the process of a block.

3.1 Design Approach

Beginning by practicing the layouts of NMOS and PMOS transistors. NMOS is an
enhancement-mode transistor, where the channel is formed by electrons, while PMOS is a

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depletion-mode transistor, where the channel is formed by holes. These transistors are
fundamental building blocks in modern integrated circuits.

In the layout of an NMOS transistor, the N-doped source and drain regions are represented by
rectangular shapes, while the gate is placed in between. The layout of the NMOS transistor
follows similar principles as the PMOS transistor, with careful attention to channel length,
gate width, and gate-to-source/drain spacing. Proper alignment and spacing between the
various components are critical for achieving efficient signal flow, minimizing leakage
currents, and maintaining overall circuit performance.

Fig3.1 Snapshot of layout of NMOS

In the layout of a PMOS transistor, the P-doped region, known as the source and drain
regions, is typically represented by rectangular shapes. The gate, consisting of a metal layer
or polysilicon material, is placed between the source and drain regions. The proper alignment
and spacing of the gate with respect to the source and drain regions ensure optimal transistor
performance and functionality. Additionally, considerations for channel length, gate width,
and gate-to-source/drain spacing are essential to meet the design specifications and minimize
parasitic effects.

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 Fig 3.2 Snapshot of Layout of PMOS

In both the PMOS and NMOS transistor layouts, specific design rules and guidelines must be
followed to ensure proper connectivity, area utilization, and adherence to manufacturing
processes. These design rules include considerations for spacing, width, and alignment, as
well as requirements for power and ground connections, metal routing, and shielding.

3.2 Detail Design

3.2.1 Created a layout design of a flip flop and cleaned DRC and LVS using Cadence
Virtuoso tool after practicing PMOS, NMOS and CMOS inverter.
➢ Introduction to Flip Flop Design
Flip flops are essential components in digital circuit design, enabling the storage and
sequential processing of data. In this project, the focus was on designing a layout for a flip
flop using Cadence Virtuoso tool.

➢ Design Methodology
The design methodology followed for the flip flop layout involved several steps, including
schematic design, component placement, and routing. These steps were crucial in achieving
the desired functionality and performance of the flip flop.

➢ Layout Design of Flip Flop

The layout design of the flip flop included the integration of PMOS, NMOS, and CMOS
inverters. These inverters were appropriately connected and interconnected to establish the
necessary flip flop structure. The layout design adhered to the specified design rules and
constraints.

➢ Design Rule Check (DRC) Cleanup

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To ensure compliance with fabrication rules, a Design Rule Check (DRC) cleanup process
was performed using Cadence Virtuoso. Any violations identified during the DRC analysis
were resolved by making necessary modifications to the layout design.

➢ Layout vs. Schematic (LVS) Cleanup

Layout vs. Schematic (LVS) cleanup was carried out to verify the consistency between the
layout and the schematic design of the flip flop. The LVS analysis helped identify any
discrepancies and ensure that the layout accurately represented the intended circuit.

Fig 3.2.1
3.2.2 Created a layout design of a buffer using Cadence Virtuoso with clean DRC and LVS.

Cadence Virtuoso is a widely used electronic design automation tool that facilitates the
creation and verification of layout designs. Here, we highlight the key aspects of the buffer
layout design using Cadence Virtuoso:
1. Initial Schematic Design: Begin by creating a schematic diagram of the buffer circuit
using Cadence Virtuoso's schematic editor. Define the input and output ports, as well
as the internal components of the buffer, such as the NMOS and PMOS transistors.
2. Layout Generation: Utilize Cadence Virtuoso's layout editor to generate the physical
layout of the buffer circuit based on the schematic design. This involves placing the
transistors, routing the interconnections, and allocating power and ground
connections.
3. Component Placement: Carefully place the NMOS and PMOS transistors within the
layout to optimize performance and minimize parasitic effects. Consider factors such
as proximity to input/output ports, signal integrity, and routing efficiency.
4. Routing: Use Cadence Virtuoso's routing capabilities to establish the interconnections
between different components of the buffer circuit. Route the input and output signals,

17
 power, ground, and any necessary biasing lines while adhering to design rules and
guidelines.
5. Design Rule Check (DRC): Perform a thorough DRC using Cadence Virtuoso's DRC
tool to ensure compliance with the design rules specified by the fabrication process.
This step checks for violations of minimum spacing, width, and other design
constraints, ensuring that the layout is compatible with the manufacturing process.
6. Layout Versus Schematic (LVS) Verification: Conduct an LVS verification to confirm
that the layout matches the intended circuit schematic. This validation ensures that the
layout accurately reflects the electrical connectivity and functionality of the buffer
circuit.
7. Iterative Optimization: Iterate through the layout design, making adjustments and
refinements as needed to improve performance, area utilization, and
manufacturability. Optimize the dimensions, placement, and routing to achieve the
desired electrical characteristics while adhering to the limitations imposed by the
fabrication process.
8. Final Review and Documentation: Review the completed buffer layout design,
ensuring its accuracy and readiness for fabrication. Document the design decisions,
dimensions, routing details, and any specific considerations. This documentation
serves as a reference for future analysis, modifications, and understanding of the
layout design.

18
Fig 3.2

19
3.3 System Design using various Structured analysis and design tools such
as: DFD’s, Data Dictionary, Structured charts, Flowcharts.

Start]

1. Define the specifications and requirements for the semiconductor device layout
2. Create a schematic diagram of the device
3. Design the physical layout of the device using computer-aided design (CAD) software
4. Perform design rule checks (DRC) to ensure the layout meets manufacturing
requirements
5. Perform layout-versus-schematic (LVS) checks to ensure the layout matches the
schematic
6. Simulate the device using computer simulation software to verify its performance
7. Generate a mask set for the device layout
8. Fabricate the device using photolithography and other semiconductor manufacturing
processes
9. Test the device to ensure it meets the specifications and requirement.

20
3.4 User Interface Design
Cadence Virtuoso is a popular software tool used for designing semiconductor layouts. It is
widely recognized for its advanced capabilities and user-friendly interface, making it a
preferred choice for engineers and designers. Virtuoso offers a wide range of features,
including a customizable layout editor, advanced routing tools, and a powerful design rule
checker. With Virtuoso, users can create complex semiconductor layouts with ease and
precision. The software also allows for easy collaboration and sharing of designs, making it
an ideal tool for team projects. Overall, Virtuoso has become a standard in the semiconductor
industry, and its use is essential for creating high-quality layouts that meet the strict
requirements of the industry.

Fig

The Cadence Layout window will have a professional and functional interface that is
optimized for designing semiconductor layouts. The main screen will display a blank canvas
with a toolbar on the left-hand side and a properties panel on the right-hand side.

The toolbar will include the following tools:

• Selection tool: This tool will allow users to select and move objects on the canvas.
• Rectangle tool: This tool will allow users to draw rectangles and squares on the
canvas.
• Circle tool: This tool will allow users to draw circles and ovals on the canvas.
• Line tool: This tool will allow users to draw straight lines on the canvas.
• Text tool: This tool will allow users to add text to the canvas.

21
 • Image tool: This tool will allow users to add images to the canvas.
• Layer tool: This tool will allow users to select which layer they want to work on.

The properties panel will display the properties of the selected object, including its size,
position, and layer. Users will be able to adjust these properties by using sliders and
dropdown menus.

The application will also include a menu bar at the top of the screen, with options for creating
a new layout, opening an existing layout, saving a layout, and exporting a layout as an image
or PDF. There will also be options for performing design rule checks (DRC) and layout-
versus-schematic (LVS) checks.

Overall, the user interface design will be optimized for designing semiconductor layouts
efficiently and accurately. The focus will be on providing users with the tools they need to
create high-quality layouts quickly and easily.

Important key points of using tis interface are:

➢ Importance of user-centered design: User-centered design is an approach to interface

design that focuses on the needs and preferences of users. By prioritizing user needs,
designers can create interfaces that are intuitive and easy to use. This can lead to
increased user satisfaction and engagement, as well as improved business outcomes.

➢ Design principles and guidelines: There are many design principles and guidelines
that can inform the design of user interfaces. These include principles such as
simplicity, consistency, and feedback, as well as guidelines for typography, color, and
layout. By following these principles and guidelines, designers can create interfaces
that are visually appealing and easy to navigate.

➢ Accessibility considerations: It's important to design interfaces that are accessible to

all users, including those with disabilities. This can involve considerations such as
providing alternative text for images, using high-contrast colors, and ensuring that the
interface can be navigated using a keyboard. By designing for accessibility, designers
can create interfaces that are inclusive and welcoming to all users.

➢ Iterative design process: User interface design is an iterative process, which means
that designers should be prepared to make changes based on user feedback and testing
results. By testing the interface with users and making improvements based on their
feedback, designers can create interfaces that are optimized for user needs and
preferences.

➢ Role of visual design: Visual design is an important component of user interface

design, as it can greatly impact the user experience. By choosing colors, fonts, and
other visual elements carefully, designers can create interfaces that are visually
appealing and engaging. However, it's important to balance visual design with
usability, ensuring that the interface is easy to use and navigate.

22
 Chapter 4: Implementation, Testing and Maintenance

4.1 Introduction to Languages, IDE’s, Tools and Technologies used for

Implementation.
The two languages upon which I have worked mostly during my internship are:
• Shell Scripting
• Python

Shell Scripting
Shell scripting is a programming language used to automate tasks on a Unix or Linux
operating system. It is a powerful tool that allows users to write scripts that can execute a
series of commands and perform complex tasks. Shell scripts are written in a shell language,
which is a command-line interface that allows users to interact with the operating system.

Shell scripting is useful for automating repetitive tasks, such as file management, system
administration, and data processing. It can also be used to create custom utilities, perform
backups, and monitor system performance. Shell scripts can be executed manually or
scheduled to run automatically at specific times or events.

The most common shell language is Bash (Bourne-Again SHell), which is the default shell
for most Linux distributions. Other popular shell languages include Korn shell (ksh), C shell
(csh), and Z shell (zsh). Each shell language has its own syntax and features, but they all
share common commands and functions.

I have mostly used BASH.

Fig

23
Shell scripts can be created using a text editor, such as vi or nano, and saved with a .sh
extension. The script can then be made executable using the chmod command, which allows
the user to run the script. The script can be executed by typing its name in the terminal,
preceded by the ./ command.

The improvements offered by Bash include.

▪Command line editing
▪Unlimited size command history
▪Job Control
▪Shell Functions and Aliases

Python
Python is a high-level, interpreted programming language that is widely used for developing
a wide range of applications. It was first released in 1991 by Guido van Rossum and has since
become one of the most popular programming languages in the world. Python is known for
its simplicity, readability, and versatility, making it a popular choice for beginners and
experienced programmers alike.
One of the key features of Python is its easy-to-read syntax. Python code is written in a clear
and concise manner, making it easy to understand and maintain. The language uses
indentation instead of braces or brackets to define blocks of code, which makes it easier to
read and write.

Tkinter

Tkinter is a standard Python library for creating graphical user interfaces (GUIs). It provides
a set of tools and widgets for building desktop applications that run on Windows, macOS,
and Linux. Tkinter is included with most Python installations, so there is no need to install
any additional software to use it.

Tkinter is based on the Tk GUI toolkit, which was originally developed for the Tcl
programming language. The Tk toolkit provides a set of graphical components, such as
buttons, labels, text boxes, and menus, that can be used to build user interfaces. Tkinter
provides a Python interface to these components, allowing developers to create GUIs using
Python code.

24
 Fig

One of the key features of Tkinter is its simplicity. It is easy to learn and use, making it a
popular choice for beginners who are just starting to learn GUI programming. Tkinter also
provides a number of layout managers, which help to arrange the widgets on the screen in a
flexible and responsive way.

Tkinter provides a number of built-in widgets, including buttons, labels, text boxes, check
boxes, radio buttons, and menus. These widgets can be customized with various options, such
as font size, color, and alignment. Tkinter also provides support for event handling, allowing
developers to respond to user input, such as mouse clicks and keyboard presses.

4.2 Coding standards of Language used

As discussed above, I have used 2 languages which are python and shell scripting.

Shell scripting
Coding standards for shell scripts are a set of guidelines and best practices that ensure
consistency, readability, and maintainability of shell scripts. These standards help to reduce
errors, improve code quality, and make it easier for other developers to understand and
modify the code. Here are some common coding standards for shell scripts:

• Use a consistent naming convention for variables, functions, and files. Use all
uppercase letters for global variables and functions, and lowercase letters for local
variables and functions. Use underscores to separate words in variable and function
names.

• Use comments to explain the purpose and behavior of the code. Use clear and concise
comments that explain what the code does, why it does it, and how it does it. Use
comments to document any assumptions, limitations, or dependencies of the code.

25
 • Use indentation and whitespace to improve readability. Use consistent indentation to
show the structure of the code. Use whitespace to separate logical blocks of code and
to make the code easier to read.

• Use error handling and exit codes to handle errors and failures. Use error handling to
catch and handle errors in the code. Use exit codes to indicate the success or failure of
the script, with 0 indicating success and non-zero values indicating failure.

• Use functions to group related code and to promote code reuse. Use functions to
encapsulate related code into reusable blocks. Use functions to simplify complex code
and to improve readability.

• Use quotes to handle spaces and special characters in filenames and variables. Use
quotes to enclose filenames and variables that contain spaces or special characters.
This helps to prevent errors and unexpected behavior when the code is executed.

• Use portable syntax to ensure compatibility across different shells and platforms. Use
syntax that is compatible with different shells and platforms, such as POSIX syntax.
Avoid using shell-specific syntax or features that may not be available on all
platforms.

Python
• Indentation: Use 4 spaces for indentation to represent a block of code. Avoid using
tabs or a different number of spaces for indentation.

• Line Length: Limit lines to a maximum of 79 characters. For lines that would exceed
this limit, you can break them into multiple lines using parentheses or the backslash ()
character.
• Constants: Use uppercase letters with words separated by underscores.
• Classes: Use capitalized words with no underscores (CamelCase).
• Imports: Import statements should be on separate lines at the top of the file. Group
imports by category and order them alphabetically.
• Whitespace: Use a single space around operators and after commas. Use blank lines to
separate logical sections of code for improved readability.
• Comments: Use comments to explain complex code or provide additional context.
Place comments on a separate line, or use them sparingly at the end of a line if they
provide necessary clarification.
• Function and Method Definitions: Use a single space after the colon in function and
method definitions. Place any default argument values after a space.
• Error and Exception Handling: Use specific exception types rather than catching
generic exceptions. Handle exceptions appropriately and avoid using bare except
clauses.

26
4.3Testing
Sample code for shell scripting:

Fig

Fig

Design and Implementation of a Python Tkinter Interface

In this project, a user-friendly Graphical User Interface (GUI) was developed using the
Python Tkinter library. The interface includes features such as radio buttons and a searchable
dropdown menu for selecting the desired technology.
The design methodology for creating the Tkinter interface involved several steps, including
UI design, event handling, and data retrieval. The interface was designed to be intuitive and
easy to navigate, ensuring a seamless user experience.

27
Implementing the above code I got the following result

28
 Fig

This is the required GUI containing various buttons which when clicked upon opens 2
options. Upon clicking the options, the required action is performed.

29
Fig
‘

30
 CHAPTER 5
RESULTS AND DISCUSSIONS

5.1 Back Ends Representation

VNC, which stands for Virtual Network Computing, is a technology that allows remote
access and control of a computer or server over a network. It enables users to view and
interact with a desktop environment on a remote machine as if they were physically present at
that location.

The concept of VNC was developed in the late 1990s at the Olivetti & Oracle Research Lab
in Cambridge, United Kingdom. The original implementation, known as VNC, was created
by Tristan Richardson and Andy Harter. It was later released as open-source software, and
several variations and implementations have been developed since then.

VNC operates using a client-server model. The server component, also known as the VNC
server, runs on the machine that is being remotely accessed. It captures the graphical output
of the desktop environment and encodes it into a series of image frames that are transmitted
over the network to the VNC client. The client component is installed on the local machine
from which the remote access is initiated. It receives the image frames from the server,
decodes them, and displays the remote desktop environment to the user.

The communication between the VNC server and client is typically carried out using the
Remote Frame Buffer (RFB) protocol. This protocol defines the format and encoding of the
image frames, as well as the various interactions and events that can be transmitted between
the client and server.

VNC offers several benefits and use cases. It allows users to access their computers or servers
remotely, which can be particularly useful for remote troubleshooting, software
demonstrations, or accessing resources from a different location. It also enables collaboration
and remote work by allowing multiple users to view and interact with the same desktop
environment simultaneously.

In addition to the standard VNC protocol, various implementations and extensions have been
developed to enhance VNC functionality. Some implementations provide additional security
features, such as encryption of the transmitted data to protect against eavesdropping. Others
offer features like file transfer capabilities or the ability to remotely access and control mobile
devices.

Overall, VNC is a versatile and widely used technology that facilitates remote access and
control of computers and servers. Its simplicity, cross-platform compatibility, and open-
source nature have contributed to its popularity and adoption in various industries and
applications.

31
5.2 Snapshots of Database

Fig

Fig

32
 CHAPTER 6
CONCLUSION AND FUTURE SCOPE

Conclusion
I learned a lot from this internship not only gained industry experience but also learned a lot
about team work, arranging meetings, sharing knowledge (as sharing is caring), disaster
management on large scale as quickly as possible. Also gained about whole hierarchy of an
enterprise, how to manage your workload and prioritizing work. Literally I learned in this 1
year, about developing myself, listening to others, taking opinion of everyone in team if
taking an action regarding team. I developed my speaking skills along with my confidence
and representing myself to others.

From project I learnt new technologies like Shell Scripting, Python, etc., learned how to
divide work in team of your project, delivering project on time.

I was lucky to get internship in ST Microelectronics as my 1st carrier step to gain

corporation life knowledge because this 1 year has changed me a lot.

Some of the reasons I would put forth are:-

● Great Technical Experience and Knowledge: I had a sound exposure to new technologies,
and excellent procedures and standards in STMicroelectronics.

● Responsibility and Faith in work: STMicroelectronics treats its trainees in the same caliber
as its skilled employees. In fact, I working on the actual projects that were run by the
company, and personally, I had a major role to play in the shaping of new project I was
assigned to.

● Training Personnel and their Enthusiasm towards trainees: team members other employees
are always ready to help trainees out with their work and readily share their experience or
knowledge when necessary.

● Providing an overall learning: STMicroelectronics understands that it is not only technical

expertise which will make a successful IT professional and therefore they are continuously
working to ensure that trainees get an all-round learning and skill development.

At last, I would also like to thank DAV Institute of Engineering and Technology for giving
me the chance to work in such a reputed company like STMicroelectronics. A heart-felt
thanks to STMicroelectronics for believing in us and giving us the training in a best possible
way.

33
Future Scope
The future scope for semiconductor layout report files encompasses several key areas of
advancement and innovation. These developments are expected to enhance the efficiency,
accuracy, and scalability of semiconductor layout design processes. Here are some potential
future directions:

1. Automation and AI-driven Layout Design: The application of artificial intelligence (AI)
and machine learning (ML) techniques is expected to revolutionize the semiconductor layout
design process. AI algorithms can analyze vast amounts of design data, learn from patterns,
and generate optimized layout solutions. This automation can significantly speed up the
design process while ensuring better performance and reducing human error.

2. Advanced Design Rule Optimization: Design rules dictate the constraints and guidelines
for creating semiconductor layouts. Future advancements will focus on optimizing design
rules to accommodate complex circuitry and shrinking process technologies. This includes
refining layout constraints, introducing new design rule methodologies, and exploring novel
approaches to layout optimization.

3. Multi-Objective Optimization: Semiconductor layout design often involves multiple

conflicting objectives, such as performance, power consumption, and area utilization. Future
developments will focus on multi-objective optimization techniques that consider these
competing factors simultaneously. Evolutionary algorithms and other optimization strategies
can help designers explore the trade-offs and find optimal solutions that balance various
design goals.

4. Layout-aware Design Automation: Traditional design automation tools focus primarily on

individual circuit components and do not always consider the overall impact on the layout.
Future advancements will integrate layout-awareness into the design automation flow. This
will enable better communication and collaboration between circuit designers and layout
engineers, resulting in more efficient and optimized layouts.

5. Advanced Manufacturing and Packaging Technologies: As semiconductor technologies

continue to evolve, new manufacturing and packaging technologies will emerge. These
advancements will impact the layout design process by introducing new constraints and
considerations. Future layout design tools will need to adapt to support emerging
technologies such as 3D integration, heterogeneous integration, and advanced packaging
techniques.

6. Security and Trustworthiness: With the growing concern for hardware security, future
layout design processes will prioritize security and trustworthiness. Layout-level techniques,
such as layout-level obfuscation and hardware Trojan detection, will be integrated into the
design flow to ensure the integrity and reliability of semiconductor layouts.

34
7. Collaboration and Integration: The future scope for semiconductor layout report files
involves enhanced collaboration and integration across different stages of the design flow.
Seamless integration between layout design tools, simulation tools, and verification tools will
enable a more streamlined and efficient design process. This integration will facilitate
concurrent design, early-stage design exploration, and improved design-for-manufacturing
(DFM) practices.

Overall, the future scope for semiconductor layout report files is focused on leveraging
advanced technologies such as AI, optimization techniques, and improved collaboration to
enhance the efficiency, accuracy, and reliability of layout design processes. These
advancements will play a crucial role in meeting the demands of emerging semiconductor
technologies and driving innovation in the semiconductor industry.

35
 REFERENCES

[1] Jidnayesh Behre,June 8th, 2018 | BMC Remedy, ISTM

http://www.vyomlabs.com/bmc-helix-the-future-of-service-management/

[2] Colin Simon, HP UCMDB

http://ucmbd.files.wordpress.com/2016/04/ucmbd_browser_installconf_4-04_1.pdf

[3] IBM Support

http://www.ibm.com/docs/en/SSGSPN_9.10/com.ibm.tivoli.itwas.doc_9.1/awsrgmst.
pdf

36