ATRIA INSTITUTE OF TECHNOLOGY

Department of Electronics and Communication Engineering

LAB MANUAL
ODD SEMESTER 2017-2018
SUBJECT: ANALOG ELECTRONICS SEMESTER: THIRD
 Analog Electronics Lab

Analog Electronics Lab Manual

Sub code: 15ECL37 IA Marks: 20
Subject: Analog Electronics lab Exam Hours: 3
Hours/Week: 01Hr Tutorial(Instructions) +02 Hours Lab Exam Marks: 80
Syllabus

List of experiments as per the syllabus.

1. Design and set up the following rectifiers with and without filters and to determine ripple
factor and rectifier efficiency:
(a) Full Wave Rectifier (b) Bridge Rectifier
2. Conduct experiment to test diode clipping (single/double ended) and clamping circuits
(positive/negative).
3. Conduct an experiment on Series Voltage Regulator using Zener diode and power transistor to
determine line and load regulation characteristics.
4. Realize BJT Darlington Emitter follower with and without bootstrapping and determine the
gain, input and output impedances.
5. Design and set up the BJT common emitter amplifier using voltage divider bias with and
without feedback and determine the gainbandwidth product from its frequency response.
6. Plot the transfer and drain characteristics of a JFET and calculate its drain resistance, mutual
conductance and amplification factor.
7. Design, setup and plot the frequency response of Common Source JFET/MOSFET amplifier
and obtain the bandwidth.
8. Plot the transfer and drain characteristics of n-channel MOSFET and calculate its parameters,
namely; drain resistance, mutual conductance and amplification factor.
9. Set-up and study the working of complementary symmetry class B push pull power amplifier
and calculate the efficiency.
10. Design and set-up the RC-Phase shift Oscillator using FET, and calculate the frequency of
output waveform.
11. Design and set-up the following tuned oscillator circuits using BJT, and determine the
frequency of oscillation.
(a) Hartley Oscillator (b) Colpitts Oscillator
12. Design and set-up the crystal oscillator and determine the frequency of oscillation.

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Cyclewise coverage of the syllabus

Cycle-1

1. Testing of Rectifiers & filters , Determination of ripple factor . regulation & efficiency.
a) Full Wave rectifier without capacitor filter.
b) Full Wave rectifier with capacitor filter.
c) Full Wave Bridge rectifier without capacitor filter.
d) Full Wave Bridge rectifier with capacitor filter.
2. Design and obtain the transfer characteristics of different clipping & clamping circuits

i) Positive peak clipping (shunt and series)

ii) Negative peak clipping (shunt and series)
iii) Double ended clipping
iv) Slicer
v) Positive peak clamping
vi) Negative peak clamping.
3. Realize BJT Darlington Emitter follower with and without bootstrapping and determine the
gain, input and output impedances.
4. Design and set up the BJT common emitter amplifier using voltage divider bias with and
without feedback and determine the gain-bandwidth product from its frequency response.
Cycle-2

5. Set-up and study the working of complementary symmetry class B push pull power amplifier
and calculate the efficiency.
6. Design, setup and plot the frequency response of Common Source JFET/MOSFET amplifier
and obtain the bandwidth.
7. Design and set-up the following tuned oscillator circuits using BJT, and determine the
frequency of oscillation.
(a) Hartley Oscillator (b) Colpitts Oscillator
8. Design and set-up the crystal oscillator and determine the frequency of oscillation.

Cycle-3
9. Plot the transfer and drain characteristics of n-channel MOSFET and calculate its parameters,
namely; drain resistance, mutual conductance and amplification factor..
10. Plot the transfer and drain characteristics of a JFET and calculate its drain resistance, mutual
conductance and amplification factor.
11. Conduct an experiment on Series Voltage Regulator using Zener diode and power transistor
to determine line and load regulation characteristics
12. Design and set-up the RC-Phase shift Oscillator using FET, and calculate the frequency of
output waveform.

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Experiment no – 1

Rectifiers
Aim: To design the following Rectifiers and to determine the ripple factor, % voltage
regulation and % efficiency.
a) Full Wave rectifier without capacitor filter
b) Full Wave rectifier with capacitor filter
c) Full Wave Bridge rectifier without capacitor filter
d) Full Wave Bridge rectifier with capacitor filter
Components:
Sl no. Components required Range Qty
1. Diodes BY127/1N4007 4
2. Resistor (180Ω / 1/2W) 1
3. Capacitor 100µF 1 each
4. CRO 1
5. DRB 1
6. Transformer 230 V/ 6V or 9V or 12V 1

a) FWR without Capacitance filter

Aim: To design and test the circuit of FWR without C filter and to calculate the η and γ.

Circuit Diagram:

Design:
Design a FWR for o/p DC voltage of 10 V and maximum load current of 100mA.
Given Vdc = 10V and IL(max) = 100 mA

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Therefore use 180Ω/2W rating resistor as load.

Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Vary the load (DRB) from no load condition to full load condition.
3. Note down the Vac, Vdc, Iac, Idc values from the multimeters.
4. Note down the transformer secondary voltage using multimeter (Vrms).
5. Observe the rectified waveform on the CRO.
Expected Waveforms:

Tabular column: (without capacitor filter)

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RL Vdc Vac Vm (V) Vrms = γ= Vac/Vdc η= %VR

(kΩ) (V) (V) from V2 dc / V2 rms
CRO

Calculations:

Where, VDCNoload= o/p Voltage with DRB to max value 10 or 30KΩ so that IL≈0

VDCload = o/p voltage with DRB = 0 so that IL = ILmax

Result:

Ripple factor =-----------------------------

Percentage efficiency =----------------------------------

Percentage Regulation = -------------------------------

b) FWR with C filter

Aim : To design and test the circuit of FWR with C filter and to calculate the η and γ

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CircuitDiagram:

Design:

Design a FWR with C filter with the O/P DC voltage of 17 V and load current of 100mA
& ripple factor of < 0.04
For a FWR with C-filter,

Transformer secondary voltage

Therefore, transformer rating 0 – 12V can be used.

Therefore use 2W rating resistor as load.

Ripple factor

Since we are using 230V, 50 Hz AC supply, therefore f = 50 Hz

So, C =100µF
Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Vary the load (DRB) from no load condition to full load condition.

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3. Note down the Vac, Vdc, Iac, Idc values from the multimeters.
4. Note down the transformer secondary voltage using multimeter (Vrms).
5. Observe the rectified waveform on the CRO.
Tabular column: (with C Filter)

RL Vm Vr,pp Vr,rms Vdc Vdc γ= η=

Use Use Theoretical theoretical Practica Vr,rms/ V2 dc / V2 rms
CRO CRO Vr,rms = Vdc = Vm- l Use Vdc
Vr,pp /2 √3 (Vr,pp/2) multime
ter in dc
mode

Result:
Ripple factor =______________.

VIVA QUESTIONS:
1. What is a full wave rectifier?
2. How Diode acts as a rectifier?
3. What is the significance of PIV requirement of Diode in full-wave rectifier?
4. Compare capacitor filter with an inductor filter?
5. Draw the o/p wave form without filter? What is wave form with filter?
6. What is ripple factor? For a good filter whether ripple factor should be high or low? What
happens to the ripple factor if we insert the filter?
7. What is meant by regulation? Why regulation is poor in the case of inductor filter?
8. What is meant by time constant?
9. What happens to the o/p wave form if we increase the capacitor value? What happens if we
increase the capacitor value?
10. What is the theoretical maximum value of ripple factor for a full wave rectifier?
c) Full wave (Bridge) Rectifier without C filter

Aim: To study the wave forms of FW bridge rectifier and calculate the η and γ

Circuit Diagram:

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Design:

Design a Full wave bridge rectifier o/p DC voltage of 10V and maximum load current of
100mA.
Given Vdc = 10V and IL(max) = 100 mA

= 15.7 V

(choose 180Ω std value)

Therefore use 2W rating resistor as load.

Procedure:

1. Connect the circuit as shown in the circuit diagram.

2. Vary the load (DRB) from no load condition to full load condition.
3. Note down the Vac, Vdc, Iac, Idc values from the multimeters.
4. Note down the transformer secondary voltage using multimeter (Vrms
5. Observe the rectified waveform on the CRO.
Expected Waveforms:

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Tabular column: (without C filter)

RL Vdc Vac Vm (V) Vrms = γ= Vac/Vdc η= %VR
(kΩ) (V) (V) from V2 dc / V2 rms
CRO

d) FW Bridge Rectifier with C filter

Aim : To study the wave form of FW bridge rectifier with C and to calculate the η and γ

Circuit Diagram:

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Design:
Design a FWR with C filter o/p DC voltage of 17 V and load current of 100mA & ripple
factor of < 0.04
For a FWR with C-filter,

Transformer secondary voltage

Therefore, transformer rating 0 – 12V can be used.

Therefore use 2W rating resistor as load.

Ripple factor

Since we are using 230V, 50 Hz AC supply, therefore f = 50 Hz

So, C =100µF

Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Vary the load (DRB) from no load condition to full load condition.

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3. Note down the Vac, Vdc, Iac, Idc values from the multimeters.
4. Note down the transformer secondary voltage using multimeter (Vrms
5. Observe the rectified waveform on the CRO.
Tabular Column:
RL Vm Vr,pp Vr,rms Vdc Vdc γ= η=
Use Use Theoretical theoretical Practica Vr,rms/ V2 dc / V2 rms
CRO CRO Vr,rms = Vdc = Vm- l Use Vdc
Vr,pp /2 √3 (Vr,pp/2) multime
ter in dc
mode

Result:
Ripple factor =______________.

VIVA QUESTIONS:
1. What are the advantages of Bridge Rectifier over the center tapped Rectifier?
2. What does Regulation indicate?
3. What is the Theoretical maximum value of Ripple factor of a Full-wave Rectifier?
4. What is the PIV requirement of a Diode in a Bridge Rectifier?
5. Explain the operation of Bridge Rectifier?

Experiment no – 2
Aim: Design and obtain the transfer characteristics of different peak clipping circuits.
1. Positive peak clipping (shunt and series)
2. Negative peak clipping (shunt and series)
3. Double ended clipping
4. Slicer

Components:

Sl no. Components required Range Qty

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1. Diodes 1N 4007 2
2. Resistors 10KΩ 1
3. CRO 1
4. Power supply (VRPS) 0-30 V 2
5. Signal Generator 1
6. Capacitor 1uF 1
1

I) Peak clipping circuits

a) Diode shunt clipping above VRef (reference voltage) / Positive peak clipping

Circuit Diagram:

Design : Let the output be clipped to say +2V. Vo(max) = +2V

from circuit diagram,

Vo(max) = VD + VREF
Where VD is the diode drop  0.7V

 VREF = Vo(max) –VD

= 2.0 – 0.7 =1.3V
Choose R = √( Rf * Rr )
= 10KΩ,
where Rf ( diode forward resistance) =10Ω.
Choose Rr ( diode reverse resistance) = 10MΩ

Procedure:

 Connections are made as shown in the circuit diagram.

 The input sinusoidal Signal (Vi) is set to 6V (p-p) of 1KHz frequency.
 Observe the output Waveform (VO) on the CRO and verify it with the expected
waveforms.

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 To find the transfer characteristics of the waveforms, apply V i and Vo to the X and Y
channel of the CRO and Use XY mode for observation.

b) Diode shunt clipping below VRef (reference voltage) / Negative peak clipping

Circuit Diagram:

Design:
Procedure:
Let the output be clipped at -2V.  VO = -2V
from circuit diagram,
 Connections are made as shown in the circuit diagram.
VO = -V D + VREF
The input sinusoidal Signal (Vi ) from the signal generator is set to 10V(p-p) of 1KHz
VD is the diode drop  0.7V
Where frequency.
 Observe the output Waveform (Vo) on the CRO and verify it with the expected
 VREFwaveforms.
= VO +VD
 To= find
- 2.0the transfer
+ 0.7 characteristics
= - 1.3 V of the waveforms, apply Vi and Vo to the X and Y
channel of the CRO. Use X-Y mode for observation.
Choose Rcharacteristics
Transfer = √( Rf * Rr ) = 10KΩ,
where Rf is the diode forward resistance = 10Ω.
Choose Rr (reverse resistance of the diode) = 10MΩ

c) Diode series clipping above VRef (reference voltage) / Positive peak clipping
Circuit Diagram:

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Design:
Let the output be clipped at +2V.
VO = VREF
= +2V
Choose R = √( Rf * Rr ) = 10KΩ,
where Rf is the diode forward resistance = 10Ω.
Choose Rr (reverse resistance of the diode) = 10MΩ
Procedure:
 Connections are made as shown in the circuit diagram.
 The input sinusoidal Signal (Vi) from the signal generator is set to 6V (p-p) of 1KHz
frequency.
Observe the output Waveform (Vo) on the CRO and verify it with the expected
waveforms.
 To find the transfer characteristics of the waveforms, apply V i and Vo to the X and Y
channel of the CRO. Use XY mode for observation.

d) Diode series clipping below VRef (reference voltage) / Negative peak clipping

Circuit Diagram :

Design:

Let the output be clipped at -2V.

VO = VREF = -2V

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Choose R = √( Rf * Rr ) = 10KΩ,
where Rf is the diode forward resistance = 10Ω.
Choose Rr (reverse resistance of the diode) = 10MΩ
Procedure :
 Connections are made as shown in the circuit diagram.
 The input sinusoidal Signal (Vi) from the signal generator is set to 6V(p-p) of 1KHz
frequency.
 Observe the output Waveform(Vo) on the CRO and verify it with the expected
waveforms.
 To find the transfer characteristics of the waveforms, apply V i and Vo to the X and Y
channel of the CRO. Use X-Y mode for observation.

e) Clipping at two independent levels (Slicer)

Circuit Diagram:

Design :

To obtain a slice of input voltage between 2V and 4V levels at its output

Let VREF1>VREF2 .
To find VREF1:

Vo = VREF1 + VD
Where VD is the diode drop  0.7V

Since Vo = 4V,
 VREF1 = Vo - VD
= 4.0 – 0.7
= 3.3 V

To find VREF2:

Vo = VREF2 – VD
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Where VD is the diode drop  0.7V

Since Vo = 2V,
 VREF2 = Vo + VD
= 2.0 + 0.7
=2.7 V

Choose R = sqrt( Rf * Rr ) = 10KΩ,

where Rf is the diode forward resistance = 10Ω.
Choose Rr (reverse resistance of the diode) = 10MΩ

Procedure:

 Connections are made as shown in the circuit diagram.

 The input sinusoidal Signal (Vi) is set to 10V(p-p) of 1KHz frequency.
 Observe the output Waveform (Vo) on the CRO and verify it with the expected
waveforms.
 To find the transfer characteristics of the waveforms, apply Vi and Vo to the X and Y
channel of the CRO. Use X-Y mode for observation.

B) Double Ended Clipper with symmetrical voltage levels:

Circuit Diagram:

Design:
Let the output be clipped at +4V and -4V.
 Vo(max) = +4 V and Vo(min) = -4 V
To find VREF1:
Vo (max) = VREF1 + VD
Where VD is the diode drop  0.7 V
 VREF1 = Vo(max) –VD

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= 3.3 V
To find VREF2:
Vo (min) = VREF2 - VD
Where VD is the diode drop  0.7 V
 VREF2 = Vo(min) + VD
= - 3.3 V
Choose R = √( Rf * Rr ) = 10KΩ,
Where Rf is the diode forward resistance = 10Ω.
Choose Rr (reverse resistance of the diode) = 10MΩ
Procedure:

 Connections are made as shown in the circuit diagram.

 The input sinusoidal Signal (Vi ) from the signal generator is set to 10V(p-p) of 1KHz
frequency.
 Observe the output Waveform (Vo) on the CRO and verify it with the expected
waveforms.
 To find the transfer characteristics of the waveforms, apply Vi and Vo to the X and Y
channel of the CRO. Use X-Y mode for observation.

Experiment no 2-b
Diode Clamping Circuits

Aim : Design and testing of clamping circuits

a) Positive peak clamping
b) negative peak clamping.

Components :

Sl no. Components required Range Qty

1. Diodes 1N 4007 1
2. Resistors 10KΩ 1
3. Capacitor 1µF 1
4. CRO 1
5. Power supply (VRPS) 0-30 V 1
6. Signal Generator 1
a) Positive Peak Clamper (Negative clamper)
Circuit Diagram:

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Expected waveform:

Design :

To design a clamping circuit to clamp the positive peak at 3V. The input waveform has a
frequency of 1KHz sine wave or square wave.
VO = +3V
Design of VREF :
From circuit diagram,
VO = VD + VREF
Where VD is the diode drop  0.7V
 VREF = Vo –VD
= 3.0 – 0.7
= 2.3 V
Design of C:
For a given frequency of 1KHz, T=1msec
Choose RC >> T (so that tilt in the waveform is negligible)

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Let RC = 10T
ie. RC = 10 * 1msec
C = 10ms / 10K
= 1F

Procedure:
 Connections are made as shown in the circuit diagram.
 The input square Signal (Vi) from the signal generator is set to 8V(p-p) of 1KHz
frequency (peak amplitude of input must be greater than the clamping level).
 Observe the output Waveform (VO) on the CRO and verify it with the expected
waveforms.

*** note: input voltage level is independent of the clamping level.

b) Negative Peak Clamper (positive clamper)

Circuit Diagram:

Expected waveform:

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Design:

To design a clamping circuit to clamp the negative peak at -3V.

Design of VREF :
VO = -3V
From circuit diagram,
VO = VREF – VD
Where VD is the diode drop  0.7V
 VREF = Vo + VD
= -3.0 + 0.7
= -2.3 V

Design of C:
For a given frequency of 1KHz, T=1msec
Choose RC >> T (so that tilt in the waveform is negligible)
Let RC = 10T
ie. RC = 10 * 1msec
C = 10ms / 10K = 1F

Procedure:
 Connections are made as shown in the circuit diagram.
 The input square Signal (Vi) from the signal generator is set to 8V(p-p) of 1KHz
frequency (peak amplitude of input must be greater than the clamping level).

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 Observe that the negative peak of the output Waveform (VO) is clamped to 0V on the
CRO when VREF = 0 and verify it with the expected waveforms.
Result:

Experiment no – 3
Common Emitter BJT amplifier
Aim : To design and set up the common emitter amplifier under voltage divider bias with and
without feedback and determine the gainbandwidth product from its frequency response.

Components required:

Sl Components required Range Qty

no.
1. Transistor(BJT) BC107 1
2. Resistors(for BJT) 18KΩ, 82KΩ, 1KΩ, 3.9KΩ 1 each
3. Capacitors 1µF (3 nos) 1 each
4. CRO 1
5. Power supply(VRPS) 0-30 V 1each
6. ASG 1
7. DRB 1

a) To find gain and frequency response of CE amplifier without feedback using BJT.

Circuit Diagram:

Design :
Design RC coupled amplifier for VCC = 10V, hfe = 100, IC = 1mA, VCE = 5 V.

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For a voltage divider bias,

( Choose 1 KΩ )

This can also be synthesized as a series of 470Ω and 1K pot.

In a voltage divider bias,

To find CE and Cc:

Coupling Capacitor Cc =

where

Procedure :

 Connections are made as shown in the circuit diagram and set Vcc =10V
 Measure the dc voltage at VB , collector VC ,emitter VE w.r.t ground.. Determine VCE &
IC. Operating point (Q) = ( VCE , IC ) = ( 5V ,1mA )
 For the circuit connected apply the sinusoidal wave of peak to peak amplitude 20mV

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from the signal generator.

 Vary the frequency of the input signal( from 100Hz to 1MHz) in suitable steps and
Measure the output of the amplifier at each step using CRO ( input Vi must remain
constant throughout the frequency range) and Record the results in tabular column.
Calculate the voltage gain.
 Plot the graph of frequency vs voltage gain in dB on a semilog graph sheet.
 Calculate the bandwidth = upper cutoff (f2) – lower cutoff (f1)

Tabular Column :
Freq (Hz) Vo (V) Vo/Vi Av(dB)= 20 log(Vo/Vi)

Expected Graph:

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b) To find gain and frequency response of CE amplifier with feedback using BJT

Note: Repeat the same procedure followed for the CE amplifier without feedback using BJT,
and determine the gain bandwidth product for CE amplifier with feedback.

Tabular Column:

Freq (Hz) Vo (V) Vo/Vi Av(dB)= 20 log(Vo/Vi)

Result :

Sl.No Details Without With Feedback

Feedback

1 Operating Point

2 Gain in db

3 Bandwidth

4 Gain – Bandwidth product

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Experiment no:4

Darlington emitter follower amplifier with and without bootstrapping

Aim: Wiring of a BJT Darlington emitter follower amplifier and determine the
a) gain, b) Frequency response,
c) input impedance d) output impedances.

Components:

Sl no. Components required Range Qty

1. Transistors SL 100 2
2. Resistors 1MΩ, 1.5MΩ, 1.2KΩ, 1KΩ 1 each
3. Capacitors 0.01µF 3
4. CRO 1
5. Power supply (VRPS) 0-30 V 1
6. ASG 1
7. DRB 1

a) To find gain of Darlington emitter follower amplifier.

Circuit Diagram:

Design : Design a Darlington emitter follower amplifier for Ic = 5mA , Vcc = 12V and
β=100 (for both SL100 & BC107 transistors)

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E
To find R

To find R1

To find R2

To find RC

Choose 0.01µF for coupling capacitors ( C1 , C2 )

Procedure:

 Connections are made as shown in the circuit diagram and set Vcc =12V
 Measure the dc voltage at collector VC2 and emitter VE2 w.r.t ground. Determine VCE2
and IC2
Operating point (Q) = ( VCE , IC ) = ( 6V ,5mA )
 For the circuit connected apply the sinusoidal wave of peak to peak amplitude 1V from
the signal generator and measure the o/p voltage and check for the unity gain
 Find gain I/P impedance and O/P impedance.

b) To find Input impedance ( Zi) :

Circuit Diagram:

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Procedure :

 Connect the decade resistance box(DRB) in series with the input(Vi) terminal.
 Let the initial resistance of the DRB be minimum(zero) and frequency of the input be
1KHz and its amplitude at a value less than the maximum signal handling capacity, note
down Vo.
 Go on Increasing the DRB resistance, till the output becomes half .i.e. Vo/2.
 Note down this value of DRB resistance. This gives the value of input impedance Zi.
c) To find output impedance (Zo):
Circuit diagram:

Procedure:
 Connect the decade resistance box (DRB) in parallel with the output (Vo) terminal.
 Let the initial resistance of the DRB be maximum and frequency of the input be 1KHz
and its amplitude at a value less than the maximum signal handling capacity, note down
value of Vo.
 Go on decreasing the DRB resistance, till the output becomes half .i.e. Vo/2.
 Note down the value of DRB resistance. This gives the value of output impedance Zo.

Darlington Emitter Follower with bootstrapping:

Circuit Diagram:

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Note:
 Input impedance is greatly increased by bootstrapping the Darlington amplifier.
 C3 is the bootstrapping capacitor

b) To find Input impedance ( Zi) :

Circuit Diagram:

Procedure :

 Connect the decade resistance box(DRB) in series with the input(Vi) terminal.
 Let the initial resistance of the DRB be minimum(zero) and frequency of the input be
1KHz and its amplitude at a value less than the maximum signal handling capacity, note
down Vo.
 Go on Increasing the DRB resistance, till the output becomes half .i.e. Vo/2.
 Note down this value of DRB resistance. This gives the value of input impedance Zi.

c) To find output impedance (Zo):

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Circuit diagram:

Procedure:

 Connect the decade resistance box (DRB) in parallel with the output (Vo) terminal.
 Let the initial resistance of the DRB be maximum and frequency of the input be 1KHz
and its amplitude at a value less than the maximum signal handling capacity, note down
value of Vo.
 Go on decreasing the DRB resistance, till the output becomes half .i.e. Vo/2.
 Note down the value of DRB resistance. This gives the value of output impedance Zo.

Result:

Parameter With bootstrapping Without bootstrapping

Q point

Gain

Input Impedance

Output Impedance

Experiment No:5
Complementary symmetry Class B Push Pull Amplifier

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Aim: To design and test a transformer less complementary Class B push pull amplifier and to
determine the conversion efficiency.

Components Required:

Sl. Components Required Range Qty.

No.
1. Power Supply (0-30)V 2
2. CRO 1
3. Function Generator 1
4. Resistors 470 Ω 2
5. DRB 1
6. Transistors SL-100, SK-100 1 each

Circuit Diagram:

Procedure:
 Connect the circuit as per the circuit diagram.
 Apply a sinusoidal signal of frequency say 1kHz and Vary the amplitude till max
undistorted output is obtained and observe the cross over distortions. Note down the
peak to peak amplitude of the output waveform and DC collector current Ic for a
particular value of load resistor RL & record the readings as shown in the tabular

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column
 Find conversion efficiency using formula.
Tabular Column:
RL (ohms) V0(p-p) (V) η%

Calculation:

Expected waveform:

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Result:
Conversion Efficiency:
Theoritical: 78.5% Practical: _________.
Experiment No: 6
Common Source FET Amplifier
Aim: To design and test the gain bandwidth product of CS JFET amplifier
Circuit Diagram:

Design:
Design of the RC coupled amplifier using FET self biasing Circuit for given VDD=15V,
IDSS = 8mA, VD = -4V and VGS = - 2V
Drain to Source voltage in an FET can be approximated to half of the DC supply voltage.
VDS = VDD

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2
= 7.5 V
ID = IDSS (1-VGS/VD) 2
= 2 mA
Applying KVL to the output Loop,
VDD – ID(RD+RS) – VDS = 0
RD+RS = VDD -VDS
ID
= 3.75 K
Choosing standard value of RS = 1 K, we get RD = 2.7K.
Since, theoritically, the input impedance of an FET is very high
Therefore , practically we assume Rg = 2.2M 

To find CS and Cc:

XCS = RS
10
For f = 100 Hz, CS = 15 uF (choose 10 uF)
Cc = CS
10
Therefore, Cc = 0.1uF

Procedure :

 Connections are made as shown in the circuit diagram and set VDD =10V
 Measure the dc voltage between source VS, and VD w.r.t ground.. Determine VDS and
ID. Operating point (Q) = ( VDS , ID ) = ( 5V ,1mA )
 For the circuit connected apply the sinusoidal wave of peak to peak amplitude 1V from
the signal generator
 Vary the frequency of the input signal ( from 100Hz to 1MHz) in suitable steps and
Measure the output of the amplifier at each step using CRO ( input Vi must remain
constant throughout the frequency range) and Record the results in tabular column.
Calculate the voltage gain.

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 Plot the graph of frequency vs voltage gain in dB on a semilog graph sheet.

 Calculate the bandwidth = upper cutoff (f2) – lower cutoff (f1)

Tabular Column :

Freq (Hz) Vo (V) Vo/Vi Av(dB)= 20 log(Vo/Vi)

Expected Graph:

Experiment No:7

Hartley’s and Colpitt’s Oscillator using BJT

AIM: ToTest the performance of BJT as Hartley Oscillator for a given frequency (fo).

COMPONENTS:

Sl. Components Required Range Qty.

No.

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1. Power Supply (0-30)V 1

2. CRO 1
3. Resistors 1 each
4. DCB 1
5. DIB 1
6. Transistors (BJT) SL100 1
7. Potentiometer

Hartley Oscillator.

CIRCUIT DIAGRAM:

Design:

a) Design of Biasing circuit:

Design RC coupled amplifier for VCC = 10V, hfe = 100, IC = 1mA, VCE = 5 V.

For a voltage divider bias,

( Choose 1 KΩ )

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This can also be synthesized as a series of 470Ω and 1K pot.

In a voltage divider bias,

To find CE and Cc:

Coupling Capacitor Cc =

where

B) Tank Circuit Design:

Tank Resonant frequency is given by: fo = 1 .

2
Where Leq = L1+ L2
For fo = 160KHz and C = 330 pF
Leq = 1 .
42fo2C

Leq =

Leq = 3mH, (choose L1 = 1mH, L2 = 2mH)

Note: L2/ L1>=1 (choose L2 greater than L1)

PROCEDURE:

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 Make the connections as shown in the circuit diagram.

 The output waveform is displayed on the CRO the potentiometer (1K
pot) is adjusted
to get a sine wave output.
 The frequency of oscillation is measured and compared with the theoretical value.

WAVEFORM:

RESULT:

Theoretical frequency Practical frequency

Colpitt’s Oscillator.

CIRCUIT DIAGRAM:

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Design:

a) Design of Biasing circuit:

Design RC coupled amplifier for VCC = 10V, hfe = 100, IC = 1mA, VCE = 5 V.

For a voltage divider bias,

( Choose 1 KΩ )

This can also be synthesized as a series of 470Ω and 1K pot.

In a voltage divider bias,

To find CE and Cc:

Coupling Capacitor Cc =

where
b) Tank Circuit Design:

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Tank Resonant frequency is given by fo =

Where
For fo = 100KHz , C1 = 1000 pf and C2 = 2200 pf
Ceq = 1000 * 2200 * 10-24
3200 * 10-12
= 687.5pf
L = 1/42(fo2) Ceq
L = 1 .
4 * (3.14)2 *(100*103)2 *687.5 * 10 -12
L = 3.6 mH.

PROCEDURE:

 Make the connections as shown in the circuit diagram.

 The output waveform is displayed on the CRO; the potentiometer (1K pot) is adjusted
to get a sine wave output.
The frequency of oscillation is measured and compared with the theoretical value.

WAVEFORM:

RESULT:

Theoretical frequency Practical frequency

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Experiment No:8
Crystal Oscillator using BJT

AIM: Testing for the performance of BJT as Crystal Oscillator for a given frequency (fo)

COMPONENTS:

Sl. Components Required Range Qty.

No.
1. Power Supply (0-30)V 1
2. CRO 1
3. Resistors 1 each
4. Crystal 1MHz 1
5. Transistors (BJT) 1
6. Potentiometer SL100 1

Circuit Diagram:

Design:

a) Design of Biasing circuit:

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Consider Vcc = 10V, hfe = 100, Ic = 1mA, Vce = 5 V.

For a voltage divider bias,

( Choose 1 KΩ )

This can also be synthesized as a series of 470Ω and 1K pot.

In a voltage divider bias,

To find CE and Cc:

Coupling Capacitor Cc =

where

PROCEDURE:

 Make the connections as shown in the circuit diagram.

 The output waveform is displayed on the CRO; the potentiometer (1K pot) is adjusted
to get a sine wave output.

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The frequency of oscillation is measured and compared with the theoretical value.

Result:

Theoretical frequency Practical frequency

Experiment No: 9
Characteristics of JFET
Aim: To plot the input and output characteristics of a JFET and calculate its parameters, namely;
drain dynamic resistance, mutual conductance and amplification factor.
Objective:

To study Drain Characteristics and Transfer Characteristics of a Field Effect Transistor (FET).

Components:

S.No. Name Quantity

1 JFET (BFW11/ BFW10) 1(One) No.

2 Resistor (1K ,100K ) 1(One) No. Each

3 Bread board 1(One) No.

Equipment:

S.No. Name Quantity

1 Dual DC Regulated Power supply (0 - 30 V) 1(One) No.

2 Digital Ammeters ( 0 - 200 mA) 1(One) No.

3 Digital Voltmeter (0 - 20V) 2(Two) No.

4 Connecting wires (Single Strand)

Specifications:

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For FET BFW11:

 Gate Source Voltage VGS = -30V

 Forward Gain Current IGF = 10mA
 Maximum Power Dissipation PD = 300mW

Circuit Diagram:

Figure 1.

Pin assignment of FET:

Top View

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Bottom View

Operation:

The circuit diagram for studying drain and transfer characteristics is shown in the figure1.

1. Drain characteristics are obtained between the drain to source voltage (VDS) and drain
current (ID) taking gate to source voltage (VGS) as the constant parameter.
2. Transfer characteristics are obtained between the gate to source voltage (VGS) and drain
current (ID) taking drain to source voltage (VDS) as the constant parameter.

Procedure:

Drain Characteristics:

1. Connect the circuit as shown in the figure1.

2. Keep VGS = 0V by varying VGG.
3. Varying VDD gradually in steps of 1V up to 10V note down drain current ID and drain to
source voltage (VDS).
4. Repeat above procedure for VGS = -1V.

Transfer Characteristics:

1. Connect the circuit as shown in the figure1.

2. Set voltage VDS = 2V/5V (BFW10/ BFW11).
3. Varying VDD in steps of 0.5V until the current ID reduces to minimum value.
4. Varying VGG gradually, note down both drain current ID and gate-source voltage(VGS).

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5. Repeat above procedure (step 3) for VDS = 4V/ 8V (BFW10/ BFW11).

Observations:

Drain Characteristics

VDD (Volts) VGS = 0V VGS = -1V

VDS(Volts) ID(mA) VDS(Volts) ID(mA)

Transfer Characteristics

VGG (Volts) VDS = 2V/5V VDS = 4V/8V

VGS(Volts) ID(mA) VGS(Volts) ID(mA)

Graph:

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1. Plot the drain characteristics by taking VDS on X-axis and ID on Y-axis at a constant VGS.
2. Plot the transfer characteristics by taking VGS on X-axis and taking ID on Y-axis at
constant VDS.

Calculations from Graph:

1. Drain Resistance (rd): It is given by the relation of small change in drain to source
voltage( VDS) to the corresponding change in Drain Current( ID) for a constant gate to
source voltage ( VGS), when the JFET is operating in pinch-off region.

at a constant VGS (from drain characteristics)

2. Trans Conductance (gm): Ratio of small change in drain current( ID) to the
corresponding change in gate to source voltage ( VGS) for a constant VDS.

gm at constant VDS (from transfer characteristics).

The value of gm is expressed in mho’s ( ) or Siemens (s).

3. Amplification factor (µ): It is given by the ratio of small change in drain to source
voltage ( VDS) to the corresponding change in gate to source voltage ( VGS) for a
constant drain current (ID).

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Inference:

1. As the gate to source voltage (VGS) is increased above zero, pinch off voltage is increased
at a smaller value of drain current as compared to that when VGS = 0V.
2. The value of drain to source voltage (VDS) is decreased as compared to that when VGS =
0V.

Precautions:

1. While performing the experiment do not exceed the ratings of the FET. This may lead to
damage of FET.
2. Connect voltmeter and ammeter with correct polarities as shown in the circuit diagram.
3. Do not switch ON the power supply unless the circuit connections are checked as per the
circuit diagram.
4. Properly identify the Source, Drain and Gate terminals of the transistor.

Result:

Drain and Transfer characteristics of a FET are studied.

Outcomes: Students are able to

1. analyze the Drain and transfer characteristics of FET in Common Source configuration.
2. calculate the parameters transconductance (gm), drain resistance (rd) and amplification
factor(µ).

Viva Questions:

1. Why FET is called a Unipolar device?

Ans: FETs are unipolar transistors as they involve single-carrier-type operation.

2. What are the advantages of FET?

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Ans: The main advantage of the FET is its high input resistance, on the order of 100 MΩ or
more. Thus, it is a voltage-controlled device, and shows a high degree of isolation between input
and output. It is a unipolar device, depending only upon majority current flow. It is less noisy.
and is thus found in FM tuners and in low-noise amplifiers for VHF and satellite receivers. It is
relatively immune to radiation. It exhibits no offset voltage at zero drain current and hence
makes an excellent signal chopper. It typically has better thermal stability than a bipolar junction
transistor (BJT)

3. What is transconductance?

Ans: Trasconductance is an expression of the performance of a bipolar transistor or field-effect

transistor (FET). In general, the larger the transconductance figure for a device, the greater the
gain(amplification) it is capable of delivering, when all other factors are held constant. The
symbol for transconductance is gm. The unit is thesiemens, the same unit that is used for direct-
current (DC) conductance.

4. What are the disadvantages of FET?

Ans: It has a relatively low gain-bandwidth product compared to a BJT. The MOSFET has a
drawback of being very susceptible to overload voltages, thus requiring special handling during
installation.The fragile insulating layer of the MOSFET between the gate and channel makes it
vulnerable to electrostatic damage during handling. This is not usually a problem after the device
has been installed in a properly designed circuit.

5. Relation between µ, gm and rd?

Ans: µ = gm * rd

6. Why an input characteristic of FET is not drawn?

7. What is the importance of high input impedance?

8. Why wedge shaped depletion region is formed in FET under reverse bias gate condition?

9. Why FET is less noisy?

10. What is the difference between n- channel FET and p-channel FET?

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Experiment No: 10

RC phase Shift Oscillator Using FET

AIM: To design and test the performance of BJT – RC – Phase shift Oscillator for given
frequency.

COMPONENTS:
Sl. Components Required Range Qty.
No.
1. Power Supply (0-30)V 1
2. CRO 1
3. Resistors 1
4. Capacitors 1
5. Transistors BC 107 1
6. Potentiometers 1

CIRCUIT DIAGRAM:

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Procedure:

 Connect the circuit as per circuit diagram.

 Set Vcc = 10 V, measure the DC voltages at collector (Vc), emitter (Ve) w.r.t ground.
 Adjust the 10 K pot to get a sine wave (stable output) on the CRO.
 Measure the frequency of oscillation using CRO. Compare the theoretical and practical
values.
 Also note the frequency shifts of 60 degrees each across each RC block. (Lissajous
Pattern)

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Expected Waveform:

Result:

Theoretical frequency Practical frequency

LISSAJOUS PATTERNS:

It is the application of CRO Used to find the phase difference between two different sinusoidal
signals.

Procedure to get Lissajous pattern in CRO:

1. Connect the output oscillating signal at coupling capacitor Cc2 to CH1 of CRO. It is
the reference signal to measure phase difference at each RC section in feedback
circuit.

2. Connect output of first RC section at point A in feedback circuit to CH2.

3. Adjust the ground levels of CH1 and CH2 and set both channels to AC-mode.

4. Press XY- mode button in CRO, it displays Lissajous pattern in first quadrant as
shown below

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5. Calculate Phase difference using corresponding formula.

6. Repeat the above procedure for second and third RC sections by changing CH2 probe
position to point B and C respectively. Press XY- mode button in CRO, it displays
Lissajous pattern in second quadrant as shown in above figure.

7. Calculate Phase difference using the formula θ= 180- sin-I (b/a). Compare these
values with theoretical values 6֠, 12֠ and 18֠ at points A, B, C respectively.

EXPERIMENT NO. 11
SERIES VOLTAGE REGULATOR
AIM: To conduct an experiment on series voltage regulator using power transistor and zener
diode and to determine the line and load regulation characteristics.

APPARATUS REQUIRED: Power BJT – 2N3055, SZ9.1, 2.5KΩ/25W, Multimeters, patch

chords.
CIRCUIT DIAGRAM:

DESIGN:

Design of R:

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Current through the Zener diode IZ to keep it in the breakdown region is 10mA.

Design of RL:

Usage of DRB is suggested.

PROCEDURE:

EXPERIMENT NO. 12
CHARACTERISTICS OF MOSFET

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AIM: To draw static characteristic of MOSFET and hence to determine the output resistance
and Trans conductance.

APPARATUS REQUIRED: MOSFET – IRF840, 2.5KΩ/25W, Multimeters, patch chords.

CIRCUIT DIAGRAM:

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Ig1
Ig2
Ig3

Fig 2.2 (a) Static Characteristics of MOSFET.

PROCEDURE:
(a) Transfer Characteristics:

PROCEDURE:
● Connect the circuit as shown in the fig 2.1 (a).
● Set VDS = 10V by varying V1. Keep R1 slightly more than ¼
of the total value.
● Vary VGS by varying V2 and note down IDS for every 0.5V variation of VGS
till 5V of VGS.
● Min VGS voltage that is required for conduction is Threshold voltage”
(VTH).
● Repeat the above experiment for different values of VDS2 = 15V.

Tabular Column:

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V1=VDS1 = 10V
VGS V IDS (mA)
0V

V1 = VDS2 =15V or 12V

VGS V IDS (mA)
0V

(b) Drain Characteristics:

● Rig up the circuit as shown in the fig 2.1(a).

● Adjust VG by varying V2 to VTH.
● Vary VDS by varying V1 in steps of 0.5v and note down IDS
(Till IDS is constant).
● Repeat the above procedure for different values of VGS2 = VTH 0.1 V.
O/P Resistance RD =∆VDS /∆ ID Trans conductance Gm=∆ ID /∆VDS

TABULAR COLUMN:

VGS = VGS1 = VTH VGS = VGS2 = VTH 0.1 V.

VDS (V) IDS(mA) VDS (V) IDS(mA)

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RESULT: The transfer characteristics & collector characteristics are obtained and their
respective graphs are plotted and output resistance and Trans conductance are found.

VIVA QUESTIONS:

1. What are MOSFET’s?

Metal oxide semiconductor field effect transistor is a voltage-controlled device. The parts of
MOSFET are gate, drain and source.

2. Draw the symbol of MOSFET.

3. What is the difference between MOSFET and BJT?

The MOSFET is a voltage controlled device where as BJT is a current controlled device.

4.What is the difference between JFET and MOSFET?

There is no direct contact between the gate terminal and the n-type channel of MOSFET.

5. Draw the structure of MOSFET.

6.What are the two types of MOSFET?

*Depletion MOSFET - N channel in p substrate.

-P channel in n substrate.
*Enhancement mosfet –virtual n channel in p substrate
-Virtual p channel in n substrate

7. What is the difference between depletion and enhancement MOSFET?

The channel in the center is absent for enhancement type MOSFET but the channel is present
in depletion type MOSFET.
The gate voltage can either be positive or negative in depletion type MOSFET’s but
enhancement MOSFET responds only for positive gate voltage.

8. How does n-drift region affect MOSFET?

The n- drift region increases the onstage drop of MOSFET and also the thickness of this region
determines the breakdown voltage of MOSFET.

9. How are MOSFET’s suitable for low power high frequency applications?

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MOSFET’s have high on state resistances due to which losses increase with the increase in the
power levels. Their switching time is low and hence suitable for low power high frequency
applications.

10. What are the requirements of gate drive in MOSFET?

*The gate to source input capacitance should be charged quickly.

*MOSFET turns on when gate source input capacitance is charged to sufficient level.
*The negative current should be high to turn off MOSFET.

11. Draw the switching model of MOSFET.

12.What is rise time and fall time?

The capacitor Cgs charges from threshold voltage to full gate voltage Vgsp. The time required
for this charging is called rise time. During this period, drain current rises to full value.
The capacitor Cgs keeps on discharging and its voltage becomes equal to threshold voltage
Vt.The time required for this discharge Cgs from Vgsp to Vt is called fall time.

13. What is pinch off voltage?

The voltage across gate to source at which the drain to source current becomes zero is called
pinch off voltage.

14. In which region does the MOSFET used as a switch?

In the linear region.

15.Which parameter defines the transfer characteristics?

The Tran conductance Gm=Id/Vgs

16.Why are MOSFET’s mainly used for low power applications?

MOSFET’s have high on state resistance Rds. Hence for higher currents; losses in the
MOSFET’s are substantially increased. Hence MOSFET’s are substantially increased. Hence,
MOSFET’s are mainly used for low power applications.

17.How is MOSFET turned off?

To turn off the MOSFET quickly, the negative gate current should be sufficiently high to
discharge gate source input capacitance.

18.What are the advantages of vertical structure of MOSFET?

*On state resistance of MOSFET is reduced.
*Width of the gate is maximized. Hence, gain of the device is increased.

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19.What are the merits of MOSFET?

* MOSFET’s are majority carrier devices.

*MOSFET’s have positive temperature coefficient, hence their paralleling is easy.
*MOSFET’s have very simple drive circuits.
*MOSFET’s have short turn on and turn off times; hence they operate at high frequencies.
*MOSFET’s do not require commutation techniques.
*Gate has full control over the operation of MOSFET.

20.What are demerits of MOSFET?

*On state losses in MOSFET are high.
*MOSFET’s are used only for low power applications.
*MOSFET’s suffer from static charge.

21.What are the applications of MOSFET?

*High frequency and low power inverters.
*High frequency SMPS.
*High frequency inverters and choppers.
*Low power AC and DC drives.

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DEPT OF E&C
Question Bank

AEC Lab 15ECL37

Q1. Conduct a suitable experiment to demonstrate the working of clipping circuit

with following specification.
a) Positive peak series clipper clipping at _________ V.
b) Double ended clipping at ________ V and _________V.

Q2. Conduct a suitable experiment to demonstrate the working of clipping circuit

with following specification.
a) Negative peak series clipper clipping at _________ V.
b) Double ended clipping at ________ V and _________V.

Q3. Conduct a suitable experiment to demonstrate the working of clipping circuit

with following specification.
a) Positive peak shunt clipper clipping at _________ V.
b) Double ended clipping at ________ V and _________V.

Q4. Conduct a suitable experiment to demonstrate the working of clamping circuit

with following specification.
a) Positive peak clamper clamping at _________ V.
b) Negative peak clamper clamping at ________ V.

Q5. Design and set up the Full Wave rectifier (center tap transformer) with and
without filter to determine ripple factor and rectifier efficiency.

Q6. Design and set up the Full Wave bridge rectifier with and without filter to
determine ripple factor and rectifier efficiency.

Q7. Conduct an experiment on Series Voltage Regulator using Zener diode and
power transistor to determine line and load regulation characteristics .

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Q8. Realize BJT Darlington Emitter follower with and without bootstrapping and
determine the gain, input and output impedances.

Q9. Design and set up the BJT common emitter amplifier using voltage divider
bias with and without feedback and determine the gain bandwidth product from its
frequency response.

Q10. Plot the transfer and drain characteristics of a JFET and calculate
its drain resistance, mutual conductance and amplification factor.

Q11. Design, setup and plot the frequency response of Common Source
JFET amplifier and obtain the bandwidth.

Q12. Plot the transfer and drain characteristics of n-channel MOSFET

and calculate its parameters, namely; drain resistance, mutual
conductance and amplification factor.

Q13. Conduct an experiment to demonstrate the working of complementary

symmetry class B push pull power amplifier and calculate the efficiency.

Q14. Design and set-up the RC-Phase shift Oscillator, and calculate the frequency
of output waveform.

Q15. Design and set-up Hartley’s oscillator circuit using BJT, and determine the
frequency of oscillation.

Q16. Design and set-up Colpitts oscillator circuit using BJT, and determine the
frequency of oscillation.

Q17. Design and set-up the crystal oscillator and determine the frequency of
oscillation.

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