Base-Plus-Index Addressing

Chapter 3: Addressing Modes
Base-Plus-Index Addressing
• Similar to indirect addressing because it

indirectly addresses memory data.
• The base register often holds the beginning
location of a memory array.
– the index register holds the relative position
of an element in the array
– whenever BP addresses memory data, both the
stack segment register and BP generate the
effective address
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Locating Data with Base-Plus-Index
Addressing
• Figure 3–8 shows how data are addressed by
the MOV DX, [BX + DI] instruction when the
microprocessor operates in the real mode.
• The Intel assembler requires this addressing
mode appear as [BX][DI] instead of [BX + DI].
• The MOV DX, [BX + DI] instruction is MOV
DX,[BX][DI] for a program written for the Intel
ASM assembler.
Barry B. Brey
Figure 3–8 An example showing how the base-plus-index addressing mode

functions for the MOV DX, [BX + DI] instruction. Notice that memory address
02010H is accessed because DS=0100H, BX=100H and DI=0010H.

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Register Relative Addressing
• Similar to base-plus-index addressing and
displacement addressing.
– data in a segment of memory are addressed by
adding the displacement to the contents of a base
or an index register (BP, BX, DI, or SI)
• Figure 3–10 shows the operation of the MOV
AX,[BX+1000H] instruction.
• A real mode segment is 64K bytes long.

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Figure 3–10 The operation of the MOV AX, [BX+1000H]

instruction, when BX=1000H and DS=0200H .

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Base Relative-Plus-Index
Addressing
• Similar to base-plus-index addressing.
– adds a displacement
– uses a base register and an index register to
form the memory address
• This type of addressing mode often addresses
a two-dimensional array of memory data.

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Addressing Data with Base

Relative-Plus-Index
• Least-used addressing mode.
• Figure 3–12 shows how data are referenced if
the instruction executed by the microprocessor
is MOV AX, [BX + SI + 100H].
– displacement of 100H adds to BX and SI to form
the offset address within the data segment
• This addressing mode is too complex for
frequent use in programming.
Barry B. Brey
Figure 3–12 An example of base relative-plus-index addressing using a MOV
AX,[BX+SI=1000H] instruction. Note: DS=1000H

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Scaled-Index Addressing
• Unique to 80386 - Core2 microprocessors.
– uses two 32-bit registers (a base register and
an index register) to access the memory

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3–2 PROGRAM MEMORY-
ADDRESSING MODES
• Used with the JMP (jump) and CALL
instructions.
• Consist of three distinct forms:
– direct, relative, and indirect

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Direct Program Memory Addressing

• Used for all jumps and calls by early
microprocessor; also used in high-level
languages, such as BASIC.
• The microprocessor uses this form, but not as
often as relative and indirect program memory
addressing.
• The instructions for direct program memory
addressing store the address with the opcode.

Barry B. Brey
• E.g. JMP 10000H instruction loads CS with
1000H and IP with 0000H to jump to memory
location 10000H for the next instruction.
– an intersegment jump is a jump to any memory
location within the entire memory system
• Often called a far jump because it can jump to
any memory location for the next instruction.
– in real mode, any location within the first 1M byte
– In protected mode operation, the far jump can
jump to any location in the 4G-byte address
range in the 80386 - Core2 microprocessors

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• The only other instruction using direct

program addressing is the intersegment or far
CALL instruction.
• Usually, the name of a memory address,
called a label, refers to the location that is
called or jumped to instead of the actual
numeric address.
• When using a label with the CALL or JMP
instruction, most assemblers select the best
form of program addressing.

Barry B. Brey
Relative Program Memory
Addressing
• Not available in all early microprocessors, but
it is available to this family of microprocessors.
• The term relative means “relative to the
instruction pointer (IP)”.
• The JMP instruction is a 1-byte instruction,
with a 1-byte or a 2-byte displacement that
adds to the instruction pointer.
• An example is shown in Figure 3–15.
Barry B. Brey
Figure 3–15 A JMP [2] instruction. This instruction skips over

the 2 bytes of memory that follow the JMP instruction.

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Indirect Program Memory
Addressing
• The microprocessor allows several forms of
program indirect memory addressing for the
JMP and CALL instructions.
• In 80386 and above, an extended register can
be used to hold the address or indirect
address of a relative JMP or CALL.
– for example, the JMP EAX jumps to the
location address by register EAX

Barry B. Brey
• If a relative register holds the address, the

jump is considered to be an indirect jump.
• For example, JMP [BX] refers to the memory
location within the data segment at the offset
address contained in BX.
– at this offset address is a 16-bit number used as
the offset address in the intersegment jump
– this type of jump is sometimes called an indirect-
indirect or double-indirect jump
• Figure 3–16 shows a jump table that is stored,
beginning at memory location TABLE.
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Figure 3–16 A jump table that stores addresses of various
programs. The exact address chosen from the TABLE is
determined by an index stored with the jump instruction.

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3–3 STACK MEMORY-ADDRESSING

MODES
• The stack plays an important role in all
microprocessors.
– holds data temporarily and stores return
addresses used by procedures
• Stack memory is LIFO (last-in, first-out)
memory
– describes the way data are stored and removed
from the stack

Barry B. Brey
• Data are placed on the stack with a PUSH
instruction; removed with a POP instruction.
• Stack memory is maintained by two registers:
– the stack pointer (SP or ESP)
– the stack segment register (SS)
• Whenever a word of data is pushed onto the
stack, the high-order 8 bits are placed in the
location addressed by SP – 1.
– low-order 8 bits are placed in the location
addressed by SP – 2

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• The SP is decremented by 2 so the next word

is stored in the next available stack location.
– the SP/ESP register always points to an area of
memory located within the stack segment.
• In protected mode operation, the SS register
holds a selector that accesses a descriptor for
the base address of the stack segment.

Barry B. Brey
• PUSH BX places the contents of BX onto
the stack; Whenever a word of data is pushed
onto the stack,
- The high-order 8 bits are placed in the location
addressed by SP –1
- The low-order 8 bits are placed in the location
addressed by SP –2
- after the data are stored by a PUSH, the
contents of the SP register decrement by two

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Barry B. Brey
• (b) POP CX removes data from the stack
and places them into CX. Instruction is
shown after execution.
• When data are popped from the stack,
- The low-order 8 bits are removed from the
location addressed by SP.
- The high-order 8 bits are removed from the
location addressed by SP+1; the SP register is
incremented by 2

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Barry B. Brey
• Note that PUSH and POP store or retrieve
words of data—never bytes—in 8086 - 80286.
• 80386 and above allow words or double
words to be transferred to and from the stack.
• Data may be pushed onto the stack from any
16-bit or 32-bit register or segment register.
• Data may be popped off the stack into any
register or any segment register except CS.

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• PUSHA and POPA instructions push or pop

all except segment registers, on the stack.
• Not available on early 8086/8088 processors.
• 80386 and above allow extended registers to
be pushed or popped.

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Example 1
• Assume that SP=1236, AX=24B6,DI=85C2,
and DX=5F93, show the content of the stack
as each of the following instructions is
executed:
PUSH AX
PUSH DI
PUSH DX

Barry B. Brey

Barry B. Brey
Example 2
• Assume that the stack as shown below and
SP=18FA, show the content of the stack and
registers as each of the following instructions
is executed:
POP CX
POP DX
POP BX

Barry B. Brey

Barry B. Brey

Base-Plus-Index Addressing

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Chapter 3: Addressing Modes

• Similar to indirect addressing because it

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Figure 3–8 An example showing how the base-plus-index addressing mode

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Figure 3–10 The operation of the MOV AX, [BX+1000H]

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Addressing Data with Base

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Direct Program Memory Addressing

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• The only other instruction using direct

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Figure 3–15 A JMP [2] instruction. This instruction skips over

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• If a relative register holds the address, the

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

3–3 STACK MEMORY-ADDRESSING

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• The SP is decremented by 2 so the next word

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• PUSHA and POPA instructions push or pop

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

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