2-1 Internal Microprocessor Architecture

Chapter 2: The Microprocessor and its Architecture
2–1 INTERNAL MICROPROCESSOR

ARCHITECTURE
• Before a program is written or instruction
investigated, internal configuration of the
microprocessor must be known.
• In a multiple core microprocessor each core
contains the same programming model.
• Each core runs a separate task or thread
simultaneously.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
The Programming Model
• Programming model of the 8086 through
Core2 considered to be program visible.
– registers are used during programming and are
specified by the instructions.
• Other registers considered to be program
invisible.
– not addressable directly during applications
programming but may be used indirectly during
system programming.

Barry B. Brey
• 80286 and above contain program-invisible

registers to control and operate protected
memory.
– and other features of the microprocessor
• Figure 2–1 illustrates the programming model
8086 through Core2 microprocessor.
– including the 64-bit extensions

Barry B. Brey
Barry B. Brey
Multipurpose Registers
• RAX (accumulator)- a 64-bit register (RAX),
a 32-bit register (EAX), a 16-bit register (AX),
or as either of two 8-bit registers (AH and AL).
• The accumulator is used for instructions such

as multiplication, division, and some of the
adjustment instructions.

Barry B. Brey
• RBX (base index), addressable as RBX, EBX,
BX, BH, BL.
– BX register sometimes holds address of a location
in the memory system in all versions of the
microprocessor
• RCX (count) , as RCX, ECX, CX, CH, or CL.
– a general-purpose register that also holds the
count for various instructions
• RDX (data) , as RDX, EDX, DX, DH, or DL.
– a general-purpose register that holds a part of the
result from a multiplication or part of dividend
before a division.

Barry B. Brey
• RBP (base pointer), as RBP, EBP, or BP.

– points to a memory location for memory data
transfers.
• RDI (destination index) , as RDI, EDI, or DI.
– often addresses string destination data for the
string instructions
• RSI (source index) , as RSI, ESI, or SI.
– the register addresses source string data for the
string instructions

Barry B. Brey
• R8 - R15 found in the Pentium 4 and Core2 if
64-bit extensions are enabled.
– data are addressed as 64-, 32-, 16-, or 8-bit
sizes and are of general purpose
• Most applications will not use these registers
until 64-bit processors are common.
– the 8-bit portion is the rightmost 8-bit only

Barry B. Brey
Special-Purpose Registers
• RIP (instruction pointer) addresses the next
instruction in a section of memory.
– IP (16-bit) or EIP (32-bit).
• RSP (stack pointer) addresses an area of

memory called the stack.
– SP (16-bit) or ESP (32-bit).

Barry B. Brey
• RFLAGS indicate the condition of the
microprocessor and control its operation.
• The flags never change for any data transfer

or program control operation.
• Figure 2–2 shows the flag registers of all

versions of the microprocessor.

Barry B. Brey
Figure 2–2 The EFLAG and FLAG register counts for the entire 8086 and Pentium
microprocessor family.

Barry B. Brey
Flag bits:
• CF (carry) holds the carry after addition or
borrow after subtraction.
– CF=0 for no carry; CF=1 for carry.
• PF (parity) is the count of ones in a number
expressed as even or odd.
– PF=0 for odd parity; PF=1 for even parity.
– E.g. If a number contains three binary one bits, it
has odd parity; If a number contains no one bits, it
has even parity

Barry B. Brey
• AF (auxiliary carry) holds the carry after

addition or the borrow after subtraction
between bit positions 3 and 4 of the result; it
just used in BCD add/sub ow it is not used.
− AF=0 for no carry; AF=1 for carry.
• ZF (zero) shows that the result of an
arithmetic or logic operation is zero.
− ZF=0 if the result is not zero; ZF=1 if the result is
zero.

Barry B. Brey
• SF (sign) flag holds the arithmetic sign of the
result after an arithmetic or logic instruction
executes.
− SF=0 for positive sign; SF=1 for negative sign.
• TF (trap) the trap flag enables trapping
through an on-chip debugging feature.
− A program is debugged to find an error or bug.
– TF=0 if the trapping feature is disabled; TF=1 if
the trapping feature is enabled; if there is bug the
microprocessor interrupts the flow of the program.

Barry B. Brey
• IF (interrupt) controls operation of the

interrupt request input pin (INTR).
– IF=1 if INTR pin enabled; IF=0 if INTR pin
disabled.
• DF (direction) selects increment or
decrement mode for the DI and/or SI registers.
– DF=1 the registers are automatically
decremented; if DF=0 , the registers are
automatically incremented.

Barry B. Brey
• OF (overflow) occurs when signed numbers
are added or subtracted.
– an overflow indicates the result has exceeded
the capacity of the machine.
– For unsigned operations, the overflow flag is
ignored.
– OF=0 if there is overflow; OF=1 if there is no
overflow.

Barry B. Brey
Segment Registers
• Segment registers generate memory
addresses when combined with other registers
in the microprocessor.
• Following is a list of each segment register,

along with its function in the system:

Barry B. Brey
• CS (code) segment holds code (programs
and procedures) used by the microprocessor.
• DS (data) contains most data used by a

program.
– Data are accessed by an offset address or
contents of other registers that hold the offset
address.
• ES (extra) an additional data segment used
by some instructions to hold destination data.

Barry B. Brey
• SS (stack) defines the area of memory used

for the stack.
– stack entry point is determined by the stack
segment and stack pointer registers

Barry B. Brey
2–2 REAL MODE MEMORY
ADDRESSING
• 80286 and above operate in either the real or
protected mode addressing.
• Real mode operation allows addressing of only
the first 1M byte of memory space.
– the first 1M byte of memory is called the real
memory, conventional memory, or DOS memory

Barry B. Brey
Segments and Offsets

• A combination of a segment address and an
offset address accesses a memory location in
the real mode.
– segment address defines the beginning address
of any 64K-byte memory segment
– offset address selects any location within the
64K byte memory segment
• Figure 2–3 shows how the segment plus offset
addressing scheme selects a memory location.

Barry B. Brey
Figure 2–3 The real mode memory-addressing scheme, using
a segment address plus an offset.
– this shows a memory

segment beginning at
10000H, ending at
location IFFFFH
• 64K bytes in length
– also shows how an offset

address, called a
displacement, of F000H
selects location
1F000H in the memory
Barry B. Brey
• In the real mode, each segment register is

internally appended with a 0H on its rightmost
end.
• For example, when a segment register
contains 1200H, it addresses a 64K-byte
memory segment beginning at location
12000H.

Barry B. Brey
• Once the beginning address is known, the
ending address is found by adding FFFFH.
– because a real mode segment of memory is64K
in length
– For example, if a segment register contains
3000H, the first address of the segment is
30000H, and the last address is
30000H + FFFF = 3FFFFH.

Barry B. Brey
• The offset address is always added to the

segment starting address to locate the data.
• Segment and offset address is sometimes
written as 1000:2000.
– a segment address of 1000H; an offset of 2000H

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Default Segment and Offset
Registers
• The microprocessor has rules that apply to
segments whenever memory is addressed.
– these define the segment and offset register
combination
• For example, the CS register is always used
with the IP to address the next instruction in a
program, this combination is CS:IP.

Barry B. Brey
• The code segment register defines the start of

the code segment. The instruction pointer
locates the next instruction within the code
segment.
• For example, if CS=1400H and IP=1200H, the
microprocessor fetches its next instruction
from memory location 14000H+1200H=
15200H.

Barry B. Brey
• Another of the default combinations is the
stack.
• stack data are referenced through the stack
segment at the memory location addressed
by either the stack pointer (SS:SP) or the
base pointer (SS:BP)
• For example, if SS=2000H and BP=3000H,
the microprocessor addresses memory
location 23000H for the stack segment
memory location.

Barry B. Brey
Quiz

Barry B. Brey
• What is the main difference
between??
1- DRAM & SDRAM
2-SDRAM & DDR SDRAM
• Calculate address memory

location if segment address is
FFFFH& offset address is
4000H??
Barry B. Brey

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Chapter 2: The Microprocessor and its Architecture

2–1 INTERNAL MICROPROCESSOR

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• 80286 and above contain program-invisible

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• The accumulator is used for instructions such

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• RBP (base pointer), as RBP, EBP, or BP.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• RSP (stack pointer) addresses an area of

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• The flags never change for any data transfer

• Figure 2–2 shows the flag registers of all

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• AF (auxiliary carry) holds the carry after

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• IF (interrupt) controls operation of the

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• Following is a list of each segment register,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• DS (data) contains most data used by a

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• SS (stack) defines the area of memory used

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Segments and Offsets

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

– this shows a memory

– also shows how an offset

• In the real mode, each segment register is

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• The offset address is always added to the

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• The code segment register defines the start of

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

• Calculate address memory

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