4ME3-21 - Digital Electronics Lab

Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA

Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
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E-mail: [email protected] Web: www.skit.ac.in
A
Course File
on
(Digital Electronics Lab: 4ME3-21)
Programme: Mechanical Engineering
Semester: IV
Session: 2021-2022
Pramod Jain
Assistant Professor
Mechanical Engineering Department
Pramod Jain /Mechanical Department/2021-2022 Page 1

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Institute Vision/Mission/Quality Policy
Institute Vision
"To promote higher learning in advanced technology and industrial research to make our country a
global player."
Mission
"To promote quality education, training and research in the field of Engineering by establishing
effective interface with industry and to encourage faculty to undertake industry sponsored projects
for students. "
Quality Policy
We are committed to ‘achievement of quality’ as an integral part of our institutional policy by

continuous self-evaluation and striving to improve ourselves.
Institute would pursue quality in
o All its endeavors like admissions, teaching- learning processes, examinations, extra
and co-curricular activities, industry institution interaction, research & development,
continuing education, and consultancy.
o Functional areas like teaching departments, Training & Placement Cell, library,
administrative office, accounts office, hostels, canteen, security services, transport,
maintenance section and all other services.”

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Departmental Vision/Mission
Vision
To become a nationally visible mechanical engineering department with excellence in teaching-
learning, research and development, entrepreneurship and industry outreach activities.
Mission
M1. To provide facilities and environment conducive to high quality education and research and
development in the field of mechanical engineering.
M2. To inculcate technical, professional and communication skills in students, staﬀ and faculty
members.
M3. To instill innovative skills, critical thinking, leadership & team work in students through various
teaching-learning activities and industry linkages.
M4. To inculcate strong ethical qualities in the students and faculty for realizing lifelong learning and
serving the society and nation at large.

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4ME3-21: DIGITAL ELECTRONICS LAB
Credit: 1.5 Max. Marks: 75 (IA:45,

ETE:30) 0L+0T+3P
SN
1 To verify the truth tables of basic logic gates: AND, OR, NOR, NAND, NOR. Also to
verify the truth table of Ex-OR, Ex-NOR (For 2, 3 & 4 inputs using gates
with 2, 3, & 4 inputs).
2 To verify the truth table of OR, AND, NOR, Ex-OR. Ex-NOR realized using
NAND & NOR gates.
3 To realize an SOP and POS expression.
4 To realize Half adder/ Subtractor & Full Adder/ Subtractor using NAND & NOR gates
and to verify their truth tables.
5 To realize a 4-bit ripple adder/ Subtractor using basic half adder/ Subtractor & basic
Full Adder/ Subtractor.
6 To verify the truth table of 4-to-l multiplexer and l-to-4 demultiplexer. Realize the
multiplexer using basic gates only. Also to construct and 8-to-1 multiplexer and l-to-8
demultiplexer using blocks of 4-to-1 multiplexer and 1-to-4
demulriplexer.
7 Design & Realize a combinational circuit that will accept a 2421 BCD code and
drive a TIL -3 I 2 seven-segment display.
8 Using basic logic gates, realize the R-S, J-K and D-flip flops with and without
clock signal and verify their truth table.
9 Construct a divide by 2, 4 & 8 asynchronous counter. Construct a 4-bit binary
counter and ring counter for a particular output pattern using D flip flop.
10 Perform input/output operations on parallel in/parallel out and Serial
in/Serial out registers using clock. Also exercise loading only one of multiple values into
the register using multiplexer.
Note: As far as possible, the experiments shall be performed on bread board. However
experiment Nos. l-4 are to be performed on bread board only

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Prerequisite of Course
Mechatronics requires knowledge of the following subjects:
1. Electronic circuits - Basics
2. Binary Number System
3. Mathematics - Calculus, differential equations, numerical methods

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List of Text and Reference Books
Text Book
S.No. Title of Book Author(S) Publication
Modern Digital
1 R P Jain TMH
Electronics
Reference Books
S.No. Title of Book Author(s) Publication
1 Digital Electronics Anand Kumar TMH

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Time Table
Day 8-9 9- 10-11 L 11:30- 12:30- 1:30-

10 12:30 1:30 2:30
Monday U DE Lab A-2
Tuesday N
Wednusday DE B-2 C
Lab
Tursday H
Friday DE A-1
Lab
Saturday

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PO/PSO-Indicator-Competency
PO 1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization for the solution of complex engineering
problems.
Competency Indicators
1.1.1 Apply the knowledge of calculus, linear algebra,

statistics and dynamics to solve simple mechanical
1.1 Demonstrate competence in engineering problem.
mathematical modelling
1.1.2 Apply the theories of probability, statistics and
numerical techniques for mathematical modeling and
simulation of nonlinear.
1.2 Demonstrate competence in basic 1.2.1 Apply fundamental concepts of physical

sciences sciences to handle mechanical engineering problems.
1.3. Demonstrate competence in 1.3.1 Apply fundamentals of engineering sciences

engineering fundamentals (..ics) in problems of mechanical engineering
1.4.1 Apply advanced manufacturing engineering

1.4. Demonstrate competence in concepts viz. 3D printing to solve complex engineering
specialized engineering knowledge to problems.
the program
PO 2: Problem analysis: Identify, formulate, research literature, and analyze complex

engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
2.1.1. Realize the target solution, define problem

statements and specify the main objective
2.1 Demonstrate an ability to identify 2.1.2. Identify the parametric dependence of the target
and formulate complex engineering solution to the problem
problem
2.1.3. Identify the required knowledge in physical
science, or mathematical knowledge needed to handle
the defined engineering problem

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2.2.1 Reframe the mechanical engineering system into

interconnected subsystems which may require input
from other branch of engineering
2.2.2 Identify, assemble and evaluate information

required and resources available to solve the problem
2.2.3 take a stock of employable solution methods

2.2 Demonstrate an ability to formulate which includes adoption of processes, mathematical
a solution plan and methodology for an modeling and computer simulation for solving the
engineering problem problem, with properly justified approximations and
assumptions
2.2.4 Compare and contrast the different solution

processes and select the best mechanical engineering
process.
2.3.1. Use engineering concepts and underlying

scientific principles to formulate a physical model, a
prototype or a mathematical model to describe the
2.3. Demonstrate an ability to formulate applicability with acceptable accuracy of the solution
and interpret a model system or process whichever is applicable.
2.3.2. Examine if the assumptions made for the

contemplated modeling is reasonable in real life
situation with the acceptable level of accuracy.
2.4.1Derive the solutions of the proosed mathematical

model with the help of available and suitable
mathematical or computational technique.
2.4.2 Get the case specific results and validate them by

using contemporary engineering tools.
2.4. Demonstrate an ability to execute a 2.4.3. Measure the certainty factor of the proposed
solution process and analyze results model, identify the error in the solution process, or the
inherited limitations of the solution
and the sources of inaccuracy thereof
2.4.4. Acquire the understanding of merits/demerits of

the model created arrive at conclusions consistent with

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objectives of the task.
PO 5: Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modelling to complex engineering
activities with an understanding of the limitations.
5.1.1 Identify modern engineering tools, techniques

such as 3D printer, CAD/CAM simulation tools viz. 3D
5.1 Demonstrate an ability to identify / modeler, Comsol Mutiphysics, ANSYS and other FEM
create modern engineering tools, simulator and similar resources for mechanic al
engineering activities
techniques and resources
5.1.2 Create/adapt/modify/extend tools and techniques
to solve mechanical engineering problems
5.2.1 Identify the strengths and limitations of tools for

(i) generating data/acquiring information, (ii) modeling
5.2 Demonstrate an ability to select and and simulating, (iii) monitoring system performance,
apply discipline specific tools, and (iv) creating engineering designs.
techniques and resources
5.1.2 Demonstrate proficiency in using tools needed for
mechanical engineering activities in manufacturing/
design/ prototyping/ material testing etc.
5.3.1.Discuss limitations and validate tools, techniques

5.3 Demonstrate an ability to evaluate
and resources
the suitability and limitations of
5.3.2. Verify the credibility of results from tool use with
tools used to solve an engineering
reference to the accuracy and limitations, and the
problem
assumptions inherent in their use.

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Teaching-Learning Methodology
 Experiments
 Demonstrations
 Concept Maps
 Models
 Charts
 Animation
 Virtual Lab

Swami Keshvanand Institute of
Technology,M&G,Jaipur
Department of Mechanical Engineering
4ME3-21: DIGITAL ELECTRONICS LAB
INDEX
Name:......................................................................... Roll No........................................... Batch. …………………….

Group Members:........................................................................................................................................................
Exp Date of Grade/ Sign.

No. Performance Marks Faculty
Title of Experiment
With
Date
1 To verify the truth tables of basic logic gates: AND, OR,
NOR, NAND, NOR. Also to verify the truth table of Ex-
OR, Ex-NOR (For 2, 3 & 4 inputs using gates with 2, 3, &
4 inputs).
2 To verify the truth table of OR, AND, NOR, Ex-OR.
Ex-NOR realized using NAND & NOR gates.
3 To realize an SOP and POS expression.
4 To realize Half adder/ Subtractor & Full Adder/ Subtractor

using NAND & NOR gates and to verify their truth tables.
5 To realize a 4-bit ripple adder/ Subtractor using basic half

adder/ Subtractor & basic Full Adder/ Subtractor.
6 To verify the truth table of 4-to-l multiplexer and l-to-4

demultiplexer. Realize the multiplexer using basic gates
only. Also to construct and 8-to-1 multiplexer and l-to-8
demultiplexer using blocks of 4-to-1 multiplexer and 1-to-4
demulriplexer.
7 Design & Realize a combinational circuit that
will accept a 2421 BCD code and drive a TIL -3
I 2 seven-segment display.
8 TUsing basic logic gates, realize the R-S, J-K and D-
flip flops with and without clock signal and verify
their truth table
9 Construct a divide by 2, 4 & 8 asynchronous counter.
Construct a 4-bit binary counter and ring counter for a
particular output pattern using D flip flop.
10 Perform input/output operations on parallel in/parallel out
and Serial in/Serial out registers using clock. Also exercise
loading only one of multiple values into the register using
multiplexer.
BC-1 Design and construct Binary code to Grey code and verify
function.
BC-2 Design and construct 8*1 multiplexer 74151 IC.
Faculty sign………………….
SWAMI KESHVANAND INSTITUTE OF TECHNOLOGY
MANAGEMENT & GRAMOTHAN
Experiment No: 1
Aim: To verify the truth tables of basic logic gates: AND, OR, NOR, NAND, NOR. Also to
verify the truth table of Ex-OR, Ex-NOR (For 2, 3 & 4 inputs using gates with 2, 3, & 4
inputs).
Apparatus Required: Digital trainer kit (SCIENTECH ST-2610)
Component Required: Digital IC’s
S. No. COMPONENT SPECIFICATION
1. 2 i/p AND GATE IC 7408

2. 2 i/p OR GATE IC 7432
3. NOT GATE IC 7404
4. 2 i/p XOR GATE IC 7486
5. 2 i/p Ex-NOR IC74266

GATE
6. 2 i/p NAND GATE IC 7400

7. 2 i/p NOR GATE IC 7402
Theory:
LOGIC GATES: Logic gates are the basic building blocks of any digital system. It is
an electronic circuit having one or more than one input and only one output. The
relationship between the input and the output is based on a certain logic. Based on
this, logic gates are named as AND gate, OR gate, NOT gate etc.
The Digital Logic "AND" Gate
A Logic AND Gate is a type of digital logic gate that has an output which is normally
at logic level "0" and only goes "HIGH" to a logic level "1" when ALL of its inputs
are at logic level "1". The output of a Logic AND Gate only returns "LOW" again
when ANY of its inputs are at a logic level "0". The logic or Boolean expression
given for a logic AND gate is that for Logical Multiplication which is denoted by a
single dot or full stop symbol, (.) giving us the Boolean expression of: A.B = Q.
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Then we can define the operation of a 2-input logic AND gate as being:
"If both A and B are true, then Q is true"
2-input AND Gate
Symbol Truth Table
B A Q
0 0 0
0 1 0
2-input AND Gate 1 0 0
1 1 1
Boolean Expression Q = A.B Read as A AND B gives Q
Commonly available digital logic AND gate IC’s included:

TTL Logic Types CMOS Logic Types
 74LS08 Quad 2-input  CD4081 Quad 2-input
 74LS11 Triple 3-input  CD4073 Triple 3-input
 74LS21 Dual 4-input  CD4082 Dual 4-input
Quad 2-Input AND Gate IC 7408
Triple 3-input AND Gate IC 7411
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Dual 4-input AND Gate IC 7421
The Logic "OR" Gate
A Logic OR Gate or Inclusive-OR gate is a type of digital logic gate that has an
output which is normally at logic level "0" and only goes "HIGH" to a logic level "1"
when ANY of its inputs are at logic level "1". The output of a Logic OR Gate only
returns "LOW" again when ALL of its inputs are at a logic level "0". The logic or
Boolean expression given for a logic OR gate is that for Logical Addition which is
denoted by a plus sign, (+) giving us the Boolean expression of: A+B = Q.
Then we can define the operation of a 2-input logic OR gate as being:

"If either A or B is true, then Q is true"
2-input OR Gate
Symbol Truth Table

B A Q
0 0 0
0 1 1
2-input OR Gate 1 0 1
1 1 1
Boolean Expression Q = A+B Read as A OR B gives Q
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Commonly available OR gate IC’s included:

 CD4075 Triple 3-input
 CD4072 Dual 4-input
Quad 2-Input OR Gate IC 7432
The Digital Logic "NOT" Gate (Digital Inverter)
The digital Logic NOT Gate is the most basic of all the logical gates and is sometimes
referred to as an Inverting Buffer or simply a Digital Inverter. It is a single input
device which has an output level that is normally at logic level "1" and goes "LOW"
to a logic level "0" when its single input is at logic level "1", in other words it
"inverts" (complements) its input signal. The output from a NOT gate only returns
"HIGH" again when its input is at logic level "0" giving us the Boolean expression
of: A = Q.
Then we can define the operation of a single input logic NOT gate as being:
"If A is NOT true, then Q is true"
Symbol Truth Table

A Q
0 1
Inverter or NOT Gate 1 0
Boolean Expression Q = not A or A Read as inverse of A gives Q
Then, with an input voltage at "A" HIGH, the output at "Q" will be LOW and an input
voltage at "A" LOW the Resulting output voltage at "Q" is HIGH producing the
complement of the input signal.
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Commonly available logic NOT gate and Inverter IC's include

 74LS04 Hex Inverting NOT Gate  CD4009 Hex Inverting NOT
 74LS04 Hex Inverting NOT Gate Gate
 74LS14 Hex Schmitt Inverting NOT  CD4069 Hex Inverting NOT
Gate Gate
 74LS1004 Hex Inverting Drivers
Hex Inverter Gate IC 7404
UNIVERSAL GATES:
The Logic "NAND" Gate
The Logic NAND Gate is a combination of the digital logic AND gate with that of an
inverter or NOT gate connected together in series. The NAND (Not - AND) gate has
an output that is normally at logic level "1" and only goes "LOW" to logic level "0"
when ALL of its inputs are at logic level "1". The Logic NAND Gate is the reverse or
"Complementary" form of the AND gate we have seen previously.
Logic NAND Gate Equivalence
The logic or Boolean expression given for a logic NAND gate is that for Logical
Addition, which is the opposite to the AND gate, and which it performs on the
complements of the inputs. The Boolean expression for a logic NAND gate is denoted
by a single dot or full stop symbol, (.) with a line or Overline, ( ‾‾ ) over the
expression to signify the NOT or logical negation of the NAND gate giving us the
Boolean expression of: A.B = Q. Then we can define the operation of a 2-input logic
NAND gate as being:
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"If either A or B are NOT true, then Q is true"
Symbol Truth Table

B A Q
0 0 1
0 1 1
2-input NAND Gate 1 0 1
1 1 0
Boolean Expression Q = A.B Read as A AND B gives NOT Q
Commonly available logic NAND gate IC’s including:

 74LS30 Single 8-input
Quad 2-Input NAND Gate IC 7400
Triple 3-Input NAND Gate IC 7410
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Dual 4-Input NAND Gate IC 7420
The Logic "NOR" Gate
The Logic NOR Gate or Inclusive-NOR gate is a combination of the digital logic OR
gate with that of an inverter or NOT gate connected together in series. The NOR
(Not - OR) gate has an output that is normally at logic level "1" and only goes "LOW"
to logic level "0" when ANY of its inputs are at logic level "1". The Logic NOR Gate
is the reverse or "Complementary" form of the OR gate we have seen previously.
NOR Gate Equivalent
The logic or Boolean expression given for a logic NOR gate is that for Logical
Multiplication which it performs on the complements of the inputs. The Boolean
expression for a logic NOR gate is denoted by a plus sign, (+) with a line or Over line,
( ‾‾ ) over the expression to signify the NOT or logical negation of the NOR gate
giving us the Boolean expression of: A+B = Q.
Then we can define the operation of a 2-input logic NOR gate as being:
"If both A and B are NOT true, then Q is true"
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Symbol Truth Table

B A Q
0 0 1
0 1 0
2-input NOR Gate 1 0 0
1 1 0
Boolean Expression Q = A+B Read as A OR B gives NOT Q
Commonly available NOR gate IC's include:

Quad 2-Input NOR Gate 7402
Triple 3-Input NOR Gate IC 7427
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Dual 4-Input NOR Gate IC 7425
The Exclusive-OR Gate (Ex-OR Gate)
The output of an Exclusive-OR gate ONLY goes "HIGH" when its two input
terminals are at "DIFFERENT" logic levels with respect to each other and they can
both be at logic level "1" or both at logic level "0" giving us the Boolean expression
of: Q = A’B + AB’. The Exclusive-OR Gate function is achieved is achieved by
combining standard gates together to form more complex gate functions. An example
of a 2-input Exclusive-OR gate is given below.
2-input Ex-OR Gate
Symbol Truth Table

B A Q
0 0 0
0 1 1
2-input Ex-OR Gate 1 0 1
1 1 0
Boolean Expression
Read as A OR B but NOT BOTH gives Q
Q=A⊕B
Quad 2-Input Ex-OR Gate IC 7486
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The Exclusive-NOR Gate
The output of an Exclusive-NOR gate ONLY goes "HIGH" when its two input
terminals, A and B are at the "SAME" logic level which can be either at a logic level
"1" or at a logic level "0". Then this type of gate gives and output "1" when its inputs
are "logically equal" or "equivalent" to each other, which is why an Exclusive-NOR
gate is sometimes called an Equivalence Gate.
Ex-NOR Gate Equivalent
Symbol Truth Table

B A Q
0 0 1
0 1 0
2-input Ex-NOR Gate 1 0 0
1 1 1
Boolean Expression Q = A XNOR B Read if A AND B the SAME gives Q
In general, an Exclusive-NOR gate will give an output value of logic "1" ONLY when
there are an EVEN number of 1's on the inputs to the gate (the inverse of the Ex-OR
gate) except when all its inputs are "LOW". Commonly available Exclusive-NOR
gate IC's include:
74LS266 Quad 2-input CD4077 Quad 2-input
Quad 2-Input Ex-NOR Gate IC 74266
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Procedure:
 Test the digital ICs with the help of IC tester.

 Make the connections on the breadboard as per the pin diagram. Connect the
inputs of logic gate to the logic sources and its output to the logic indicator.
 Apply various input combinations and observe output for each one.
 Verify the truth table for each input/ output combination.
 Repeat the process for all other logic gates.
Result: The truth tables of logic gates: AND, OR, NOT, NAND, NOR Ex-OR and
Ex-NOR are verified using their ICs.
Conclusion: In conclusion, each basic gate works in unique way, which is proved
during this experiment. We used the truth table to examine the operation of the basic
logic gate. It is proved from experiment that logic gates work in basis of Boolean
algebra. AND Gate, OR Gate and NOT Gate are the basic gates. All the
combinational logic gates are made of these three basic gates. Output from one logic
gate can be used as input for another logic gate to form combinational logic gate. So,
we have studied how logic gates work on the basis of Boolean algebra.
Discussion:
1. Define the term Digital and Analog.

2. What is Integrated Circuit?
3. Define the Basic and Universal gates.
4. If a 3-input NOR gate has eight input possibilities, how many of those possibilities
will Result in a HIGH output?
5. The output of a logic gate is ‘1’ when all its input are at logic 0.The gate is either
(a)NAND or an EX OR gate
(b)NOR or an EX-NOR gate
(c)An OR or an EX NOR gate
(d)An AND or an EX-OR gate
6. Which of the logical operations is represented by the + sign in Boolean algebra?
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Experiment No.2
Aim: To verify the truth table of OR, AND, NOR, Ex-OR. Ex-NOR realized using
NAND & NOR gates.
Apparatus Required: Digital trainer kit (SCIENTECH ST-2610)
Component Required: Digital ICs (7400, 7402)
Theory:
Universal Gates (NAND & NOR Gates):

A universal gate is a gate which can implement any Boolean function without need to
use any other gate type. The NAND and NOR gates are universal gates. This is
advantageous since NAND and NOR gates are economical and easier to fabricate.
NAND Gate is a Universal Gate:

To prove that any Boolean function can be implemented using only NAND gates, we
will show that the AND, OR, and NOT operations can be performed using only these
gates.
Implementing an Inverter Using only NAND Gate

The figure shows two ways in which a NAND gate can be used as an inverter
(NOT gate).
1. All NAND input pins connect to the input signal A gives an output A’.
Y = (A.A)’
=> Y = (A)’
2. One NAND input pin is connected to the input signal A while all other input pins
are connected to logic 1. The output will be A’.
Implementing AND Using only NAND Gates

3. An AND gate can be replaced by NAND gates as shown in the figure (The AND
is replaced by a NAND gate with its output complemented by a NAND gate
inverter).
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Y = ((A.B)’)’
=> Y = (A.B)
Implementing OR Using only NAND Gates

4. An OR gate can be replaced by NAND gates as shown in the figure (The OR gate
is replaced by a NAND gate with all its inputs complemented by NAND gate
inverters).
From DE Morgan’s theorems: (A.B)’ = A’ + B’

=> (A’.B’)’ = A’’ + B’’ = A + B
Thus, the NAND gate is a universal gate since it can implement the AND, OR
and NOT functions.
Implementing NOR Using only NAND Gates

A NOR gate is an OR gate followed by NOT gate. So connect the output of OR gate
to a NOT gate, overall output is that of a NOR gate.
Y = (A + B)’
Implementing EX-OR Using only NAND Gates
The output of a two input X-OR gate is shown by: Y = A’B + AB’. This can be
achieved with the logic diagram shown.
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Gate No. Inputs Output

1 A, B (AB)’
2 A, (AB)’ (A (AB)’)’
3 (AB)’, B (B (AB)’)’
4 (A (AB)’)’, (B (AB)’)’ A’B + AB’
Now the output from gate no. 4 is the overall output of the configuration.
Y = ((A (AB)’)’ (B (AB)’)’)’

= (A(AB)’)’’ + (B(AB)’)’’
= (A(AB)’) + (B(AB)’)
= (A(A’ + B)’) + (B(A’ + B’))
= (AA’ + AB’) + (BA’ + BB’)
= ( 0 + AB’ + BA’ + 0 )
= AB’ + BA’
=> Y = AB’ + A’B
Implementing EXNOR Using only NAND Gates
X-NOR gate is actually X-OR gate followed by NOT gate. So give the output of X-
OR gate to a NOT gate, overall output is that of an X-NOR gate.
Y = AB+ A’B’
NOR Gate is a Universal Gate:

To prove that any Boolean function can be implemented using only NOR gates, we
will show that the AND, OR, and NOT operations can be performed using only
these gates.
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Implementing an Inverter Using only NOR Gate

The figure shows two ways in which a NOR gate can be used as an inverter (NOT
gate).
1. All NOR input pins connect to the input signal A gives an output A’.
Y = (A+A)’
=> Y = (A)’
2. One NOR input pin is connected to the input signal A while all other input pins are
connected to logic 0. The output will be A’.
Implementing OR Using only NOR Gates
An OR gate can be replaced by NOR gates as shown in the figure (The OR is

replaced by a NOR gate with its output complemented by a NOR gate inverter)
Y = ((A+B)’)’
=> Y = (A+B)
Implementing AND Using only NOR Gates
An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is
replaced by a NOR gate with all its inputs complemented by NOR gate inverters)
From DE Morgan’s theorems: (A+B)’ = A’B’

=> (A’+B’)’ = A’’B’’ = AB
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Thus, the NOR gate is a universal gate since it can implement the AND, OR and
NOT functions.
Implementing EX-NOR Using only NOR Gates

The output of a two input X-NOR gate is shown by: Y = AB + A’B’. This can
be achieved with the logic diagram shown.
Gate No. Inputs Output

1 A, B (A + B)’
2 A, (A + B)’ (A + (A+B)’)’
3 (A + B)’, B (B + (A+B)’)’
4 (A + (A + B)’)’, (B + (A+B)’)’ AB + A’B’
Now the output from gate no. 4is the overall output of the configuration.
Y = ((A + (A+B)’)’ (B +( A+B)’)’)’
= (A+(A+B)’)’’.(B+(A+B)’)’’
= (A+(A+B)’).(B+(A+B)’)
= (A+A’B’).(B+A’B’)
= (A + A’).(A + B’).(B+A’)(B+B’)
= 1.(A+B’).(B+A’).1
= (A+B’).(B+A’)
= A.(B + A’) +B’.(B+A’)
= AB + AA’ +B’B+B’A’
= AB + 0 + 0 + B’A’
= AB + B’A’
=> Y = AB + A’B’
Implementing EXOR Using only NOR Gates
X-OR gate is actually X-NOR gate followed by NOT gate. So give the output of X-
NOR gate to a NOT gate, overall output is that of an X-OR gate.
Y = A’B+ AB’
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Implementing NAND Using only NOR Gates

A NAND gate is an AND gate followed by NOT gate. So connect the output of AND
gate to a NOT gate, overall output is that of a NAND gate.
Y = (AB)’
Procedure:
 Test the digital ICs (7400, 7402) with the help of IC tester.
 Make the connections on breadboard as per the pin diagram. Connect the
inputs of the logic gate to the logic sources and its output to the logic
indicator.
 Verify the truth table for each input/ output combination.
Result: The truth tables of logic gates: AND, OR, NOT, NAND, NOR Ex-OR and
Ex-NOR are verified using the universal gate ICs 7400 and IC 7402.
Conclusion: The universal gates are the gates which can implement any Boolean
function without need to use any other gate type. Hence all the gates are realized using
Universal gates. In practice, this is advantageous since NAND and NOR gates are
economical and easier to fabricate and are the mostly used gates in digital logic families.
Discussion:
1. Why NAND & NOR gates are called universal gates?

2. Which gate is equal to AND-inverter Gate?
3. Which gate is equal to OR-inverter Gate?
4. Draw X= ab + b’a’ by NAND gate?
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5. What is DE Morgan’s theorem?

6. Solve following example by DE Morgan’s theorem
1) (A+B+C)’ 2) (ABC)’ (AB)’ 3) (A+A) A =?
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Experiment No.3
Aim: -To realize an SOP and POS expression.
Two input SOP - A.B + A’.B’

Two input POS: - (A+B) (B+C) (A+C’)
Apparatus Required: Digital trainer kit (SCIENTECH ST-2610), IC tester
Components Required: Digital ICs (7404, 7408, and 7432).
Theory:
Sum of Product (SOP)
The sum-of-products (SOP) form is a method (or form) of simplifying the Boolean
expressions of logic gates. In this SOP form of Boolean function representation, the
variables are operated by AND (product) to form a product term and all these product
terms are ORed (summed or added) together to get the final function. Here the
product terms are defined by using the AND operation and the sum term is defined by
using OR operation.
SOP form representation is most suitable to use them in FPGA (Field Programmable
Gate Arrays).
Product of Sums (POS)

The product of sums form is a method (or form) of simplifying the Boolean
expressions of logic gates. In this POS form, all the variables are ORed, i.e. written as
sums to form sum terms. All these sum terms are ANDed (multiplied) together to get
the product-of-sum form. This form is exactly opposite to the SOP form. So this can
also be said as “Dual of SOP form”.
Here the sum terms are defined by using the OR operation and the product term is
defined by using AND operation.
Implement the following SOP function

Two input SOP - A.B + A’.B’
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Implement the following POS function
Two input POS: - (A+B) (B+C) (A+C’)
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Procedure:
 Test the digital ICs with the help of IC tester.

 Make the connections on the breadboard as per the pin diagram and circuit.
Connect the inputs of the logic gate to the logic sources and its output to the
logic indicator.
 Verify the circuit for each input/ output combination.
Result: We have implemented the given Boolean function using logic gates in both SOP
and POS forms.
Conclusion: In the experiment, De-Morgan’s theorem and postulate of Boolean
algebra are verified. Also the Sum of products and product of sum expressions are
realized using the basic gates and the universal gates.
Discussion:
1. Express the function f(x, y, z) = 1 in the form of sum of minterms and a

product of maxterms.
2. What is D’morgans theorem?
3. Solve following example by using D’morgans theorem.
(ABC)’ (AB)’
4. Examine this truth table and then write both SOP and POS Boolean expressions
describing the Output:
A B C output
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
5. Convert the following SOP expression to an equivalent POS expression.
6. Express the function f(x, y, z) = 1 in the sum of minterms and a product of

maxterms?
Minterms = (0,1,2,3,4,5,6,7), Maxterms = No maxterms.
7. Make the truth table of πM(1,2,6,7,13,14,15) + d(0,3,5)?
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Experiment No: 4
Aim: To realize half adder/ Subtractor & Full Adder/ Subtractor using NAND &
NOR gates and to verify their truth table.
Apparatus Required: Digital trainer kit (SCIENTECH ST-2610), IC tester
Component Required: Digital ICs (7400, 7402)
Theory: A very useful combinational logic circuit which can be constructed using
just a few basic logic gates and adds together binary numbers is the Binary Adder
circuit. The Binary Adder is made up from standard AND and Ex-OR gates and allow
us to "add" together single bit binary numbers, a and b to produce two outputs, the
SUM of the addition and a CARRY. One of the main uses for the Binary Adder is in
arithmetic and counting circuits.
The Half Adder Circuit
1-bit Adder with Carry-Out
Half Adder Truth Table

A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Boolean Expression: Sum = A ⊕ B Carry = A . B
From the truth table we can see that the SUM (S) output is the Result of the Ex-OR
gate and the Carry-out (CARRY) is the Result of the AND gate. One major
disadvantage of the Half Adder circuit when used as a binary adder, is that there is no
provision for a "Carry-in" from the previous circuit when adding together multiple
data bits.
Circuit diagram for half-adder using NAND gates
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Circuit diagram for half-adder using NOR gates
The Full Adder Circuit: The main difference between the Full Adder and the
previous seen Half Adder is that a full adder has three inputs, the same two single bit
binary inputs A and B as before plus an additional Carry-In (C) input as shown
below.
Full Adder Truth Table

CARRY
A B C SUM
(Cout)
0 0 0 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1
0 0 1 1 0
0 1 1 0 1
1 0 1 0 1
1 1 1 1 1
Boolean Expression: Sum = A ⊕ B ⊕ C-in
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Full Adder implementation using NAND Gate
The Half Subtractor Circuit
A half-subtractor has two inputs and two outputs. Let the input variables minuend and
subtrahend be designated as X and Y respectively, and output functions be designated
as D for difference and B for borrow. The truth table of the functions is as follows.
Truth Table
Half Subtractor
X Y D B
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
Boolean Expression: DIFF = A ⊕ B BORROW = A’. B
Circuit diagram for half-Subtractor using NAND gates.
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Circuit diagram for half-Subtractor using NOR gates.
The Full Subtractor Circuit
A combinational circuit of full-Subtractor performs the operation of subtraction of

three bits—the minuend, subtrahend, and borrow generated from the subtraction
operation of previous significant digits and produces the outputs difference and
borrow. Let us designate the input variables minuend as A/X, subtrahend as B/Y, and
previous borrow as C/Z, and outputs difference as D and B as Borrow. Eight different
input combinations are possible for three input variables.
Full Subtractor Truth Table

a/X b/Y C/Z D B
0 0 0 0 0
0 1 0 1 1
1 0 0 1 1
1 1 0 0 1
0 0 1 1 0
0 1 1 0 0
1 0 1 0 0
1 1 1 1 1
Boolean Expression: D = a ⊕ b ⊕ c; B= a’b+bc+b’c
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Full Subtractor implementation using NAND Gate
Full Subtractor implementation using NOR Gate
Procedure:
1. Insert the IC chips into the breadboard. Point all the chips in the same direction
with pin 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next
to it on the chip package).
2. Connect +5V and GND pins of each IC chips to the power and ground bus strips
on the breadboard.
3. Make the connections as per the circuit diagram.
4. Switch on VCC and apply various combinations of input according to truth table.
5. Note down the output readings for half/full adder and sum and the carry bit for
different combinations of inputs. Where 5V indicating logic 1 and 0V indicating
logic 0.
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Result: The truth table for Half adder/Subtractor and Full Adder/Subtractor has been
verified.
Conclusion: By using various logic gate ICs we can design full or half adder and
subtractor. Half adders/subtractors perform their operation on two bits and gives a two bit
output. Full adder/subtractor perform their operation on three bit inputs and gives a two
bit output.
Discussion:
1. Define Combinational Circuits.

2. What is the difference between half adder and a full adder?
3. What is meant by two and three variable map?
4. Realize a full adder using two half adders.
5. Realize a full subtractors using two half subtractors.
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Experiment No: 5
Aim: To realize a 4-bit ripple adder/Subtractor using basic half adder/ Subtractor and
basic full adder/ Subtractor.
Apparatus / Component Required: IC tester, Digital trainer kit, Digital ICs (7483,
7486, 7404, 7408, and 7432)
Theory:
In digital circuits, an adder–Subtractor is a circuit that is capable of adding or

subtracting numbers (in particular, binary). Adder-subtractor is a circuit that does
adding or subtracting depending on a control signal. It is also possible to construct a
circuit that performs both addition and subtraction at the same time.
4 Bit Binary Adder

A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output
carry from each full adder connected to the input carry of next full adder in chain. The
augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers
from right to left, with subscript 0 denoting the least significant bits. The carries are
connected in chain through the full adder. The input carry to the adder is C0 and it
ripples through the full adder to the output carry C4.
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4 Bit Binary Subtractor

The circuit for subtracting A-B consists of an adder with inverters, placed between
each data input ‘B’ and the corresponding input of full adder. The input carry C0 must
be equal to 1 when performing subtraction.
4 Bit Binary Adder/Subtractor

The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the
circuit is adder circuit. When M=1, it becomes Subtractor.
Pin Diagram for IC 7483
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LOGIC DIAGRAM:
Logic Diagram for 4-Bit Binary Adder
Logic Diagram for 4-Bit Binary Subtractor:
Logic Diagram for 4-Bit Binary Adder/Subtractor:
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Observations for IC 7483
Procedure:
1. Test the digital ICs with the help of IC tester.
3. Connect the output pin on LED through Resistor.
5. Observe the logical output and verify with the truth tables.
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Result: Thus the 4-bit adder and subtractor using IC 7483 was designed and
implemented.
Conclusion: A four bit ripple carry adder/subtractor can be designed by using four
full adders/subtractors. They can also be designed by using IC 7483 by using
appropriate selection mode (M).
Precautions:
1. All ICs should be checked before starting the experiment.
2. All the connection should be tight.
3. Always connect ground first and then connect Vcc.
Discussions:
1. What is BCD adder?

2. What is the difference between adder and parallel adder?
3. How many full adders are required to construct an m-bit parallel adder?
4. What are the disadvantages of the ripple-carry adder/Subtractor?
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Experiment No: 6
Aim: To verify the truth table of 4-to-l multiplexer and l-to-4 demultiplexer. Realize the
multiplexer using basic gates only. Also to construct and 8-to-1 multiplexer and l-to-8
demultiplexer using blocks of 4-to-1 multiplexer and 1-to-4 demultiplexer.
Apparatus / Component Required: IC tester, Digital trainer kit, Digital ICs (74153,
74151, 7408, 7432, 7404, 7411, 74155)
Theory:
(a) MULTIPLEXER:
Combinational logic switching devices that operate like a very fast acting multiple
position rotary A data selector, more commonly called a Multiplexer, shortened to
"Mux" or "MPX", are switch. They connect or control, multiple input lines called
"channels" consisting of 2, 4, 8 or 16 individual inputs, one at a time to an output.
Then the job of a multiplexer is to allow multiple signals to share a single common
output.
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that
selects binary information from one of many input lines and directs it to a single
output line. The selection of a particular input line is controlled by a set of selection
lines. Normally there are 2n input line and n selection lines whose bit combination
determine which input is selected.
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:
TRUTH TABLE:
S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3
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CIRCUIT DIAGRAM FOR MULTIPLEXER:
FUNCTION TABLE:
S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0
Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0
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PIN DIAGRAM FOR IC 74153
TRUTH TABLE OF 4:1 MUX(IC 74153) (CHANNEL A) WITH ACTIVE LOW

MODE:
Inputs(Channel A) Select lines Output

Ea Iao Ia1 Ia2 Ia3 S0 S1 Za
1 × × × × × × 0
0 0 × × × 0 0 0
0 1 × × × 0 0 1
0 × 0 × × 0 1 0
0 × 1 × × 0 1 1
0 × × 0 × 1 0 0
0 × × 1 × 1 0 1
0 × × × 0 1 1 0
0 × × × 1 1 1 1
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IMPLEMENTATION OF 8:1 MULTIPLEXER USING 4:1 MUX:
CIRCUIT OF 8:1 MUX USING DUAL 4:1 MUX
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TRUTH TABLE OF 8:1 MUX
Truth table of 8:1 MUX
IMPLEMENTATION OF 8:1 MULTIPLEXER (74151)
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(b) DEMULTIPLEXER:
The function of De-multiplexer is in contrast to multiplexer function. It takes

information from one line and distributes it to a given number of output lines. For this
reason, the de-multiplexer is also known as a data distributor. Decoder can also be
used as de-multiplexer. In the 1: 4 de-multiplexer circuit, the data input line goes to
all of the AND gates. The data select lines enable only one gate at a time and the data
on the data input line will pass through the selected gate to the associated data output
line.
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:
TRUTH TABLE:
OUTPUT
INPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
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LOGIC DIAGRAM FOR DEMULTIPLEXER:
PIN DIAGRAM OF DUAL 1:4 DEMUX (IC74155)
TRUTH TABLE OF 1:4 DEMUX(IC 74155) WITH ACTIVE LOW MODE:
Input(Channel A) Output
Ea S0 S1 D0 D1 D2 D3
1 × × 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
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IMPLEMENTATION OF 1:8 DEMULTIPLEXER USING 1:4 DEMUX:

(74155)
CIRCUIT OF 1:8 DMUX USING DUAL 1:4 DMUX
TRUTH TABLE OF 1:8 DEMUX
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Procedure:

Result: Hence the 4:1mux and 1:4 demux is designed with basic gate as given in the
figure and verified with the truth table. 8:1 mux are designed with 4:1mux and 1:8
demux are designed with 1:4 demux as given in circuit.
Conclusion: 4:1 multiplexer and 8:1 multiplexer and 1:4 demultiplexer and 1:8
demultiplexer can be realized using basic logic gates, they can also be designed by using
IC 74153 (multiplexer), IC 74155 (demultiplexer) and IC 74151 (multiplexer).
Precautions:
1. All ICs should be checked before starting the experiment.

Discussions:
1. What is the function of the enable input in a Multiplexer?

2. What is the difference between multiplexer and decoder?
3. List out the applications of multiplexer?
4. Realize the following Boolean expression using 4:1 MUXs only
5. How many select lines will a 32:1 multiplexer will have.

6. Give the applications of Demultiplexer.
7. The logic realized by the circuit shown in figure is
8.
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Experiment No: 7
Aim: Design and realize a combinational circuit that will accept the 2421 BCD code
and drive a TIL-312 to 7-Segment Display
Apparatus / Component Required: IC tester, Digital trainer kit, Digital ICs (7447),
register (200 Ω / 330 Ω), seven segment display
Theory:
The Binary Coded Decimal (BCD) to 7-Segment Display Decoder. 7-segment LED
(Light Emitting Diode) or LCD (Liquid Crystal) displays, provide a very convenient
way of displaying information or digital data in the form of numbers, letters or even
alpha-numerical characters and they consist of 7 individual LED's (the segments),
within from 0 to 9 and A to F respectively, on the display the correct combination of
LED segments need to be illuminated and BCD to 7-segment Display Decoders such
as the 74LS47 do just that. A standard 7-segment LED display generally has 8 input
connections, one for each LED segment and one that acts as a common terminal or
connection for all the internal segments.
There are two important types of 7-segment LED digital display.

 The Common Cathode Display (CCD) - In the common cathode display, all the
cathode connections of the LED's are joined together to logic "0" and the
individual segments are illuminated by application of a "HIGH", logic "1" signal
to the individual Anode terminals.
 The Common Anode Display (CAD) - In the common anode display, all the anode
connections of the LED's are joined together to logic "1" and the individual
segments are illuminated by connecting the individual Cathode terminals to a
"LOW", logic "0" signal.
7-Segment Display Format
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7-Segment Display Elements for all Numbers.
It can be seen that to display any single digit number from 0 to 9 or letter from A to F,
we would need 7 separate segment connections plus one additional connection for the
LED's "common" connection. Also as the segments are basically a standard light
emitting diode, the driving circuit would need to produce up to 20mA of current to
illuminate each individual segment and to display the number 8, all 7 segments would
need to be lit resulting a total current of nearly 140mA, (8 x 20mA). Obviously, the
use of so many connections and power consumption is impractical for some electronic
or microprocessor based circuits and so in order to reduce the number of signal lines
required to drive just one single display, display decoders such as the BCD to 7-
Segment Display Decoder and Driver IC's are used instead.
Combinational circuit for converting 2421 BCD code to seven segment number
Both the 2421 code and BCD code are 4-bit codes and represent the decimal
equivalents 0 to 9. To design the converter circuit for the above, first the truth table is
prepared with the input variables W, X, Y, and Z of 2421 code, and the output
variables A, B, C, and D. Karnaugh maps to obtain the simplified expressions of the
output functions are shown in Figure. Unused combinations are considered as don’t-
care condition.
Table 1: Truth Table for BCD to Seven Segment

Decoder
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The output expressions are:
a = F1 (A, B, C, D) = ∑m (0, 2, 3, 5, 7, 8, 9)
b = F2 (A, B, C, D) = ∑m (0, 1, 2, 3, 4, 7, 8, 9)
c = F3 (A, B, C, D) = ∑m (0, 1, 3, 4, 5, 6, 7, 8, 9)
d = F4 (A, B, C, D) = ∑m (0, 2, 3, 5, 6, 8)
e = F5 (A, B, C, D) = ∑m (0, 2, 6, 8)
f = F6 (A, B, C, D) = ∑m (0, 4, 5, 6, 8, 9)
g = F7 (A, B, C, D) = ∑m (2, 3, 4, 5, 6, 8, 9)
The K-Map of the above expressions are:
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Fig.2 Logic diagram of BCD to Seven segment decoder
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Procedure:
2. Make the connections as per the circuit diagram on the digital trainer kit.
3. Connect the output pins to the seven segment pins.
4. Switch on VCC and apply various combinations of input according to the truth
table.
BCD to 7-Segment Display Decoders using TTL 74LS47
A binary coded decimal (BCD) to 7-segment display decoder such as the TTL
74LS47 or 74LS48, have 4 BCD inputs and 7 output lines, one for each LED
segment. This allows a smaller 4-bit binary number (half a byte) to be used to display
all the denary numbers from 0 to 9 and by adding two displays together, a full range
of numbers from 00 to 99 can be displayed with just a single byte of 8 data bits.
PIN diagram for 7447 IC:
Fig.3: PIN diagram for 7447 IC
The use of packed BCD allows two BCD digits to be stored within a single byte (8-
bits) of data, allowing a single data byte to hold a BCD number in the range of 00 to
99.
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Fig.4 BCD to 7-Segment Display Decoders using TTL 74LS47
Observations: For DM7447A:
Symbol Parameter Min Typical Max Unit
Vcc Supply Voltage 4.75 5 5.25 V
VIH High Level Input Voltage 2 - - V
VIL Low Level Input Voltage - - 0.8 V
VOH High level output voltage(a - - 30

to g)
IOH High Level Output - - -0.2 µA

Current(BI/RBO)
IOL Low Level Output Current(a - - 40 mA

to g)
Result: Hence the BCD to seven segment display is designed using basic gates and
with a BCD to seven segment display IC as given in the figure and verified with the
truth table.
Conclusion: It is possible to display any single digit number on a 7-segment display

by sending a high digital signal to the specific segments that make up the number. It is
possible to display the decimal value of a binary number on a 7-segment display using
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a BCD decoder. However, this method will allow displaying only digits from 0 to 9.
In the case of the decoder circuit, any binary number between 1010 through 1111 (A
to F) is an invalid input and would provide distorted shapes on the LCD display. The
usage of a 7-segment display paired with a BCD decoder is opening the door for an
application using digital computation requiring a human-readable that application can
be for instance: “a clock, a timer, a calculator, counter…” Thus we had concluded that
7 segment display can be implemented using IC, s and we had seen different numbers
0-9.
Precautions:
• All connections should be made neat and tight.
• Digital Lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
Discussions
1. What is code conversion?

2. Can a decoder function as a Demultiplexer?
3. Give the applications of seven segment display?
4. What are happened if the input given in between A to F.
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Experiment No: 8
Aim: Using basic logic gates realize the R-S, J-K and D flip flops with and without
clock pulse and verify truth table.
Apparatus / Component Required: IC tester, Digital trainer kit, connecting wires,

Digital ICs (7400, 7402, 7404, 7408, 7432)
Theory:
Sequential Logic circuits have some form of inherent "Memory" built in to them as
they are able to take into account their previous input state as well as those actually
present, a sort of "before" and "after" is involved with sequential circuits.
In other words, the output state of a sequential logic circuit is a function of the
following three states, the "present input", the "past input" and/or the "past output".
Sequential Logic circuits remember these conditions and stay fixed in their current
state until the next clock signal changes one of the states, giving sequential logic
circuits "Memory".
Sequential logic circuits are generally termed as two state or Bistable devices which
can have their output or outputs set in one of two basic states, a logic level "1" or a
logic level "0" and will remain "latched" (hence the name latch) indefinitely in this
current state or condition until some other input trigger pulse or signal is applied
which will cause the bistable to change its state once again.
Sequential Logic Representation
The word "Sequential" means that things happen in a "sequence", one after another
and in Sequential Logic circuits, the actual clock signal determines when things will
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happen next. Simple sequential logic circuits can be constructed from standard
Bistable circuits such as Flip-flops, Latches and Counters and which themselves can
be made by simply connecting together universal NAND Gates and/or NOR Gates in
a particular combinational way to produce the required sequential circuit.
FLIP-FLOP:-
"Flip-flop" is the common name given to two-state devices which offer basic memory
for sequential logic operations. Flip-flops are heavily used for digital data storage and
transfer and are commonly used in banks called "register" for the storage of binary
numerical data.
S-R Flip Flop
The SR flip-flop can be considered as a 1-bit memory, since it stores the input pulse
even after it has passed. Flip-flops (or bi-stables) of different types can be made from
logic gates and, as with other combinations of logic gates, the NAND and NOR gates
are the most versatile, the NAND being most widely used. This is because, as well as
being universal, i.e. it can be made to mimic any of the other standard logic functions,
it is also cheaper to construct. The SET-RESET flip flop is designed with the help of
two NOR gates and also two NAND gates. These flip flops are also called S-R Latch.
 S-R Filp Flop using NOR Gate(Without Clock)
The design of such a flip flop includes two inputs, called the SET [S] and RESET [R].
There are also two outputs, Q and Q’. The diagram and truth table is shown below.
Fig. 2: Logic Diagram of NOR based S-R Flip flop
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Truth Table-1 : S-R Latch using NOR Gate
Inputs Outputs Action

S R Qn+1
0 0 Qn No change
0 1 0 1 Reset
1 0 1 0 Set
1 1 ? ? Forbidden
 S-R Flip Flop using NAND Gate(Without Clock)
The circuit of the S-R flip flop using NAND Gate and its truth table is shown below.
Fig. 3: Logic Diagram of NAND based S-R Latch
Truth Table -2: S-R Latch using NAND Gate

S R Qn+1
0 0 ? ? Forbidden
0 1 1 0 Set
1 0 0 1 Reset
1 1 Qn No
change
 Clocked S-R Flip Flop
It is also called a Gated S-R flip flop.
The problems with S-R flip flops using NOR and NAND gate is the invalid state. This
problem can be overcome by using a bistable SR flip-flop that can change outputs
when certain invalid states are met, regardless of the condition of either the Set or the
Reset inputs. For this, a clocked S-R flip flop is designed by adding two NAND gates
to a basic NAND Gate flip flop. The circuit diagram and truth table is shown below.
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Fig. 4: Logic Diagram of NAND based Clocked S-R Flip flop
Truth Table: 3 Clocked Based S-R Flip Flop
Clock Inputs Outputs Action

CLK S R Qn+1
0 X X Qn No
change
1 0 0 Qn No
change
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 ? ? Forbidden
D Flip Flop
D flip flop is actually a slight modification of the above explained clocked SR flip-
flop. From the figure you can see that the D input is connected to the S input and the
complement of the D input is connected to the R input.
 D Flip Flop without clock
The circuit diagram of D latch with NAND gates:
Fig. 5: Logic Diagram of NAND Based D Latch
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Truth Table 4: D Latch
Enable Input Output

En D Qn+1
0 X Qn
1 0 0
1 1 1
 Clocked D Flip Flop

The D flip-flop is the modification of the SR flip flop which is shown in the
figure 5. The i/p D goes directly into the input S and the complement of the
input D goes to the input R. The D input is sampled during the existence of a
clock pulse. If it is 1, then the flip flop is switched to the set state. If it is 0,
then the flip-flop switches to the clear state.
Fig. 6: Logic Diagram of Clocked based D Flip Flop
Truth Table 5: D Flip Flop
Clock Input Output

CLK D Qn+1
0 X Qn
1 0 0
1 1 1
 IC 7474 (D FF)
J-K Flip Flop
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JK flip-flop is basically an SR flip flop with feedback which enables only one of its
two input terminals, either SET or RESET to be active at any one time thereby
eliminating the invalid condition seen previously in the SR flip flop circuit. The only
difference is that the intermediate state is more refined and precise than that of an S-R
flip flop.
 JK Flip Flop without clock
JK latch is similar to RS latch. This latch consists of 2 inputs J and K as shown in the
below figure 6. The ambiguous state has been eliminated here: when the inputs of J-K
latch are high, then output toggles. The output feedback to inputs is the only
difference, which is not there in the RS latch.
Fig.7: Logic Diagram of J-K Latch
Truth Table 6: J-K Latch

J K Qn+1
0 0 Qn No
change
0 1 0 1 Reset
1 0 1 0 Set
1 1 Qn Toggle
When both the inputs J and K have a HIGH state, the flip-flop switches to the
complement state. So, for a value of Q = 1, it switches to Q=0 and for a value of Q =
0, it switches to Q=1.
 JK Flip Flop with clock

A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of
the SR type is defined in the JK type. Inputs J and K behave like inputs S and R to
set and clear the flipflop (note that in a JK flip-flop, the letter J is for set and the
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letter K is for clear). When logic 1 inputs are applied to both J and K
simultaneously, the flip-flop switches to its complement state, ie., if Q=1, it
switches to Q=0 and vice versa
The circuit diagram and truth-table of a J-K flip flop is shown below.
Fig.8: Logic Diagram of J-K Clocked Flip Flop
Truth Table 6: J-K Flip Flop

Clock Inputs Outputs Action
CLK J K Qn+1
0 X X Qn No
change
1 0 0 Qn No
change
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 Qn Toggle
The output may be repeated in transitions once they have been complimented for
J=K=1 because of the feedback connection in the JK flip-flop. This can be avoided by
setting a time duration lesser than the propagation delay through the flip-flop. The
restriction on the pulse width can be eliminated with a master-slave or edge-triggered
construction.
 IC 7476 (JK FF)
Procedure:
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3. Connect the output pin of LED on Digital Trainer Kit.
4. Switch on VCC and apply various combinations of input according to the truth
table.
Observations:
Symbol Parameter Min Typical Max Unit
Vcc Supply Voltage 4.75 5 5.25 V
VIH High Level Input Voltage 2 - - V
VIL Low Level Input Voltage - - 0.8 V
IOH High Level Output Current - - -0.4 mA
IOL Low Level Output Current - - 16 mA
Result: Hence the S-R, J-K, D flip flops with and without clocks are designed with
basic gates IC and verified with the truth table.
Conclusion:
 The function of the S – R flip-flop is to store a bit value of either 0 or 1 for

later use based on the S and R input values. When S is high, the flip-flop
stores a logic value of 1 and stores a logic 0 when input R is high.
 The D – Flip-flop operates by propagating the logic level placed on the input
D to the Output Q on the high edge of the clock. When the clock level is low,
the state of the flip-flop latches and output does not change
 The J-K flip-flop sequential operation is the same as the S-R flip-flop with set
and reset inputs. But it has no forbidden or invalid input states of the S-R
Latch, when both inputs, S and R, are both equal to logic 1.
Precautions:
• All the connections should be made properly.

• Digital Lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.
Discussions:
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1. What is sequential circuit?

2. What is Synchronous sequential circuit?
3. What is an excitation table?
4. What do you mean by triggering of flip-flop.
5. What is called latch?
6. What advantage does a J-K Flip-flop have over an S-R?
7. What is meant by Race around condition?
Experiment No: 9
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Aim: Construct a divide by 2, 4 & 8 asynchronous counter. Construct a 4-bit binary

counter and ring counter for a particular output pattern using D flip flop.
Apparatus / Component Required: IC tester, Digital trainer kit, Digital IC 7474
Theory: A counter is a register capable of counting number of clock pulse arriving at

its clock input. Counter represents the number of clock pulses arrived. An up/down
counter is one that is capable of progressing in increasing order or decreasing order
through a certain sequence. An up/down counter is also called bidirectional counter.
Usually up/down operation of the counter is controlled by up/down signal.
Asynchronous or ripple counters are arranged in such a way that the output of one flip
flop changes the state of the next. In a long chain of ripple counter stages, the last flip
flop changes its state considerably later than the first FF due to propagation delays in
each stage. If the output lines are connected to logic which can respond to these in-
between states, glitches can occur that are so fast the error may be difficult to track
down.
The 2-bit ripple counter circuit has four different states, each one corresponding to a
count value. Similarly, a counter with n flip-flops can have 2 to the power n states.
The number of states in a counter is known as its mod (modulo) number. Thus a 2-
bit counter is a mod-4 counter.
A mod-n counter may also describe as a divide-by-n counter. This is because the
most significant flip-flop (the furthest flip-flop from the original clock pulse)
produces one pulse for every n pulses at the clock input of the least significant flip-
flop (the one triggers by the clock pulse). Thus, the above counter is an example of a
divide-by-4 counter.
Divide by Two Counter

The edge-triggered D-type ip-ops which we introduced in the previous Section are
quite useful and versatile building blocks of sequential logic. A simple application is
the divide-by-2counter shown in Fig. 1, along with the corresponding timing diagram.
Divide by four Counter
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Since the Q output of the first flip flop changes every time the clock input goes low, it
effectively divides the input frequency by 2. The other output of the flip flop
becomes the clock input to the next stage, so the output of the second flip flop divides
the original input frequency by 4. Hence the term "divide-by-4" or "modulo-4".
Divide by Eight Counter
We can chain as many ripple counters together as we like. A three bit ripple counter
will count 23=8 numbers, and an n-bit ripple counter will count 2n numbers.
The problem with ripple counters is that each new stage put on the counter adds a
delay. This propagation delay is seen when we look at a less idealized timing
diagram:
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Binary 4 bit UP-COUNTER
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Ring Counter
A ring counter is a Shift Register (a cascade connection of flip-flops) with the output
of the last flip flop connected to the input of the first. It is initialized such that only
one of the flip flop output is 1 while the remainder is 0. The 1 bit is circulated so the
state repeats every n clock cycles if n flip-flops are used. The "MOD" or
"MODULUS" of a counter is the number of unique states. The MOD of the n flip flop
ring counter is n.
The following is a 4-bit ring counter constructed from D flip-flops. The output of
each stage is shifted into the next stage on the positive edge of a clock pulse. If the
CLEAR signal is high, all the flip-flops except the first one FF0 are reset to 0. FF0 is
preset to 1 instead.
Since the count sequence has 4 distinct states, the counter can be considered as a mod-
4 counter. Only 4 of the maximum 16 states are used, making ring counters very
inefficient in terms of state usage. But the major advantage of a ring counter over a
binary counter is that it is self-decoding. No extra decoding circuit is needed to
determine what state the counter is in.
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IC used for realizing above counters:
Procedure:
Result: counters are designed with the help of trainer kit and verified with the truth
table.
Conclusion: Divide by 2, 4 & 8 asynchronous counter,4-bit binary counter and ring

counter for a particular output pattern using D flip flop are designed and their truth
table are verified.
When the value of output voltage is greater than 2.4V then it will be represented by
logic 1 and if output voltage is less then 0.4 volt it will be represented by logic 0.
Precautions:

3. The kit should be off before change the connections.

4. After completed the experiments switch off the supply of the apparatus.
Discussions:
1. What is the difference between synchronous and asynchronous counter?
2. What is up and down counter?
3. How many flip flops are required for designing the decade counter.
4. How the synchronous counters eliminate the delay problems encountered in
asynchronous counters.
5. Design Mod 5 counter in synchronous mode.
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Experiment No: 10
Aim: Perform input/output operations on parallel in/parallel out and Serial in/Serial out
registers using clock. Also exercise loading only one of multiple values into the register using
multiplexer.
Apparatus / Component Required: IC tester, Digital trainer kit, Digital ICs 7474
Theory:
A flip-flop stores 1-bit of digital information. It is also referred to as 1-bit register. An

array of flip-flops is required to store the no. of bits. This is called register. The data
can be entered into or retrieved from the register. A register is capable of shifting its
binary information in one or both directions is known as shift register. The logical
configuration of shift register consist of a D-Flip flop cascaded with output of one flip
flop connected to input of next flip flop. All flip flops receive common clock pulses
which causes the shift in the output of the flip flop. The simplest possible shift register
is one that uses only flip-flops, as shown in figure. The Q output of a given flip-flop is
connected to the D input of the flip-flop at its right. Each clock pulse shifts the
contents of the register one bit position to the right. The serial input determines what
goes into the leftmost flip-flop during the shift. The serial output is taken from the
output of the rightmost flip-flop prior to the application of a pulse. Although this
register shifts its contents to the right, if we turn the page upside down; we find that
the register shifts its contents to the left. Thus a unidirectional shift register can
function either as a shift-right or as shift-left register.
The register in figure shifts its contents with every clock pulse during the positive
edge of the pulse transition. If we want to control the shift so that it occurs only with
certain pulses but not with others, we must control CLK input of the register.
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Shift registers can be used for converting serial data to parallel, and vice versa. If we
have access to all the flip-flop outputs of a shift register, then information entered
serially by shifting can be taken out in parallel from the outputs of the flip-flops. If a
parallel-load capability is added to a shift register, then data entered in parallel can be
taken out in serial fashion by shifting the data stored in the register.
There are five basic types of shift registers:

1) Serial in serial out (SISO)
2) Serial in parallel out (SIPO)
3) Parallel in serial out (PISO)
4) Parallel in parallel out (PIPO)
5) Bidirectional shift registers
Unidirectional shift register - Serial in serial out (SISO)

A Serial-in Serial-out shift register can be implemented using D-type flip-flops joined
together, the output of one flip-flop used as the input to the next flip-flop. The circuit
for a 4-bit Serial-in Serial-out shift register is shown below.
The operation of the serial-in Serial-out shift register can be easily explained.
Consider the circuit shown. On each clock edge (rising in this case) we can say the
following about the outputs of each stage of the register (i.e. each D-type flip-flop in
the register):
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Waveforms
Serial in parallel out (SIPO)

 In such types of operations, the data is entered serially and taken out in parallel
fashion.
 Data is loaded bit by bit. The outputs are disabled as long as the data is loading.
 As soon as the data loading gets completed, all the flip-flops contain their
required data, the outputs are enabled so that all the loaded data is made
available over all the output lines at the same time.
 4 clock cycles are required to load a four bit word. Hence the speed of operation
of SIPO mode is same as that of SISO mode.
Truth Table
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Clock Pulse No QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 0 0 0 0
Parallel-in to Serial-out (PISO)
The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to
parallel-out one above. The data is loaded into the register in a parallel format i.e. all
the data bits enter their inputs simultaneously, to the parallel input pins P A to PD of the
register. The data is then read out sequentially in the normal shift-right mode from the
register at Q representing the data present at P A to PD. This data is outputted one bit at
a time on each clock cycle in a serial format. It is important to note that with this
system a clock pulse is not required to parallel load the register as it is already
present, but four clock pulses are required to unload the data.
Truth Table
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
As this type of shift register converts parallel data, such as an 8-bit data word into
serial format, it can be used to multiplex many different input lines into a single serial
DATA stream which can be sent directly to a computer or transmitted over a
communications line.
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Parallel-in to Parallel-out (PIPO)
The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type
of register also acts as a temporary storage device or as a time delay device similar to
the SISO configuration above. The data is presented in a parallel format to the parallel
input pins PA to PD and then transferred together directly to their respective output
pins QA to QA by the same clock pulse. Then one clock pulse loads and unloads the
register. This arrangement for parallel loading and unloading is shown below.
TRUTH TABLE:
CLK DATA INPUT OUTPUT

DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
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Pin Diagram for IC 7495:
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Page 68
PISO
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PROCEDURE:
Serial In Parallel Out (SIPO):

1. Connections are made as per circuit diagram.
2. Apply the data at serial i/p
3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.
4. Apply the next data at serial i/p.
5. Apply one clock pulse at clock 2, observe that the data on QA will shift to
QB and the new data applied will appear at QA.
6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the
shift register.
Serial In Serial Out (SISO):

2. Load the shift register with 4 bits of data one by one serially.
3. At the end of 4th clock pulse the first data ‘d0’ appears at QD.
4. Apply another clock pulse; the second data ‘d1’ appears at QD.
5. Apply another clock pulse; the third data appears at QD.
6. Application of next clock pulse will enable the 4th data ‘d3’ to appear at
QD. Thus the data applied serially at the input comes out serially at QD
Parallel In Serial Out (PISO):

2. Apply the desired 4 bit data at A, B, C and D.
3. Keeping the mode control M=1 apply one clock pulse. The data applied at
A, B, C and D will appear at QA, QB, QC and QD respectively.
4. Now mode control M=0. Apply clock pulses one by one and observe the
Data coming out serially at QD
Parallel In Parallel Out (PIPO):

2. Apply the 4 bit data at A, B, C and D.
3. Apply one clock pulse at Clock 2 (Note: Mode control M=1).
4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD
respectively.
Result: Thus the Serial in serial out, Serial in parallel out, Parallel in serial out and
Parallel in parallel out shift registers were implemented using IC 7495.
Conclusion: Shift registers using IC 7495 in all its modes i.e.SIPO/SISO, PISO/PIPO
are verified by their truth table. When the value of output voltage is greater than 2.4V
then it will be represented by logic 1 and if output voltage is less than 0.4 volt it will
be represented by logic 0.
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Precautions:
1. All the connections should be made properly.

2. IC should not be reversed.
Discussions:
1. What is bi-directional shift register and unidirectional shift register?

2. Write the uses of a shift register?
3. Shifting a register content to left by one bit position is equivalent to
(A) division by two. (B) addition by two.
(B) multiplication by two. (D) subtraction by two.
4. Can a shift register be used as a counter? If yes, explain how?
.
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Swami Keshvanand Institute of Technology, Management &Gramothan,

Ramnagaria, Jagatpura, Jaipur-302017, INDIA

Pramod Jain /Mechanical Department/2021-2022 Page 1

Institute Vision/Mission/Quality Policy

We are committed to ‘achievement of quality’ as an integral part of our institutional policy by

Institute would pursue quality in

Pramod Jain /Mechanical Department/2021-2022 Page 2

Pramod Jain /Mechanical Department/2021-2022 Page 3

4ME3-21: DIGITAL ELECTRONICS LAB

Credit: 1.5 Max. Marks: 75 (IA:45,

Pramod Jain /Mechanical Department/2021-2022 Page 4

1. Electronic circuits - Basics

2. Binary Number System

3. Mathematics - Calculus, differential equations, numerical methods

Pramod Jain /Mechanical Department/2021-2022 Page 5

List of Text and Reference Books

1 Digital Electronics Anand Kumar TMH

Pramod Jain /Mechanical Department/2021-2022 Page 6

Day 8-9 9- 10-11 L 11:30- 12:30- 1:30-

Pramod Jain /Mechanical Department/2021-2022 Page 7

1.1.1 Apply the knowledge of calculus, linear algebra,

1.2 Demonstrate competence in basic 1.2.1 Apply fundamental concepts of physical

1.3. Demonstrate competence in 1.3.1 Apply fundamentals of engineering sciences

1.4.1 Apply advanced manufacturing engineering

PO 2: Problem analysis: Identify, formulate, research literature, and analyze complex

2.1.1. Realize the target solution, define problem

Pramod Jain /Mechanical Department/2021-2022 Page 8

2.2.1 Reframe the mechanical engineering system into

2.2.2 Identify, assemble and evaluate information

2.2.3 take a stock of employable solution methods

2.2.4 Compare and contrast the different solution

2.3.1. Use engineering concepts and underlying

2.3.2. Examine if the assumptions made for the

2.4.1Derive the solutions of the proosed mathematical

2.4.2 Get the case specific results and validate them by

and the sources of inaccuracy thereof

2.4.4. Acquire the understanding of merits/demerits of

Pramod Jain /Mechanical Department/2021-2022 Page 9

objectives of the task.

5.1.1 Identify modern engineering tools, techniques

5.2.1 Identify the strengths and limitations of tools for

5.3.1.Discuss limitations and validate tools, techniques

Pramod Jain /Mechanical Department/2021-2022 Page 10

Pramod Jain /Mechanical Department/2021-2022 Page 11

Pramod Jain /Mechanical Department/2021-2022 Page 12

Pramod Jain /Mechanical Department/2021-2022 Page 13

Pramod Jain /Mechanical Department/2021-2022 Page 14

Name:......................................................................... Roll No........................................... Batch. …………………….

Exp Date of Grade/ Sign.

3 To realize an SOP and POS expression.

4 To realize Half adder/ Subtractor & Full Adder/ Subtractor

5 To realize a 4-bit ripple adder/ Subtractor using basic half

6 To verify the truth table of 4-to-l multiplexer and l-to-4

Apparatus Required: Digital trainer kit (SCIENTECH ST-2610)

Component Required: Digital IC’s

S. No. COMPONENT SPECIFICATION

1. 2 i/p AND GATE IC 7408

5. 2 i/p Ex-NOR IC74266

6. 2 i/p NAND GATE IC 7400