Pin Diagram of 8086
Pin Diagram of 8086
Pin Diagram of 8086
com
Intel
It
This
microprocessor had
major improvement over
the execution speed of
8085.
It
is available as 40-pin
Dual-Inline-Package
(DIP).
www.eazynotes.com
It
is available in three
versions:
8086
(5 MHz)
8086-2 (8 MHz)
8086-1 (10 MHz)
It
consists of 29,000
transistors.
www.eazynotes.com
It
And
bus.
20 line address
It
could address up to 1
MB of memory.
It
It
supports
multiplication and
division.
www.eazynotes.com
www.eazynotes.com
These
During
In
AD0-AD7
of data.
AD8-AD15
These
lines are
multiplexed unidirectional
address and status bus.
During
In
BHE
BHE
signal is used to
indicate the transfer of data
over higher order data bus
(D8 D15).
8-bit
It
It
It
is an output signal.
It
www.eazynotes.com
10
This
is an acknowledgement
signal from slower I/O
devices or memory.
It
When
When
low, then
microprocessor is in wait
state.
www.eazynotes.com
11
It
is a system reset.
It
When
high,
microprocessor enters into
reset state and terminates
the current activity.
It
12
It
is an interrupt request
signal.
It
is active high.
It
is level triggered.
www.eazynotes.com
13
It
is a non-maskable
interrupt signal.
It
is an active high.
It
is an edge triggered
interrupt.
www.eazynotes.com
14
It
The
If
15
This
It
is symmetric square
wave with 33% duty cycle.
The
range of frequency of
different versions is 5
MHz, 8 MHz and 10 MHz.
www.eazynotes.com
16
VCC
+5V
DC is supplied
through this pin.
VSS
is ground signal.
www.eazynotes.com
17
8086
Minimum Mode
Maximum Mode
If
If
www.eazynotes.com
18
Pins
24 to 31 issue two
different sets of signals.
One
Other
set of signals is
issued when CPU operates
in maximum mode.
www.eazynotes.com
19
www.eazynotes.com
20
This
is an interrupt
acknowledge signal.
When
microprocessor
receives INTR signal, it
acknowledges the
interrupt by generating
this signal.
It
21
This
is an Address Latch
Enable signal.
It
It
It
22
This
is a Data Enable
signal.
This
signal is used to
enable the transceiver
8286.
Transceiver
is used to
separate the data from the
address/data bus.
It
23
This
is a Data
Transmit/Receive signal.
It
When
it is high, data is
transmitted out.
When
it is low, data is
received in.
www.eazynotes.com
24
This
When
it is high, memory is
accessed.
When
25
It
is a Write signal.
It
It
www.eazynotes.com
26
It
is a Hold Acknowledge
signal.
It
It
www.eazynotes.com
27
When
DMA controller
needs to use address/data
bus, it sends a request to
the CPU through this pin.
It
When
microprocessor
receives HOLD signal, it
issues HLDA signal to the
DMA controller.
www.eazynotes.com
28
www.eazynotes.com
29
These
QS1
QS0
Status
No operation
Empty queue
www.eazynotes.com
30
These
status signals
indicate the operation
being done by the
microprocessor.
This
information is
required by the Bus
Controller 8288.
Bus
controller 8288
generates all memory and
I/O control signals.
www.eazynotes.com
31
S2
S1
S0
Status
Interrupt Acknowledge
I/O Read
I/O Write
Halt
Opcode Fetch
Memory Read
Memory Write
Passive
www.eazynotes.com
32
This
When
This
33
These
pins.
are Request/Grant
Other
After
RQ/GT0
than RQ/GT1.
www.eazynotes.com
34
www.eazynotes.com
35