Total No. of Questions : 8] SEAT No.

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P1537 [Total No. of Pages : 2

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LOGIC DESIGN & COMPUTER ORGANIZATION

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(2019 Pattern) (Semester - III) (214442)

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Time : 2½ Hours] [Max. Marks : 70

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Instructions to the candidates:
1) Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8.
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2) Neat diagrams must be drawn wherever necessary.
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3) Figures to the right indicate full marks.

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Q1) a) Define the following terms. [8]
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i) Propagation Delay Time
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ii) Setup Time
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iii) Hold Time

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iv) Maximum Clock Frequency

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b) Draw and explain SR flip-flop using NAND gate. [6]

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c) Convert T flip-flop to D flip-flop. [4]

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Q2) a) Design MOD-45 counter using IC 7490. [8]

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b) Draw and explain 4-bit serial-in serial-out shift register using D-FFs. [6]
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c) Differentiate between Latch and Flip Flop. [4]

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Q3) a) Draw and explain Single bus organization of CPU? State functions of
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CPU? [8]
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b) Explain sequence of events that occur in Fetch cycle symbolically with

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diagram at each stage. [9]

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Q4) a) Draw the block diagram of Hardwired control unit. [8]

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b) Describe the functions of registers: IR, MBR, MAR, PC, Flag register.[9]

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Q5) a) What are key characteristics of RISC & CISC. Compare RISC and

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CISC. [9]

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b) What is mean by Instruction format? Explain 0-1-2-3 address formats

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with suitable example? [9]
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Q6) a) Draw and explain Cluster and Cluster Architectures. [9]

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b) Explain symmetric multiprocessors(SMP) organization with features.[9]
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Q7) a) What are the different algorithms and techniques used in managing cache

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memory. [8]
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b) Explain Interrupt Driven I/O with a diagram. [9]

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Q8) a) Draw & explain memory hierarchy structure? What is mean by a Principle
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of Locality. [9]
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b) Explain the memory write cycle with help of suitable timing diagram.[8]
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