Total No. of Questions : 8] SEAT No.

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PB3652 [6261]-60
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LOGIC DESIGN & COMPUTER ORGANIZATION

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(2019 Pattern) (Semester-III) (214442)

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Time : 2½ Hours] [Max. Marks : 70

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Instructions to the candidates:
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1) Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8.
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2) Figures to the right indicates full marks.
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3) Assume suitable data if necessary.

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Q1) a) Differentiate between combinational Circuit and Sequential Circuit. [6]
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b) Explain in detail the Conversion of D flip-flop to T flip-flop. [6]

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c) Define Register. Explain various types of shift registers. [5]
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Q2) a) Draw the pin Configuration of IC 7476 and explain the function of
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Present and Clear pins. [6]
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b) What is meant by race around condition? How race around condition

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can be eliminated? [6]

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c) Define Modulus of Counter. Design MOD-81 counter using Decade

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Counter IC 7490. [5]

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Q3) a) Explain following terms in brief i) ALU Signals ii) ALU Functions ic-
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iii) ALU Types. [6]
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b) What are the uses of Registers in a CPU? List typical Registers in a

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CPU. Write a short note on Flag register. [6]

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c) What are interrupts? Explain with diagram what steps are carried out
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when they are present. [6]

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Q4) a) Write in brief about the Fetch cycle with operations and microinstructions
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carried out? [6]

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b) Explain and Design basic structure of Von Neumann architecture. Write

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the difference between Harvard and Von Neumann architecture. [6]

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c) Write a short note on following - Address Bus, Data Bus, Control Bus.[6]
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[6261]-60 1 P.T.O.
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Q5) a) What is mean by Machine Instruction? Explain basic format of Machine

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instruction? What are the basic types of machine instructions? [6]

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b) What is meant by Multicore architecture? List the typical features of

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multicore intel core i7. [6]

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c) What is purpose of Interrupt? What are various types of Interrupts? [5]

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Q6) a) Explain interrupt handling. [6]

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b) Give the Taxonomy of Parallel Processor Architectures, with one line

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explanation of each type. [6]

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c) Identify the addressing mode in following instructions: [5]

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i) MOV R1, #0A2DH
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ii) MOV R1,R2
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` iii) MOV R1, [R2]

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Q7) a) Along with suitable diagram explain direct cache mapping technique.[6]
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b) What is DMA? Along with suitable diagram explain how DMA is used
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for data transfer. [6]

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c) Explain memory read cycle with timing diagram. [6]

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Q8) a) Compare : SRAM and DRAM. [6]

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b) Explain Cache Coherence. [6]

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c) Whta is Principle of Locality? Explain two types of Localities. [6]

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[6261]-60 2
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