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7 lpc2103 ADC

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7 lpc2103 ADC

Uploaded by

Khải Nguyễn
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© © All Rights Reserved
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4.4.

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(datasheet LPC2103)
+ ADC
+
Analog to Digital Converter (ADC)
LPC2103 ADC. Control reg.
AD0CR (R/W)
• Bits [7:0] SEL: Channel select mask. 1 bit per enabled
input. Example: 00000101 enables conversions on AD0
and AD2. Selected channels are converted sequentially
• Bits [15:8] CLKDIV: PCLK frequency is divided by
(CLKDIV+1) to obtain the ADC clock frequency. This
frequency must be less than 4.5MHz.
• Bit 16 BURST: Enables repeated conversions if set to 1:
The ADC is triggered again after each conversion is
complete. Single conversion if 0.
LPC2103 ADC. Control reg.
AD0CR (R/W)
• Bits [19:17] CLKS: Clock cycles per conversion / ADC
resolution
value Clocks resolution
000 11 10-bit
001 10 9-bit
010 9 8-bit
011 8 7-bit
100 7 6-bit
101 6 5-bit
110 5 4-bit
111 4 3-bit
LPC2103 ADC. Control reg.
AD0CR (R/W)
• Bit 21 PDN:
– Bit 1: The ADC is operational.
– Bit 0: The ADC is in power-down mode
• Bits [26:24] START: Select the event to trigger the
conversions
• Bit 27 EDGE:
– Start conversions on: 1 – Falling edge. 0 – Rising Edge
value Trigger source value Trigger source
000 No start (used with burst mode) 100 Start on edge on MAT0.1
001 Start conversion now 101 Start on edge on MAT0.3
010 Start on edge on P0.16 110 Start on edge on MAT1.0
011 Start on edge on P0.22 111 Start on edge on MAT1.1
LPC2103ADC
• Global DATA reg. AD0GDR (R/W)
– Bits [5:0] Reserved
– Bits [15:6] RESULT: The value of the last converted
channel is stored in this field
– Bits [26:24] CHN: Number of the last channel
converted
– Bit 30 OVERRUN: 1: Data lost in burst mode. Cleared
automatically when reading AD0GDR
– Bit 31 DONE: Set to 1 when an ADC conversion
completes. Cleared after AD0GDR is read and after
AD0CR is written.
LPC2103ADC
• Individual DATA registers AD0DRx (R/0)
– Bits [5:0] Reserved
– Bits [15:6] RESULT: The value of the last conversion
for this channel is stored in this field
– Bit 30 OVERRUN: 1: Data lost in burst mode. Cleared
automatically when reading AD0DRx
– Bit 31 DONE: Set to 1 when an ADC conversion
completes. Cleared after AD0DRx is read
LPC2103ADC
• Status reg. AD0STAT (Read Only)
– Bits [7:0] DONE7 – DONE0: Individual DONE flags
(one per channel)
– BITS [15:8] OVERRUN7 – OVERRUN0: Individual
OVERRUN Flags
– BIT 16 ADINT: Interrupt flag. Set when a conversion
completes in an interrupt-enabled channel (DONE=1).
Cleared along with DONE.
• Interrupt Enable register AD0INTEN (R/W)
– Bits [7:0] ADINTEN7 – ADINTEN0: Interrupt enable
bits. If 1 the corresponding channel will generate an
interrupt when its conversion completes.
LPC2103 ADC. Usage notes
• The AVdd and AGND pins must be connected to an
accurate 3.3V power supply. There is no Vref pin.
Therefore the ADC reference is AVdd (3.3V)
• The selected channels are scanned sequentially. The
resulting sampling rate is then:
Fsamp=Fpclk/(CLKDIV+1)/(Nbit+1)/Nch,
– where Nbit is the selected resolution and Nch is the number of
selected channels.
ADC Procedure
• Configure ADC pin(s)
• Configure ADCR register:
– Select channel
– Select Fadc clock = Fpclk/(CLKDIV+1)
– -> CLKDIV = (Fpclk/Fadc) – 1 = (15 Mhz/ 1 Mhz) – 1 = 14
– Select ADC resolution (10 bits as default)
– Enable ADC
• Stimulate the ADC convert
• Waiting for the convert
• Return the result
Examples
• Use ADC with the AD0.1 input. 6bit results are
display on 6 leds from p0.5-p0.0

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