Dual Ultrafast

Voltage Comparator
ADCMP566
FEATURES FUNCTIONAL BLOCK DIAGRAM
250 ps propagation delay input to output
50 ps propagation delay dispersion
NONINVERTING
Differential ECL compatible outputs INPUT Q OUTPUT

Differential latch control ADCMP566

INVERTING Q OUTPUT
Robust input protection INPUT

Input common-mode range −2.0 V to +3.0 V

LATCH ENABLE LATCH ENABLE
Input differential range ±5 V INPUT INPUT
ESD protection >3 kV HBM, >200 V MM 03633-0-001

Power supply sensitivity > 65 dB Figure 1.

200 ps minimum pulsewidth
5 GHz equivalent input rise time bandwidth
Typical output rise/fall of 165 ps GENERAL DESCRIPTION
The ADCMP566 is an ultrafast voltage comparator fabricated
APPLICATIONS on Analog Devices’ proprietary XFCB process. The device
High speed instrumentation features 250 ps propagation delay with less than 35 ps overdrive
Scope and logic analyzer front ends dispersion. Overdrive dispersion, a particularly important
Window comparators characteristic of high speed comparators, is a measure of the
High speed line receivers and signal restoration difference in propagation delay under differing overdrive
Threshold detection conditions.
Peak detection
A fast, high precision differential input stage permits consis-
High speed triggers tent propagation delay with a wide variety of signals in the
Patient diagnostics common-mode range from −2.0 V to +3.0 V. Outputs are
Disk drive read channel detection complementary digital signals fully compatible with ECL 10 K
Hand-held test instruments and 10 KH logic families. The outputs provide sufficient drive
Zero-crossing detectors current to directly drive transmission lines terminated in 50 Ω
Clock drivers to −2 V. A latch input is included, which permits tracking,
Automatic test equipment track-and-hold, or sample-and-hold modes of operation.

The ADCMP566 is available in a 32-lead LFCSP package.

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com
registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
ADCMP566

TABLE OF CONTENTS
Specifications..................................................................................... 3 Optimizing High Speed Performance ........................................9

Absolute Maximum Ratings............................................................ 5 Comparator Propagation Delay Dispersion ..............................9

Thermal Considerations.............................................................. 5 Comparator Hysteresis .............................................................. 10

ESD Caution.................................................................................. 5 Minimum Input Slew Rate Requirement ................................ 10

Pin Configuration and Function Descriptions............................. 6 Typical Application Circuits ..................................................... 11

Timing Information ......................................................................... 8 Typical Performance Characteristics ........................................... 12

Application Information.................................................................. 9 Outline Dimensions ....................................................................... 14

Clock Timing Recovery ............................................................... 9 Ordering Guide .......................................................................... 14

REVISION HISTORY
Revision 0: Initial Version

Rev. 0 | Page 2 of 16
 ADCMP566

SPECIFICATIONS
Table 1. ADCMP566 ELECTRICAL CHARACTERISTICS (VCC = +5.0 V, VEE = −5.2 V, TA = 25°C, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
DC INPUT CHARACTERISTICS (See Note)
Input Common-Mode Range VCM −2.0 +3.0 V
Input Differential Voltage −5 +5 V
Input Offset Voltage VOS −5.0 ±1.0 +5.0 mV
Input Offset Voltage Channel Matching ±1.0 mV
Offset Voltage Tempco DVOS/dT 10.0 µV/°C
Input Bias Current IBC −10 +24 +42 µA
Input Bias Current Tempco 10.0 nA/°C
Input Offset Current −8.0 ±0.5 +8.0 µA
Input Capacitance CIN 0.75 pF
Input Resistance, Differential Mode 100 kΩ
Input Resistance, Common Mode 600 kΩ
Open Loop Gain 60 dB
Common-Mode Rejection Ratio CMRR VCM = −2.0 V to +3.0 V 69 dB
Hysteresis ±1.0 mV
LATCH ENABLE CHARACTERISTICS
Latch Enable Common-Mode Range VLCM −2.0 0 V
Latch Enable Differential Input Voltage VLD 0.4 2.0 V
Input High Current @ 0.0 V −12 +6 +12 µA
Input Low Current @ −2.0 V −12 +6 +12 µA
Latch Setup Time tS 250 mV overdrive 50 ps
Latch to Output Delay tPLOH, tPLOL 250 mV overdrive 250 ps
Latch Pulsewidth tPL 250 mV overdrive 150 ps
Latch Hold Time tH 250 mV overdrive 75 ps
OUTPUT CHARACTERISTICS
Output Voltage—High Level VOH ECL 50 Ω to −2.0 V −1.06 −0.81 V
Output Voltage—Low Level VOL ECL 50 Ω to −2.0 V −1.95 −1.65 V
Rise Time tR 20% to 80% 170 ps
Fall Time tF 20% to 80% 140 ps
AC PERFORMANCE
Propagation Delay tPD 1 V overdrive 240 ps
Propagation Delay tPD 20 mV overdrive 290 ps
Propagation Delay Tempco 0.5 ps/°C
Prop Delay Skew—Rising Transition to ±10 ps
Falling Transition
Within Device Propagation Delay Skew— ±10 ps
Channel to Channel
Propagation Delay Dispersion vs. 1 MHz, 1 ns tR, tF ±10 ps
Duty Cycle
Propagation Delay Dispersion vs. 50 mV to 1.5 V 35 ps
Overdrive
Propagation Delay Dispersion vs. 20 mV to 1.5 V 50 ps
Overdrive
Propagation Delay Dispersion vs. 0 V to 1 V swing, 50 ps
Slew Rate 20% to 80%,
50 and 600 ps tR, tF
Propagation Delay Dispersion vs. 1 V swing, 5 ps
Common-Mode Voltage −1.5 V to 2.5 VCM
Equivalent Input Rise Time Bandwidth BW 0 V to 1 V swing, 5000 MHz
20% to 80%,
50 ps tR, tF

Rev. 0 | Page 3 of 16
ADCMP566

Parameter Symbol Condition Min Typ Max Unit

AC PERFORMANCE (continued)
Toggle Rate >50% output swing 5 Gbps
Minimum Pulsewidth PW ∆tpd from 10 ns to 200 ps
200 ps < ±25 ps
Unit to Unit Propagation Delay Skew ±10 ps
POWER SUPPLY
Positive Supply Current IVCC @ +5.0 V 9 13 18 mA
Negative Supply Current IVEE @ −5.2 V 60 70 85 mA
Positive Supply Voltage VCC Dual 4.75 5.0 5.25 V
Negative Supply Voltage VEE Dual −4.96 −5.2 −5.45 V
Power Dissipation Dual, without load 375 450 525 mW
Power Dissipation Dual, with load 550 mW
Power Supply Sensitivity—VCC PSSVCC 68 dB
Power Supply Sensitivity—VEE PSSVEE 85 dB

NOTE: Under no circumstances should the input voltages exceed the supply voltages.

Rev. 0 | Page 4 of 16
 ADCMP566

ABSOLUTE MAXIMUM RATINGS

Table 2. ADCMP566 Absolute Maximum Ratings THERMAL CONSIDERATIONS
Parameter Rating
The ADCMP566 LFCSP 32-lead package option has a θJA
Supply Positive Supply Voltage −0.5 V to +6.0 V
Voltages (VCC to GND) (junction-to-ambient thermal resistance) of 27.2°C/W in
Negative Supply Voltage −6.0 V to +0.5 V
still air.
(VEE to GND)
Ground Voltage Differential −0.5 V to +0.5 V
Input Input Common-Mode −3.0 V to +4.0 V
Voltages Voltage
Differential Input Voltage −7.0 V to +7.0 V
Input Voltage, VEE to 0.5 V
Latch Controls
Output Output Current 30 mA
Temperature Operating Temperature, −40°C to +85°C
Ambient
Operating Temperature, 125°C
Junction
Storage Temperature Range −65°C to +150°C

Stress above those listed under Absolute Maximum Ratings may

cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 16
ADCMP566

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND

GND

GND
LEA
LEA

QA
QA
NC
32
31
30
29
28
27
26
25
GND 1 24 VEE
PIN 1
–INA 2 23 NC
INDICATOR
+INA 3 22 VEE
VCC 4 ADCMP566 21 VCC
VCC 5 TOP VIEW 20 VCC
+INB 6 19 VEE
(Not to Scale)
–INB 7 18 NC
GND 8 17 VEE

9
10
11
12
13
14
15
16
GND
LEB
LEB
NC
GND
QB
QB
GND
NC = NO CONNECT

03633-0-002

Figure 2. ADCMP566 Pin Configuration

Table 3. ADCMP566 Pin Descriptions

Pin No. Mnemonic Function
1 GND Analog Ground
2 −INA Inverting analog input of the differential input stage for Channel A. The inverting A input must be driven
in conjunction with the noninverting A input.
3 +INA Noninverting analog input of the differential input stage for Channel A. The noninverting A input must
be driven in conjunction with the inverting A input.
4 VCC Positive Supply Terminal
5 VCC Positive Supply Terminal
6 +INB Noninverting analog input of the differential input stage for Channel B. The noninverting B input must
be driven in conjunction with the inverting B input.
7 −INB Inverting analog input of the differential input stage for Channel B. The inverting B input must be driven
in conjunction with the noninverting B input.
8 GND Analog Ground
9 GND Analog Ground
10 LEB One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic low), the
output will track changes at the input of the comparator. In the latch mode (logic high), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven
in conjunction with LEB.
11 LEB One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic high), the
output will track changes at the input of the comparator. In the latch mode (logic low), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven
in conjunction with LEB.
12 NC No Connect. Leave pin unconnected.
13 GND Digital Ground
14 QB One of two complementary outputs for Channel B. QB will be at logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEB description (Pin 11) for more information.
15 QB One of two complementary outputs for Channel B. QB will be at logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEB description (Pin 11) for more information.
16 GND Digital Ground
17 VEE Negative Supply Terminal
18 NC No Connect. Leave pin unconnected.
19 VEE Negative Supply Terminal
20 VCC Positive Supply Terminal
21 VCC Positive Supply Terminal

Rev. 0 | Page 6 of 16
 ADCMP566
Pin No. Mnemonic Function
22 VEE Negative Supply Terminal
23 NC No Connect. Leave pin unconnected.
24 VEE Negative Supply Terminal
25 GND Digital Ground
26 QA One of two complementary outputs for Channel A. QA will be at logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEA description (Pin 30) for more information.
27 QA One of two complementary outputs for Channel A. QA will be at logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEA description (Pin 30) for more information.
28 GND Digital Ground
29 NC No Connect. Leave pin unconnected.
30 LEA One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic high), the
output will track changes at the input of the comparator. In the latch mode (logic low), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven
in conjunction with LEA.
31 LEA One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic low), the
output will track changes at the input of the comparator. In the latch mode (logic high), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven
in conjunction with LEA.
32 GND Analog Ground

Rev. 0 | Page 7 of 16
ADCMP566

TIMING INFORMATION
LATCH ENABLE
50%
LATCH ENABLE

tS tPL

tH

DIFFERENTIAL VIN
VREF ± VOS
INPUT VOLTAGE VOD

tPDL tPLOH

Q OUTPUT
50%

tF
tPDH

50%
Q OUTPUT
tPLOL

tR
03633-0-003

Figure 3. System Timing Diagram

The timing diagram in Figure 3 shows the ADCMP566 compare Symbol Timing Description
and latch features. Table 4 describes the terms in the diagram. tH Minimum Minimum time after the negative
hold time transition of the Latch Enable
Table 4. Timing Descriptions signal that the input signal must
Symbol Timing Description remain unchanged to be acquired
and held at the outputs
tPDH Input to output Propagation delay measured from
high delay the time the input signal crosses tPL Minimum Minimum time that the Latch
the reference (± the input offset latch enable Enable signal must be high to
voltage) to the 50% point of an pulsewidth acquire an input signal change
output low-to-high transition tS Minimum Minimum time before the
tPDL Input to output Propagation delay measured from setup time negative transition of the Latch
low delay the time the input signal crosses Enable signal that an input signal
the reference (± the input offset change must be present to be
voltage) to the 50% point of an acquired and held at the outputs
output high-to-low transition tR Output rise Amount of time required to
tPLOH Latch enable Propagation delay measured from time transition from a low to a high
to output high the 50% point of the Latch Enable output as measured at the 20%
delay signal low-to-high transition to and 80% points
the 50% point of an output low- tF Output fall Amount of time required to
to-high transition time transition from a high to a low
tPLOL Latch enable Propagation delay measured from output as measured at the 20%
to output low the 50% point of the Latch Enable and 80% points
delay signal low-to-high transition to VOD Voltage Difference between the
the 50% point of an output high- overdrive differential input and reference
to-low transition input voltages

Rev. 0 | Page 8 of 16
 ADCMP566

APPLICATION INFORMATION
The ADCMP566 comparators are very high speed devices. CLOCK TIMING RECOVERY
Consequently, high speed design techniques must be employed Comparators are often used in digital systems to recover clock
to achieve the best performance. The most critical aspect of any timing signals. High speed square waves transmitted over a
ADCMP566 design is the use of a low impedance ground plane. distance, even tens of centimeters, can become distorted due to
A ground plane, as part of a multilayer board, is recommended stray capacitance and inductance. Poor layout or improper
for proper high speed performance. Using a continuous termination can also cause reflections on the transmission line,
conductive plane over the surface of the circuit board can create further distorting the signal waveform. A high speed
this, allowing breaks in the plane only for necessary signal comparator can be used to recover the distorted waveform
paths. The ground plane provides a low inductance ground, while maintaining a minimum of delay.
eliminating any potential differences at different ground points
throughout the circuit board caused by ground bounce. A OPTIMIZING HIGH SPEED PERFORMANCE
proper ground plane also minimizes the effects of stray As with any high speed comparator amplifier, proper design and
capacitance on the circuit board. layout techniques should be used to ensure optimal perform-
ance from the ADCMP566. The performance limits of high
It is also important to provide bypass capacitors for the power
speed circuitry can easily be a result of stray capacitance,
supply in a high speed application. A 1µF electrolytic bypass
improper ground impedance, or other layout issues.
capacitor should be placed within 0.5 inches of each power
supply pin to ground. These capacitors will reduce any potential Minimizing resistance from source to the input is an important
voltage ripples from the power supply. In addition, a 10 nF consideration in maximizing the high speed operation of the
ceramic capacitor should be placed as close as possible from the ADCMP566. Source resistance in combination with equivalent
power supply pins on the ADCMP566 to ground. These input capacitance could cause a lagged response at the input,
capacitors act as a charge reservoir for the device during high thus delaying the output. The input capacitance of the
frequency switching. ADCMP566 in combination with stray capacitance from an
input pin to ground could result in several picofarads of
The LATCH ENABLE input is active low (latched). If the
equivalent capacitance. A combination of 3 kΩ source resistance
latching function is not used, the LATCH ENABLE input
and 5 pF of input capacitance yields a time constant of 15 ns,
should be grounded (ground is an ECL logic high), and the
which is significantly slower than the sub 500 ps capability of
complementary input, LATCH ENABLE, should be tied to
the ADCMP566. Source impedances should be significantly less
−2.0 V. This will disable the latching function.
than 100 Ω for best performance.
Occasionally, one of the two comparator stages within the
Sockets should be avoided due to stray capacitance and induc-
ADCMP566 will not be used. The inputs of the unused
tance. If proper high speed techniques are used, the ADCMP566
comparator should not be allowed to float. The high internal
should be free from oscillation when the comparator input
gain may cause the output to oscillate (possibly affecting the
signal passes through the switching threshold.
comparator that is being used) unless the output is forced into a
fixed state. This is easily accomplished by ensuring that the two COMPARATOR PROPAGATION
inputs are at least one diode drop apart, while also appropriately DELAY DISPERSION
connecting the LATCH ENABLE and LATCH ENABLE inputs
The ADCMP566 has been specifically designed to reduce
as described above.
propagation delay dispersion over an input overdrive range of
The best performance is achieved with the use of proper ECL 100 mV to 1 V. Propagation delay overdrive dispersion is the
terminations. The open emitter outputs of the ADCMP566 are change in propagation delay that results from a change in the
designed to be terminated through 50 Ω resistors to −2.0 V, or degree of overdrive (how far the switching point is exceeded by
any other equivalent ECL termination. If a −2.0 V supply is not the input). The overall result is a higher degree of timing
available, an 82 Ω resistor to ground and a 130 Ω resistor to accuracy since the ADCMP566 is far less sensitive to input
−5.2 V provide a suitable equivalent. If high speed ECL signals variations than most comparator designs.
must be routed more than a centimeter, microstrip or stripline
Propagation delay dispersion is a specification that is important
techniques may be required to ensure proper transition times
in critical timing applications such as ATE, bench instruments,
and prevent output ringing.
and nuclear instrumentation. Overdrive dispersion is defined

Rev. 0 | Page 9 of 16
ADCMP566
as the variation in propagation delay as the input overdrive –VH +VH
conditions are changed (Figure 4). For the ADCMP566, 2 2
0V
overdrive dispersion is typically 35 ps as the overdrive is INPUT
changed from 100 mV to 1 V. This specification applies for
1
both positive and negative overdrive since the ADCMP566 has
equal delays for positive and negative going inputs.

The 35 ps propagation delay overdrive dispersion of the

ADCMP566 offers considerable improvement of the 100 ps
dispersion of other similar series comparators.
0
1.5V OVERDRIVE

INPUT VOLTAGE OUTPUT

20mV OVERDRIVE
03633-0-005
VREF ± VOS Figure 5. Comparator Hysteresis Transfer Function

DISPERSION 60

Q OUTPUT
50
03633-0-004

Figure 4. Propagation Delay Dispersion

40
HYSTERESIS (mV)

COMPARATOR HYSTERESIS 30

The addition of hysteresis to a comparator is often useful in a

noisy environment or where it is not desirable for the compara- 20

tor to toggle between states when the input signal is at the

switching threshold. The transfer function for a comparator 10

with hysteresis is shown in Figure 5. If the input voltage

03633-0-006
0
approaches the threshold from the negative direction, the –20 –15 –10 –5 0 5 10 15
comparator will switch from a 0 to a 1 when the input crosses ∆ LATCH = LE – LEB (mV)

+VH/2. The new switching threshold becomes −VH/2. The Figure 6. Comparator Hysteresis Transfer Function
comparator will remain in a 1 state until the threshold −VH/2 is Using Latch Enable Input
crossed coming from the positive direction. In this manner,
noise centered on 0 V input will not cause the comparator to
MINIMUM INPUT SLEW RATE REQUIREMENT
switch states unless it exceeds the region bounded by ±VH/2.
As for all high speed comparators, a minimum slew rate must
Positive feedback from the output to the input is often used to be met to ensure that the device does not oscillate when the
produce hysteresis in a comparator (Figure 9). The major input crosses the threshold. This oscillation is due in part to the
problem with this approach is that the amount of hysteresis high input bandwidth of the comparator and the parasitics of
varies with the output logic levels, resulting in a hysteresis that the package. Analog Devices recommends a slew rate of 5 V/µs
is not symmetrical around zero. or faster to ensure a clean output transition. If slew rates less
than 5 V/µs are used, then hysteresis should be added to reduce
Another method to implement hysteresis is generated by
the oscillation.
introducing a differential voltage between LATCH ENABLE
and LATCH ENABLE. inputs (Figure 10). Hysteresis generated
in this manner is independent of output swing and is symmetri-
cal around zero. The variation of hysteresis with input voltage is
shown in Figure 6.

Rev. 0 | Page 10 of 16
 ADCMP566
TYPICAL APPLICATION CIRCUITS

VIN
VIN ADCMP566 OUTPUTS
ADCMP566 OUTPUTS
VREF

LATCH HYSTERESIS 450Ω –2.0V

–2.0V
ENABLE VOLTAGE
INPUTS
ALL RESISTORS 50Ω
ALL RESISTORS 50Ω UNLESS OTHERWISE NOTED
03633-0-007
03633-0-010

Figure 7. High Speed Sampling Circuits Figure 10. Hysteresis Using Latch Enable Input

+VREF 30Ω 50Ω

ADCMP566 OUTPUTS VIN ADCMP566

VIN 30Ω 50Ω

127Ω 127Ω

–5.2V
03633-0-011

ADCMP566 Figure 11. How to Interface an ECL Output to an

–VREF
Instrument with a 50 Ω to Ground Input

LATCH –2.0V
ENABLE
INPUTS
ALL RESISTORS 50Ω

03633-0-008

Figure 8. High Speed Window Comparator

VIN
ADCMP566 OUTPUTS

VREF
R1 R2

–2.0V

ALL RESISTORS 50Ω

03633-0-009

Figure 9. Hysteresis Using Positive Feedback

Rev. 0 | Page 11 of 16
ADCMP566

TYPICAL PERFORMANCE CHARACTERISTICS

(VCC = +5.0 V, VEE = −5.2 V, TA = 25°C, unless otherwise noted.)
30
23.4

25 23.2

+IN INPUT BIAS CURRENT (µA)

INPUT BIAS CURRENT (µA)

20 23.0

(+IN = 1V, –IN = 0V)

22.8
15
22.6

10
22.4

5 22.2

03633-0-016
0 03633-0-013 22.0
–2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 –40 –20 0 20 40 60 80
NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0.5V) TEMPERATURE (°C)
Figure 15. Input Bias Current vs. Temperature
Figure 12. Input Bias Current vs. Input Voltage

60
2.0

1.8 50
1.6

1.4 40
OFFSET VOLTAGE (mV)

HYSTERESIS (mV)

1.2
30
1.0

0.8 20
0.6

0.4 10

0.2

03633-0-017
0
03633-0-014

0 –20 –15 –10 –5 0 5 10 15

–40 –20 0 20 40 60 80 ∆ LATCH = LE – LEB (mV)
TEMPERATURE (°C)
Figure 13. Input Offset Voltage vs. Temperature Figure 16. Hysteresis vs. ∆Latch

195
195

185
185

175
175
TIME (ps)

165
TIME (ps)

165

155
155

145
145

135
135
03633-0-018

125
03633-0-015

125 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. Rise Time vs. Temperature Figure 17. Fall Time vs. Temperature

Rev. 0 | Page 12 of 16
 ADCMP566

242 239

240 238

238 237
PROPAGATION DELAY (ps)

PROPAGATION DELAY (ps)

236 236

234 235

232 234

230 233

228 232

03633-0-022
03633-0-019
226 231
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 –2 –1 0 1 2 3
TEMPERATURE (°C) INPUT COMMON-MODE VOLTAGE (V)
Figure 18. Propagation Delay vs. Temperature Figure 21. Propagation Delay vs. Common-Mode Voltage

60 0

–5
50
PROPAGATION DELAY ERROR (ps)

PROPAGATION DELAY ERROR (ps)

–10
40
–15

30 –20

–25
20
–30
10
–35
03633-0-020

03633-0-023
0 –40
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.15 2.15 4.15 6.15 8.15
OVERDRIVE VOLTAGE (V) PULSEWIDTH (ns)
Figure 19. Propagation Delay Error vs. Overdrive Voltage Figure 22. Propagation Delay Error vs. Pulsewidth

–0.8

–1.0
OUTPUT RISE AND FALL (V)

–1.2

–1.4

–1.6

–1.8
03633-0-021

–2.0
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
TIME (ns)
Figure 20. Rise and Fall of Outputs vs. Time

Rev. 0 | Page 13 of 16
ADCMP566

OUTLINE DIMENSIONS
5.00 0.60 MAX
BSC SQ 0.60 MAX PIN 1
INDICATOR
25 32 1
24
PIN 1
INDICATOR 0.50
4.75 BSC 3.25
TOP BOTTOM
VIEW BSC SQ VIEW 2.70 SQ
1.25
0.50
0.40 17
16 8
9
0.30

0.80 MAX 3.50

12° MAX REF
0.65 NOM
0.05 MAX
1.00 0.02 NOM
0.90 0.30
0.80 0.20 REF COPLANARITY
0.23 0.08
SEATING 0.18
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 23. 32-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-32)
Dimensions shown in millimeters

ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADCMP566BCP −40°C to +85°C LFCSP-32 CP-32

Rev. 0 | Page 14 of 16
 ADCMP566

Notes

Rev. 0 | Page 15 of 16
ADCMP566

Notes

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
C03633–0–10/03(0)

Rev. 0 | Page 16 of 16