SEMICONDUCTOR TECHNICAL DATA

  
 !   !
 
High–Performance Silicon–Gate CMOS J SUFFIX
CERAMIC PACKAGE
The MC54/74HC259 is identical in pinout to the LS259. The device inputs 16 CASE 620–10
are compatible with standard CMOS outputs; with pullup resistors, they are 1
compatible with LSTTL outputs.
The HC259 has four modes of operation as shown in the mode selection N SUFFIX
table. In the addressable latch mode, the data on Data In is written into the PLASTIC PACKAGE
16
addressed latch. The addressed latch follows the data input with all CASE 648–08
non–addressed latches remaining in their previous states. In the memory 1
mode, all latches remain in their previous state and are unaffected by the
Data or Address inputs. In the one–of–eight decoding or demultiplexing D SUFFIX
16 SOIC PACKAGE
mode, the addressed output follows the state of Data In with all other outputs
1 CASE 751B–05
in the LOW state. In the Reset mode all outputs are LOW and unaffected by
the address and data inputs. When operating the HC259 as an addressable ORDERING INFORMATION
latch, changing more than one bit of the address could impose a transient
MC54HCXXXJ Ceramic
wrong address. Therefore, this should only be done while in the memory
MC74HCXXXN Plastic
mode.
MC74HCXXXD SOIC
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
PIN ASSIGNMENT
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices A0 1 16 VCC
• In Compliance with the Requirements Defined by JEDEC Standard A1 2 15 RESET
No. 7A
A2 3 14 ENABLE
• Chip Complexity: 202 FETs or 50.5 Equivalent Gates
Q0 4 13 DATA IN
Q1 5 12 Q7
Q2 6 11 Q6
LOGIC DIAGRAM
Q3 7 10 Q5
GND 8 9 Q4
1 4
A0 Q0
ADDRESS 2 5
A1 Q1
INPUTS 3 6
A2 Q2 MODE SELECTION TABLE
7
Q3 NONINVERTING Enable Reset Mode
9 OUTPUTS
Q4
13 10 L H Addressable Latch
DATA IN Q5 H H Memory
11
Q6 L L 8–Line Demultiplexer
12
Q7 H L Reset
15
RESET LATCH SELECTION TABLE
14
ENABLE Address Inputs Latch
PIN 16 = VCC C B A Addressed
PIN 8 = GND L L L Q0
L L H Q1
L H L Q2
L H H Q3
H L L Q4
H L H Q5
H H L Q6
H H H Q7

10/95

 Motorola, Inc. 1995 1 REV 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC54/74HC259
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Value Unit This device contains protection

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
due to high static voltages or electric
Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 V fields. However, precautions must

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
voltage higher than maximum rated
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Iout DC Output Current, per Pin ± 25 mA cuit. For proper operation, Vin and

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vout should be constrained to the
ICC DC Supply Current, VCC and GND Pins ± 50 mA v
range GND (Vin or Vout) VCC. v
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic or Ceramic DIP† 750 mW

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tied to an appropriate logic voltage
SOIC Package† 500
level (e.g., either GND or VCC).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C Unused outputs must be left open.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds _C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Plastic DIP or SOIC Package) 260
(Ceramic DIP) 300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Ceramic DIP: – 10 mW/_C from 100_ to 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
VCC = 6.0 V 0 400

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC – 55 to
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIH
v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Voltage |Iout| 20 µA 4.5 3.15 3.15 3.15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.3 0.3 0.3 V
v
Voltage |Iout| 20 µA 4.5 0.9 0.9 0.9

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 1.2 1.2 1.2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
v
Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 6.0 5.9 5.9 5.9

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v
Vin = VIH or VIL |Iout| 4.0 mA 4.5 3.98 3.84 3.70

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
|Iout| 5.2 mA 6.0 5.48 5.34 5.20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
v
Voltage |Iout| 20 µA 4.5 0.1 0.1 0.1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1
v
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 4.0 mA 4.5 0.26 0.33 0.40
v
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
|Iout| 5.2 mA 6.0 0.26 0.33 0.40
± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 8 80 160 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Current (per Package) Iout = 0 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

MOTOROLA 2 High–Speed CMOS Logic Data

DL129 — Rev 6
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC54/74HC259

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Data to Output 2.0 185 230 280 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL (Figures 1 and 6) 4.5 37 46 56
6.0 31 39 48

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Address Select to Output 2.0 215 270 325 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL (Figures 2 and 6) 4.5 43 54 65

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 37 46 55

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Enable to Output 2.0 200 250 300 ns
tPHL (Figures 3 and 6) 4.5 40 50 60

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 34 43 51

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL Maximum Propagation Delay, Reset to Output 2.0 155 195 235 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figures 4 and 6) 4.5 31 39 47
6.0 26 33 40

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL (Figures 1 and 6) 4.5 15 19 22

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 13 16 19
Cin Maximum Input Capacitance — 10 10 10 pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)* 30 pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Motorola High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (Input tr = tf = 6 ns)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tsu Minimum Setup Time, Address or Data to Enable 2.0 100 125 150 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 5) 4.5 20 25 30
6.0 17 21 26

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
th Minimum Hold Time, Enable to Address or Data 2.0 5 5 5 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 5) 4.5 5 5 5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 5 5 5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Reset or Enable 2.0 80 100 120 ns
(Figure 3 or 4) 4.5 16 20 24

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 14 17 20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 1) 4.5 500 500 500
6.0 400 400 400
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

High–Speed CMOS Logic Data 3 MOTOROLA

DL129 — Rev 6
MC54/74HC259

SWITCHING WAVEFORMS

VCC
DATA IN
GND

VCC
50%
tr tf GND
ADDRESS
DATA IN VCC
90% SELECT
50% VCC
10% GND 50%
tPLH tPHL GND
90% tPHL tPLH
50%
OUTPUT Q 10%
OUTPUT Q 50%
tTLH tTHL

Figure 1. Figure 2.

VCC
VCC
DATA IN
GND DATA IN
tw tw GND
tw
VCC VCC
ENABLE 50% 50% 50% RESET 50%
GND GND
tPHL tPLH
tPHL

OUTPUT Q OUTPUT Q 50%

Figure 3. Figure 4.

TEST POINT

DATA IN VCC OUTPUT

OR 50% DEVICE
ADDRESS GND UNDER
th(H) th(L) TEST CL*
SELECT
tsu tsu
VCC
ENABLE 50%
GND
* Includes all probe and jig capacitance

Figure 5. Figure 6. Test Circuit

MOTOROLA 4 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC259

EXPANDED LOGIC DIAGRAM

13 4
DATA INPUT D Q0

5
D Q1

6
D Q2

7
D Q3

A0

ADDRESS 3 TO 8
A1
INPUTS DECODER 9
D Q4
A2

10
D Q5
14
ENABLE

11
D Q6

12
D Q7

15
RESET

High–Speed CMOS Logic Data 5 MOTOROLA

DL129 — Rev 6
MC54/74HC259

OUTLINE DIMENSIONS

J SUFFIX
–A CERAMIC PACKAGE
– CASE 620–10
NOTES:
16 9 ISSUE V 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
–B 2. CONTROLLING DIMENSION: INCH.
– 3. DIMENSION L TO CENTER OF LEAD WHEN
1 8 FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
C L THE LEAD ENTERS THE CERAMIC BODY.

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
–T B 0.240 0.295 6.10 7.49
–
SEATING N K C — 0.200 — 5.08
PLANE D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
E M G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38
F G J 16 PL K 0.125 0.170 3.18 4.31
D 16 PL 0.25 (0.010) M T B S L 0.300 BSC 7.62 BSC
M 0° 15° 0° 15°
0.25 (0.010) M T A S N 0.020 0.040 0.51 1.01

N SUFFIX
–A PLASTIC PACKAGE NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
– CASE 648–08 Y14.5M, 1982.
ISSUE R 2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
F DIM MIN MAX MIN MAX
C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.070 1.02 1.77
–T PLANE G 0.100 BSC 2.54 BSC
– H 0.050 BSC 1.27 BSC
K M J
H J 0.008 0.015 0.21 0.38
G K 0.110 0.130 2.80 3.30
D 16 PL L 0.295 0.305 7.50 7.74
M 0° 10° 0° 10°
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

D SUFFIX
PLASTIC SOIC PACKAGE
–A CASE 751B–05
– ISSUE J NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B MOLD PROTRUSION.
P 8 PL 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
–
1 8 0.25 (0.010) M B M PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
G MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45° B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
–T
–
SEATING M J J 0.19 0.25 0.008 0.009
PLANE K 0.10 0.25 0.004 0.009
D 16 PL M 0° 7° 0° 7°
0.25 (0.010) M T B S A S P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

MOTOROLA 6 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC259

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*MC54/74HC259/D*
◊ CODELINE MC54/74HC259/D
High–Speed CMOS Logic Data 7 MOTOROLA
DL129 — Rev 6