DR3000

· Designed for Short-Range Wireless Data Communications

· Supports 2.4-19.2 kbps Encoded Data Transmissions
· 3 V, Low Current Operation plus Sleep Mode
· Ready to Use OEM Module
916.50 MHz
Transceiver
The DR3000 transceiver module is ideal for short-range wireless data applications where robust
operation, small size and low power consumption are required. The DR3000 utilizes RFM’s Module
TR1000 amplifier-sequenced hybrid (ASH) architecture to achieve this unique blend of charac-
teristics. The receiver section of the TR1000 is sensitive and stable. A wide dynamic range log
detector provides robust performance in the presence of on-channel interference or noise. Two
stages of SAW filtering provide excellent receiver out-of-band rejection. The transmitter includes
provisions for both on-off keyed (OOK) and amplitude-shift keyed (ASK) modulation. The trans-
mitter employs SAW filtering to suppress output harmonics, facilitating compliance with FCC
15.249 and similar regulations. The DR3000 includes the TR1000 plus all configuration compo-
nents in a ready-to-use PCB assembly, excellent for prototyping and intermediate volume pro-
duction runs.

Absolute Maximum Ratings

Rating Value Units

Power Supply and All Input/Output Pins -0.3 to +4.0 V
o
Non-Operating Case Temperature -50 to +100 C
o
Soldering Temperature (10 seconds) 230 C

Electrical Characteristics, 2.4 kbps On-Off Keyed

Characteristic Sym Notes Minimum Typical Maximum Units

Operating Frequency fO 916.30 916.70 MHz
Modulation Type OOK
Data Rate 2.4 kbps
Receiver Performance (OOK @ 2.4 kbps)
Input Current, 3 Vdc Supply IR 4.5 mA
-4
Input Signal for 10 BER, 25 °C -100 dBm
Rejection, ±30 MHz RREJ 55 dB
Transmitter Performance (OOK @ 2.4 kbps)
Peak Input Current, 3 Vdc Supply ITP 12 mA
Peak Output Power PO 0.75 mW
Turn On/Turn Off Time tON/tOFF 12/6 µs
Sleep to Receive Switch Time (100 ms sleep, -85 dBm signal) tSR 200 µs
Sleep Mode Current IS 0.75 µA
Transmit to Receive Switch Time (100 ms transmit, -85 dBm signal) tTOR 200 µs
Receive to Transmit Switch Time tRTO 12 µs
Power Supply Voltage Range VCC 2.7 3.5 Vdc
o
Operating Ambient Temperature TA -40 +85 C

1
 D R 3 0 0 0 S c h e m a tic
R F IO R F G N D
(1 3 ) (1 4 )

C 1
C T R 0 (1 2 )
C 6
C T R 1 (1 1 )
V C C (9 )

+ R 1 R 2
R 3
C 4 C 5
R 8

2 0 1 1
L 1

A S H T r a n s c e iv e r R 4

L 2
1 1 0

L P F A D J (8 )
C 3
R 5 R 6
C 2

G N D (6 , 7 , 1 0 )

R X B B O T X IN
(3 ) (5 )
A G C /V C C P K D E T R X D A T A
(1 ) (2 ) (4 )

D R 3 0 0 0 P in O u t D R 3 0 0 0 O u tlin e D r a w in g
R F .7 0
G N D R F IO .2 5 .2 0
1 4 1 3
.1 6 5
A G C /V C C 1 1 2 C T R 0
P K D E T 2 1 1 C T R 1 .1 0

R X B B O 3 1 0 G N D
.7 0
R X D A T A 4 9 V C C
T X IN 5 8 L P F A D J
6 7
G N D G N D

D im e n s io n s in in c h e s

2
Pin Descriptions

Pin Name Description

This pin is connected directly to the transceiver AGCCAP pin. To disable AGC operation, this pin is tied to VCC.
To enable AGC operation, a capacitor is placed between this pin and ground. This pin controls the AGC reset op-
eration. A capacitor between this pin and ground sets the minimum time the AGC will hold-in once it is engaged.
The hold-in time is set to avoid AGC chattering. For a given hold-in time tAGH, the capacitor value CAGC is:

CAGC = 19.1* tAGH, where tAGH is in µs and CAGC is in pF

A ±10% ceramic capacitor should be used at this pin. The value of CAGC given above provides a hold-in time be-
tween tAGH and 2.65* tAGH, depending on operating voltage, temperature, etc. The hold-in time is chosen to allow
1 AGC/VCC
the AGC to ride through the longest run of zero bits that can occur in a received data stream. The AGC hold-in
time can be greater than the peak detector decay time, as discussed below. However, the AGC hold-in time
should not be set too long, or the receiver will be slow in returning to full sensitivity once the AGC is engaged by
noise or interference. The use of AGC is optional when using OOK modulation with data pulses of at least 30 µs.
Active or latched AGC operation is required for ASK modulation and/or for data pulses of less than 30 µs. The
AGC can be latched ON once engaged by connecting a 150 K resistor between this pin and ground, instead of a
capacitor. AGC operation depends on a functioning peak detector, as discussed below. The AGC capacitor is dis-
charged in the transceiver power-down (sleep) mode and in the transmit modes. Note that provisions are made on
the circuit board to install a jumper between this pin and the junction of C2 and L3. Installing the jumper allows ei-
ther this pin or Pin 7 to be used for the Vcc supply when AGC operation is not required.

This pin is connected directly to the transceiver PKDET pin. This pin controls the peak detector operation. A ca-
pacitor between this pin and ground sets the peak detector attack and decay times, which have a fixed 1:1000 ra-
tio. For most applications, the attack time constant should be set to 6.4 ms with a 0.027 µF capacitor to ground.
(This matches the peak detector decay time constant to the time constant of the 0.1 µF coupling capacitor C3.) A
±10% ceramic capacitor should be used at this pin. The peak detector is used to drive the “dB-below-peak” data
2 PK DET slicer and the AGC release function. The AGC hold-in time can be extended beyond the peak detector decay time
with the AGC capacitor, as discussed above. Where low data rates and OOK modulation are used, the
“dB-below-peak” data slicer and the AGC are optional. In this case, the PKDET pin can be left unconnected, and
the AGC pin can be connected to VCC to reduce the number of external components needed. The peak detector
capacitor is discharged in the transceiver power-down (sleep) mode and in the transmit modes. See the descrip-
tion of Pin 3 below for further information.

This pin is connected directly to the transceiver BBOUT pin. On the circuit board, BBOUT also drives the trans-
ceiver CMPIN pin through C3, a 0.1 µF coupling capacitor (tBBC = 6.4 ms). RX BBO can also be used to drive an
external data recovery process (DSP, etc.). The nominal output impedance of this pin is 1 K. The RX BBO signal
changes about 10 mV/dB, with a peak-to-peak signal level of up to 675 mV. The signal at RX BBO is riding on a
1.1 Vdc value that varies somewhat with supply voltage and temperature, so it should be coupled through a ca-
3 RX BBO pacitor to an external load. A load impedance of 50 K to 500 K in parallel with no more than 10 pF is recom-
mended. Note the AGC reset function is driven by the signal applied to CMPIN through C3. When the transceiver
is in power-down (sleep) or in a transmit mode, the output impedance of this pin becomes very high, preserving
the charge on the coupling capacitor(s). The value of C3 on the circuit board has been chosen to match typical
data encoding schemes at 2.4 kbps. If C3 is modified to support higher data rates and/or different data encoding
schemes and PK DET is being used, make the value of the peak detector capacitor about 1/3 the value of C3.

RX DATA is connected directly to the transceiver data output pin, RXDATA. This pin will drive a 10 pF, 500 K par-
allel load. The peak current available from this pin increases with the receiver low-pass filter cutoff frequency. In
the power-down (sleep) or transmit modes, this pin becomes high impedance. If required, a 1000 K pull-up or
4 RX DATA
pull-down resistor can be used to establish a definite logic state when this pin is high impedance (do not connect
the pull-up resistor to a supply voltage higher than 3.5 Vdc or the transceiver will be damaged). This pin must be
buffered to successfully drive low-impedance loads.

The TX IN pin is connected to the transceiver TXMOD pin through a 4.7 K resistor on the circuit board. Additional
series resistance will often be required between the modulation source and the TX IN pin, depending on the de-
sired output power and peak modulation voltage (3.3 K typical for a peak modulation voltage of 3 volts). Saturated
output power requires about 450 µA of drive current. Peak output power PO for a 3 Vdc supply is approximately:

5 TX IN
PO = 4.8*((VTXH – 0.9)/(RM + 4.7))2, where PO is in mW, peak modulation voltage VTXH is in volts and
external modulation resistor RM is in kilohms

This pin must be held low in the receive and sleep modes. Please refer to section 2.9 of the ASH Transceiver De-
signer’s Guide for additional information.

6 GND This is a ground pin.

3
7 GND This is a ground pin.

This pin is the receiver low-pass filter bandwidth adjust, and is connected directly to the transceiver LPFADJ pin.
R6 on the circuit board (330 K) is connected between LPFADJ and ground will be in parallel with any external re-
sistor connected to LPF ADJ. The filter bandwidth is set by the parallel resistance of R6 and the external resistor
(if used). The equivalent resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth fLPF
from 4.4 kHz to 1.8 MHz. The 3 dB filter bandwidth is determined by:

fLPF = 1445/ (330*RLPF/(330 + RLPF)), where RLPF is in kilohms, and fLPF is in kHz
8 LPF ADJ
A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between fLPF
and 1.3* fLPF with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree
equiripple phase response. The peak drive current available from RXDATA increases in proportion to the filter
bandwidth setting. As shipped, the transceiver module is set up for nominal 2.4 kbps operation. An external resis-
tor can be added between Pin 6 and ground to support higher data rates. Preamble training times will not be
decreased, however, unless C3 is replaced with a smaller capacitor value (see the descriptions of Pins 2 and 3
above). Refer to sections 1.4.3, 2.5.1 and 2.6.1 in the ASH Transceiver Designer’s Guide for additional informa-
tion on data rate adjustments.

This is the positive supply voltage pin for the module. The operating voltage range is 2.7 to 3.5 Vdc. It is also pos-
9 VCC
sible to use Pin 1 as the Vcc input. Please refer to the Pin 1 description above.

10 GND This is the supply voltage return pin.

CTR1 is connected to the CNTRL1 control pin on the transceiver. CTR1 and CTR0 select the transceiver operat-
ing modes. CTR1 and CTR0 both high place the unit in the receive mode. CTR1 and CTR0 both low place the unit
in the power-down (sleep) mode. CTR1 high and CTR0 low place the unit in the ASK transmit mode. CTR1 low
11 CTR1
and CTR0 high place the unit in the OOK transmit mode. CTR1 is a high-impedance input (CMOS compatible).
This pin must be held at a logic level; it cannot be left unconnected. At turn on, the voltage on this pin and CTR0
should rise with VCC until VCC reaches 2.7 Vdc (receive mode). Thereafter, any mode can be selected.

CTR0 is connected to the CNTRL0 control pin on the transceiver CTR0 is used with CTR1 to control the operating
modes of the transceiver. CTR0 is a high-impedance input (CMOS compatible). This pin must be held at a logic
12 CTR0
level; it cannot be left unconnected. At turn on, the voltage on this pin and CTR1 should rise with VCC until VCC
reaches 2.7 Vdc (receive mode). Thereafter, any mode can be selected.

RFIO is the RF input/output pin. A matching circuit for a 50 ohm load (antenna) is implemented on the circuit
13 RFIO
board between this pin and the transceiver SAW filter transducer.

This pin is the RF ground (return) to be used in conjunction with the RFIO pin. For example, when connecting the
14 RF GND transceiver module to an external antenna, the coaxial cable ground is connected this pin and the coaxial cable
center conductor is connected to RFIO.

2 .4 k b p s A p p lic a tio n C ir c u it 1 9 .2 k b p s A p p lic a tio n C ir c u it

R /T 3 V d c R /T 3 V d c

1 2 1 1 1 0 9 8 1 2 1 1 1 0 9 8

1 3 7 1 3 7
3 3 K

D R 3 0 0 0 D R 3 0 0 0
1 4 6 1 4 6

1 2 3 4 5 1 2 3 4 5

D a ta In D a ta In
3 .3 K 3 .3 K
D a ta O u t D a ta O u t

4
DR3000 Bill of Materials

Item Reference Description Value Quantity

1 IC1 TR1000 ASH Transceiver 916.5 MHz 1
2 C1, C2, C4, C6 Capacitor SMT 0603 100 pF ±10% 4
3 C3 Capacitor SMT 0603 0.1 µF ±10% 1
4 C5 Capacitor E1A-B 0805 4.7 µF ±10% 1
5 R1 Resistor Chip 0603 270 K ±5% 1
6 R2 Resistor Chip 0603 330 K ±5% 1
7 R3 Resistor Chip 0603 10 K ±1% 1
8 R4 Resistor Chip 0603 100 K ±1% 1
9 R5 Resistor Chip 0603 4.7 K ±5% 1
10 R6 Resistor Chip 0603 330 K ±5% 1
11 R7 Resistor Chip 0603 zero ohm jumper 1
12 R8 Not Used N/A 0
13 L1 Inductor Chip 0805CS 10 nH ±5% 1
14 L2 Inductor Chip 0805CS 100 nH ±10% 1
15 PCB Printed Circuit Board 400-1526-002x1 1

Note: Specifications subject to change without notice.

File: dr3000h.vp, 2002.10.23 rev