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RDC-19220/2/4 SERIES
16-BIT MONOLITHIC TRACKING RESOL
VER
(LVDT)-TO-DIGITAL CONVERTERS FEATURES
• +5 Volt Only Option
• Only Five External Passive
Components
• Programmable:
- Resolution: 10-, 12-, 14-, or 16-Bit
- Bandwidth: to 1200 Hz
- Tracking: to 2300 RPS
• Differential Resolver and LVDT
Input Modes
• Velocity Output Eliminates
Tachometer
• Built-In-Test (BIT) Output
• No 180° Hang-Up

DESCRIPTION • Small Size: Available in DDIP, PLCC or

MQFP Packages
The RDC-19220 Ser ies of con verters are lo w-cost, v ersatile, 16-bit
monolithic, state-of-the-ar t Resolv er(/LVDT)-to-Digital Con verters. • -55° to +125°C Operating
These single-chip con verters are a vailable in small 40-pin DDIP, 44- Temperature Available
pin J-Lead, and 44-pin MQFP packages and offer programmable fea- • Programmable for LVDT input
tures such as resolution, bandwidth and v elocity output scaling.

Resolution programming allows selection of 10-, 12-, 14-, or 16-bit,

with accur acies to 2.3 min. This feature combines the high tr acking
rate of a 10-bit con verter with the precision and lo w-speed velocity
resolution of a 16-bit converter in one package.

The velocity output (VEL) from the RDC-19220 Ser ies, which can be
used to replace a tachometer, is a 4 V signal (3.5 V with the +5 V only
option) referenced to ground with a linearity of 0.75% of output voltage.
The full scale value of VEL is set by the user with a single resistor.

RDC-19220 Series converters are a vailable with oper ating tempera-

ture ranges of 0° to +70°C, -40° to +85°C and -55° to +125°C. Military
processing is available.

APPLICATIONS
With its low cost, small size, high accuracy and versatile performance,
the RDC-19220 Series converter is ideal for use in modern high-per-
formance industrial and militar y control systems. Typical applications
include motor control, r adar antenna positioning, machine tool con-
trol, robotics , and process control. MIL-PRF-38534 processing is
available for military applications.
FOR MORE INFORMATION CONTACT:
Technical Support:
Data Device Corporation
1-800-DDC-5757 ext. 7771
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com © 1999 Data Device Corporation http://www.Datasheet4U.com
www.ddc-web.com
Data Device Corporation
+REF -REF BIT

-VSUM
SIN C BW
-S - C BW
+S + 10 RB
R1
CONTROL
COS TRANSFORMER GAIN DEMODULATOR VEL
-C -

+C + INTEGRATOR RV
HYSTERESIS
A B
+5C
-VCO

2
16 BIT VCO
+CAP -5 V
UP/DOWN &
-CAP INVERTER RS
COUNTER TIMING
-5C

E RC
A GND
+5 V DATA
GND LATCH
-5 V

INH EM BIT 1 EL A B CB
THRU
BIT 16

RDC-19220 SERIES
R-12/05-0
FIGURE 1. RDC-19220 SERIES BLOCK DIAGRAM
 TABLE 1. RDC-19220 SERIES SPECIFICATIONS TABLE 1. RDC-19220 SERIES SPECS (CONT’D)
These specifications apply over the rated power supply, temperature These specifications apply over the rated power supply, temperature
and reference frequency ranges, and 10% signal amplitude variation and reference frequency ranges, and 10% signal amplitude v ariation
and harmonic distortion. and harmonic distortion.
PARAMETER UNIT VALUE PARAMETER UNIT VALUE
RESOLUTION Bits 10, 12, 14, or 16 DYNAMIC (at maximum bandwidth)
ACCURACY Min 4 or 2 + 1 LSB (note 3) CHARACTERISTICS
REPEATABILITY LSB 1 max Resolution bits 10 12 14 16
Tracking Rate (max)(note 4) rps 1152 288 72 18
DIFFERENTIAL LINEARITY LSB 1 max in the 16th bit Bandwidth(Closed Loop) Hz 1200 1200 600 300
REFERENCE (+REF, -REF) (max) (note 4)
Type Differential Ka (Note 7) 1/sec2 5.7M 5.7M 1.4M 360k
Voltage: A1 1/sec 19.5 19.5 4.9 1.2
differential VP-P 10 max A2 1/sec 295k 295k 295k 295k
single ended VP ±5 max A 1/sec 2400 2400 1200 600
overload V ±25 continuous, 100 transient B 1/sec 1200 1200 600 300
Frequency Hz DC to 40,000 (note 4 & note 9) Acceleration (1 LSB lag) deg/s2 2M 500k 30k 2k
Input Impedance Ohm 10M min // 20 pf Settling Time(179° step) msec 2 8 20 50
SIGNAL INPUT (+S, -S, SIN, +C, -C, COS) VELOCITY
Type Resolver, differential, groundbased CHARACTERISTICS
Voltage: operating Vrms 2 ±15% Polarity Positive for increasing angle
overload V ±25 continuous Voltage Range(Full Scale) V ±4 (at nominal ps)
Input impedance Ohm 10M min//10 pf. Scale Factor Error % 10 typ 20 max
DIGITAL INPUT/OUTPUT (Note 6) Scale Factor TC PPM/C 100 typ 200 max
Logic Type TTL/CMOS compatible Reversal Error % 0.75 typ 1.3 max
Inputs Logic 0 = 0.8 V max. Linearity % 0.25 typ 0.50 max
Logic 1 = 2.0 V min. Zero Offset mv 5 typ 10 max
Loading =10 µA max pull-up cur- Zero Offset TC µV/C 15 typ 30max
rent source to +5 V //5 pF max. Load kΩ 8 min
CMOS transient protected Noise (Vp/V)% 1 typ . 125 min 2 max
Inhibit (INH) Logic 0 inhibits; Data stable (note 5)
POWER SUPPLIES
within 0.3 µs +5 -5
Nominal Voltage V
Enable Bits 1 to 8 (EM) Logic 0 enables;Data stable with % ± 5 ±5
Voltage Range
Enable Bits 9 to 16 (EL) -in 150 ns (logic 0=Transparent) +7 -7
Max Volt. w/o Damage V
Logic 1 = High Impedance mA 14 typ, 22 max (each)
Current
Data High Z within 100 nS
Resolution and Mode TEMPERATURE RANGE
Control (A & B) Mode B A Resolution Operating (Case)
(see notes 1 and 2. resolver 0 0 10 bits -30X °C 0 to +70
pre-set to logic 1 note 6) " 0 1 12 bits -20X °C -40 to +85
"1 0 14 bits -10X °C -55 to +125
"1 1 16 bits -A0X °C -40 to +125
LVDT -5 V 0 8 bits Storage
" 0 -5 V 10 bits plastic package °C -65 to +150
"1 -5 V 12 bits ceramic package °C -65 to +150
" -5 V -5 V 14 bits MOISTURE SENSITIVITY
Outputs LEVEL MQFP JEDEC 2
Parallel Data (1-16) 10, 12, 14, or 16 par allel lines; RDC-19224
natural binary angle positive
THERMAL RESISTANCE
logic (see TABLE 2)
Junction-to-Case (θjc)
Converter Busy (CB) 0.25 to 0.75 µs positive pulse
40-pin DDIP (ceramic) °C/W 4.6
leading edge initiates counter
44-pin J-Lead (ceramic) °C/W 2.4
update.
Zero Index Logic 1 at all 0s (ENL to -5 V);
(Zl) LSBs are enabled PHYSICAL
Built-in-Test (BIT) Logic 0 for BIT condition. CHARACTERISTICS
±100 LSBs of error typ. with a Size: 40-pin DDIP in(mm) 2.0 x 0.6 x 0.2 (50.8 x 15.24 x 5.08)
filter of 500 µS, or total Loss-of- 44-pin J-Lead in(mm) 0.690 square (17.526)
Signal (LOS) 44-pin MQFP in(mm) 0.394 square (10.0)
Drive Capability 50 pF +
Logic 0; 1 TTL load, 1.6 mA at
Weight: Plastic Cer amic
0.4 V max
40-pin DDIP oz(g) n/a 0.24 (6.80)
Logic 1; 10 TTL loads, = 0.4 mA
44-pin J-Lead oz(g) n/a 0.065 (1.84)
at 2.8 V min
44-pin MQFP oz(g) 0.017 (0.5) n/a
Logic 0; 100 mV max driving CMOS
Logic 1; +5 V supply minus 100mV
min driving CMOS, High Z;
10 uA//5 pF max

Data Device Corporation RDC-19220 SERIES

www.ddc-web.com 3 R-12/05-0
 Notes for TABLE 1:(from previous page)
φ. Its output is an analog error angle , or diff erence angle ,
1. Unused data bits are set to logic “0.”
2. In LVDT mode, bit 16 is LSB f or 14-bit resolution or bit 12 is LSB f or between the two inputs. The CT performs the ratiometric trigono-
10-bit resolution. metric computation of SINθCOSφ - COSθSINφ = SIN(θ-φ) using
3. Accuracy spec below for LVDT mode, null to + full scale tr avel (45 amplifiers, switches, logic and capacitors in precision r atios.
degrees).(2 wire-LVDT configuration).
4 Min part = 0.15% + 1 LSB of full scale “resolution set”.
2 Min part = 0.07% + 1 LSB of full scale “resolution set” Note: The transfer function of the CT is nor mally trigonometric,
Accuracy spec below for LVDT mode, null to + full scale tr avel (90 but in LDVT mode the transfer function is triangular (linear)
degrees).(3 wire-LVDT configuration). and could thereby convert any linear transducer output.
4 Min part = 0.07% + 1 LSB of full scale “resolution set”.
2 Min part = 0.035% + 1 LSB of full scale “resolution set”
Note that this is the con verter spec only and does not consider the TABLE 2. DIGITAL ANGLE OUTPUTS
front end external resistor tolerances. BIT DEG/BIT MIN/BIT
4. See text, General Setup Considerations and HigherTracking Rates.
5. See text: General Setup Considerations for RDC19222. 1(MSB) 180 10800
6. Any unused input pins may be left floating (unconnected). All input 2 90 5400
pins are internally pulled-up to +5 Volts. 3 45 2700
7. Ka = Acceleration constant, for a full definition see the RD/RDC 4 22.5 1350
application manual acceleration lag section. 5 11.25 675
8. When using internally generated -5V, the internal -5V charge pump 6 5.625 337.5
when measured at the converter pin, can read as lo w as -20% (or - 7 2.813 168.75
4V). 8 1.405 84.38
9. No 180° hangup with A/C ref erence. 9 0.7031 42.19
10 0.3516 21.09
11 0.1758 10.55
12 0.0879 5.27
13 0.0439 2.64
14 0.0220 1.32
THEORY OF OPERATION 15 0.0110 0.66
16 0.0055 0.33
The RDC-19220 Ser ies of con verters are single CMOS custom
monolithic chips. They are implemented using the latest IC tech- Note: EM enables the MSBs and EL enables the LSBs.
nology which merges precision analog circuitr y with digital logic
to f orm a complete , high-perf ormance tr acking Resolv er-to- The con verter accur acy is limited b y the precision of the com-
Digital con verter. For user fle xibility and con venience, the con- puting elements in the CT . For enhanced accuracy, the CT in
verter bandwidth, dynamics and v elocity scaling are e xternally these converters uses capacitors in precision r atios, instead of
set with passive components. the more conventional precision resistor ratios. Capacitors, used
as computing elements with op-amps , need to be sampled to
FIGURE 1 is the functional b lock diag ram of the RDC-19220 eliminate voltage drifting. Therefore, the circuits are sampled at a
Series. The con verter oper ates with ±5 Vdc po wer supplies . high rate (67 kHz) to eliminate this dr ifting and at the same time
Analog signals are ref erenced to analog g round, which is at to cancel out the op-amp offsets .
ground potential. The converter is made up of two main sections;
a converter and a digital interf ace. The converter front-end con- The error processing is perf ormed using the industr y standard
sists of sine and cosine differential input amplifiers. These inputs technique for type II tracking R/D converters. The dc error is inte-
are protected to ±25 V with 2 k Ω resistors and diode clamps to grated yielding a v elocity voltage which in tur n drives a v oltage
the ±5 Vdc supplies . These amplifiers f eed the high accur acy controlled oscillator (VCO). This VCO is an incremental integ ra-
Control Transformer (CT). Its other input is the 16-bit digital angle tor (constant voltage input to position r ate output) which togeth-
RB CBW
VEL

C BW /10 RV
RS

-VSUM VEL -VCO

50 pf
C VCO

CT
RESOLVER R1 16 BIT
+
INPUT GAIN DEMOD VCO UP/DOWN
(θ) 1 ±1.25 V COUNTER
- CS FS THRESHOLD
11 mV/LSB

DIGITAL
H=1 OUTPUT
(φ)

FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1

Data Device Corporation RDC-19220 SERIES
www.ddc-web.com 4 R-12/05-0
er with the velocity integrator forms a type II servo feedback loop. GENERAL SETUP CONSIDERATIONS
A lead in the frequency response is introduced to stabiliz e the Note: For detailed application and technical information see the RD/RDC convert-
er applications man ual which is a vailable for download from the DDC w eb site @
loop and another lag at higher frequency is introduced to reduce www.ddc-web.com.
the gain and r ipple at the carr ier frequency and abo ve. The set-
tings of the various error processor gains and break frequencies DDC has e xternal component selection softw are which consid-
are done with e xternal resistors and capacitors so that the con- ers all the cr iteria below, and in a simple f ashion, asks the k ey
verter loop dynamics can be easily controlled b y the user. parameters (carrier frequency, resolution, bandwidth, and tr ack-
ing rate) to derive the external component value.
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined from The f ollowing recommendations should be considered when
its Transfer Function Block Diagrams and its Bode Plots (open and installing the RDC-19220 Series R/D converters:
closed loop).These are shown in FIGURES 2, 3, and 4.
1) In setting the bandwidth (BW) and Tracking Rate (TR) (select-
The open loop transfer function is as follows: ing five external components), the system requirements need
to be considered. For greatest noise immunity, select the min-
A2 S +1 ( ) imum BW and TR the system will allow.
B
Open Loop Transfer Function =
S2 S +1
10B ( ) 2) +5 and -5 volt operation:

where A is the gain coefficient and A 2= A1A2 Power supplies are ±5 V dc. For lowest noise performance it
is recommended that a 0.1 µF or larger cap be connected
and B is the frequency of lead compensation. from each supply to g round near the con verter pac kage.
When using a +5V and -5V supply to po wer the con verter,
The components of gain coefficient are error gradient, integrator RDC-19222 pins 22, 23, 25, 26 m ust be no connection, and
gain and VCO gain. These can be broken down as follows: on RDC-19224 pins 20, 40, 16, 11, m ust be no connection.
Also, the 10uF cap is not connected to +cap and -cap pins .
- Error Gradient = 0.011 volts per LSB (CT + Error Amp + Demod
with 2 Vrms input) 3) This con verter has 2 inter nal g round planes , which reduce
noise to the analog input due to digital g round currents. The
- Integrator Gain = Cs Fs volts per second per volt
1.1 CBW resolver inputs and v elocity output are ref erenced to A GND.
The digital outputs and inputs are ref erenced to GND . The
- VCO Gain = 1 LSBs per second per volt AGND and GND pins m ust be tied together as close to the
1.25 RV CVCO
converter pac kage as possib le. Not shor ting these pins
where: Cs = 10 pF
Fs = 67 kHz when Rs = 30 kΩ together as close to the con verter pac kage as possib le will
Fs = 100 kHz when Rs = 20 kΩ cause unstable converter results.
Fs = 134 kHz when Rs = 15 kΩ
CVCO = 50 pF

RV, RB, and C BW are selected by the user to set velocity scaling
and bandwidth.
-1
2d
b/o

(CRITICALLY DAMPED)
c
t

GAIN = 4
VELOCITY 2A
OUT OPEN LOOP ω (rad/sec)
ERROR PROCESSOR B A -6
db 10B
VCO (B = A/2) /oc
CT t
+ A1 S + 1 A2 DIGITAL
RESOLVER e B
INPUT S POSITION GAIN = 0.4
(θ) S S +1
- 10B OUT (φ)

f BW = BW (Hz) = 2A
π

H=1
2A 2 2A
CLOSED LOOP ω (rad/sec)

FIGURE 3. TRANSFER FUNCTION

BLOCK DIAGRAM #2 FIGURE 4. BODE PLOTS
Data Device Corporation RDC-19220 SERIES
www.ddc-web.com 5 R-12/05-0
4) The BIT output which is activ e low is activated by an error of
approximately 100 LSBs . During nor mal oper ation f or step
inputs or on power up, a large error can e xist.
-CAP
5) This device has several high impedance amplifier inputs (+C , RDC-19222/4 10uF
-C, +S, -S, -VCO and -VSUM). These nodes are sensitiv e to +CAP
noise and coupling components should be connected as
close as possible.

6) Setup of bandwidth and velocity scaling for the optimized crit- (-5c) -5V (+5c) +5V
ically damped case should proceed as f ollows:
- Select the desired f BW (closed loop) based on overall
system dynamics.
.01uF .01uF
- Select f carrier ≥ 3.5f BW
+
- Select the applications tracking rate (in accordance with TABLE 3),
and use appropriate values for R SET and R CLK

Full Scale Velocity Voltage

+ 47uF 47uF
- Compute Rv =
Tracking Rate (rps) x 2 resolution x 50 pF x 1.25 V
FIGURE 5. -5V BUILT-IN INVERTER
3.2 x Fs (Hz) x 108
- Compute CBW (pF) =
Rv x (f BW)2
- Where Fs = 67 kHz for R CLK = 30 KΩ
100 kHz for R CLK = 20 KΩ 7) Selecting a f BW that is too low relative to the maxim um appli-
125 kHz for R CLK = 15 KΩ
cation tr acking r ate can create a spin-around condition in
0.9
- Compute RB =
CBW x f BW
which the con verter never settles. The relationship to insure
against spin-around is as f ollows (T ABLE 3):
- Compute CBW
10
8) For RDC-19222 & RDC-19224; package’s only.
As an example:
Calculate component values for a 16-bit converter with 100Hz
bandwidth, a tracking rate of 10RPS and a full scale velocity
of 4 volts.
This version is capab le of +5V only oper ation. It accomplish-
es this with a charge pump technique that in verts the +5V
- Rv = 4V = 97655 Ω supply for use as -5V, hence the +5V supply current doub les.
10 rps x 216 x 50 pF x 1.25 V
The built-in -5 V inverter can be used b y connecting pin 2 to
3.2 x 67 kHz x 108
- Compute CBW (pF) =
97655 x 100 Hz2
= 21955 pF 26, pin 17 to 22, a 10 µF/10 Vdc capacitor from pin 23 (nega-
tive terminal) to pin 25 (positive terminal), and a 47 µF/10 Vdc
- Compute RB = 0.9 = 410 kΩ
21955 x 10 -12 x 100 Hz capacitor from -5 V to GND. The current dr ain from the +5 V
supply doubles. No external -5 V supply is needed (SEE FIG-
URE 5).

Note: DDC has software available to perform the previous calcu- When using the -5 V inverter, the max. tracking rate should be
lations. Contact DDC to request software or visit our web- scaled for a velocity output of 3.5V max.Use the following equa-
site at www.ddc-web.com to download software. tion to determine tracking rate used in the formula on page 5:

TR (required) x (4.0) = Tracking r ate used in calculation

(3.5)

Note: When using the highest BW and Tracking Rates, using

the -5 V inverter is not recommended.
TABLE 3. TRACKING/BW RELATIONSHIP
RPS (MAX)/BW RESOLUTION
HIGHERTRACKING RA
TES AND CARRIER FREQ
UENCIES
1 10 Tracking r ate (nominally 4 V) is limited b y tw o f actors: velocity
0.45 12 voltage satur ation and maxim um inter nal cloc k r ate (nominally
0.25 14 1,333,333 Hz). An understanding of their inter action is essential
0.125 16 to extending performance.

The Gener al Setup Consider ations section mak es note of the

selection of Rv for the desired velocity scaling.Rv is the input resis-

Data Device Corporation RDC-19220 SERIES

www.ddc-web.com 6 R-12/05-0
bring it to 0 V. The output counts per second per volt input is there- TRANSFORMER ISOLATION
fore:
System requirements often include electrical isolation. There are
1 transformers available for reference and synchro/resolver signal
(Rv x 50 pF x 1.25) isolation. TABLE 6 includes a listing of the most common tr ans-
formers. The synchro/resolv er tr ansformers reduce the v oltage
As an example: to 2 Vrms for a direct connection to the converter. See FIGURES
5A, 5B, 5C and 5D f or transformer layouts and schematics, and
Calculate Rv for the maximum counting rate, at a VEL voltage FIGURE 6 for typical connections.
of 4 V.
DC INPUTS
For a 12-bit converter there are 2 12 or 4096 counts per rotation. As noted in TABLE 1, the RD-19220/2/4 will accept DC inputs .
1,333,333/4096 = 325 rotations per second or 333,333 counts
per second per volt. • Operation from 0° to 180° or 180° to 359° only . This is due to
the possibility of a unstab le f alse n ull. IE: 180° hang-up . This
1 180° hang-up is unstable and once the converter moves it will go
Rv = = 48 kΩ
(333,333 x 50 pF x 1.25)
to the correct answer. In real world applications where an instan-
taneous 180° change are not possib le the converter will always
The maxim um r ate capability of the RDC-19220 is set b y R s. be correct within 360°. The problem ar ises at po wer-up in real
When R s = 30 k Ω it is nominally 1,333,333 counts/sec , which systems. If the con verter angle po wers up at e xactly 180° from
equates to 325 r ps (rotations per second). This is the absolute the applied input the converter will not move. This is very unlike-
maximum rate; it is recommended to only run at <90% of this rate ly although it is theoretically possible. This condition is most often
(as seen in TABLE 3), theref ore the minim um R v will be limited encountered dur ing wr ap around v erification tests , sim ulations
to 55 kΩ. The converter maximum tracking rate can be increased or troubleshooting.
50% in the 16- and 14-bit modes and 100% in the 12- and 10-bit
modes b y increasing the supply current from 12 to 15 mA (b y • Set the REF input to DC by tying RH to +5V and RL to GND or
using an R c = 23 k Ω), and b y increasing the sampling r ate by -5V.
changing Rs to 20 kΩ for 16- and 14-bit resolution or to 15 kΩ for
12- and 10-bit resolution (see TABLE 4). • Set the COS and SIN inputs such that max signal will be equal
to 1.8VDC. IE: For 90°, the SIN input will equal 1.8VDC. This will
The maximum carrier frequency can, in the same w ay, increase keep the BW hysteresis consistant with AC operation.
from: 5 to 10 kHz in the 16-bit mode , 7 to 14 kHz in the 14-bit
mode, 11 to 32 kHz in the 12-bit mode , and 20 to 40 kHz in the • Input offsets will affect accuracy. Verify the COS and SIN inputs
10-bit mode (see TABLE 5). do not ha ve DC offsets . If offsets are present , a diff erential op
amp configur ation can be used to minimiz e diff erential offset
The maximum tracking rate and carr ier frequency for full perfor- problems.
mance are set b y the po wer supply current control resistor (R c)
per the following tables: • With DC inputs the converter BIT will remain at logic 0.

The carrier frequency should be 1/10, or less, of the sampling fre- • The Bandwidth value of the converter should be chosen based
quency in order to have many samples per carrier cycle. The con- on the r ate of change of the system’ s input amplitude v ariation,
verter will work with reduced quadrature rejection at a carrier fre- and should be large enough so to minimize it’s effect on the sys-
quency up to 1/4 the sampling frequency . Carrier frequency should tem dynamics. Note that if the bandwidth is too high the system
be at least 3.5 times the BW in order to eliminate the chance of .jitter will be more susceptible to noise.

REDUCED POWER SUPPLY CURRENTS • The accuracy of the converter using a DC input will be degrad-
When Rs = 30 kΩ (tracking rate is not being pushed), nominal po wer ed from the r ated accur acy. Consider the best case where the
supply current can be cut from 14 to 9 mA b y setting Rc = 53 kΩ. input is single ended and no additional DC offsets are present on
the input con verter - the accur acy will deg rade by about 2 arc
minutes. IE:, If a par t is r ated at 2 arc min utes, a DC input will
degrade the accuracy to approximately 4 arc minutes.

Data Device Corporation RDC-19220 SERIES

www.ddc-web.com 7 R-12/05-0
 TABLE 4. MAX TRACKING RATE TABLE 5. CARRIER FREQUENCY
(MIN) IN RPS (MAX) IN KHZ
RC&RSET RS&RCLK RESOLUTION Depending on the res- RC&RSET RS&RCLK RESOLUTION
Ω)
(Ω Ω)
(Ω 10 12 14 16
olution, select one of
Ω)
(Ω Ω)
(Ω 10 12 14 16
the values from this
30k**or open 30k 1200 288 72 18 row, for use in convert- 30k** or open 30k 20 11 7 5
er max tracking rate
23k 20k 1200 432 108 27 formula. (See previous 23k 30k 24 12 11 7
page for formula.) 23k 20k 34 24 14 10
23k 15k * 576 * *
* Not recommended. 23k 15k 40 32 * *
** The use of a high quality thin-film resistor will pro vide better temperature * Not recommended.
stability than leaving open. ** The use of a high quality thin-film resistor will pro vide better temperature
Note: RC “Rcurrent” = RSET stability than leaving open.
RS “Rsample” = RCLK Note: RC “Rcurrent” = RSET
RS “Rsample” = RCLK

TABLE 6. TRANSFORMERS NOTE 1

FREQUENCY ANGLE LENGTH WIDTH HEIGHT FIGURE AVAILABLE
P/N TYPE IN (VRMS)* OUT (VRMS)**
(HZ)* ACCURACY*** (IN) (IN) (IN) NUMBER FROM
52034 S-R 400 11.8 2 1 0.81 0.61 0.3 5A BETA
52035 S-R 400 90 2 1 0.81 0.61 0.3 5A BETA
52036 R-R 400 11.8 2 1 0.81 0.61 0.3 5B BETA
52037 R-R 400 26 2 1 0.81 0.61 0.3 5B BETA
52038 R-R 400 90 2 1 0.81 0.61 0.3 5B BETA
B-426 Reference 400 115 3.4 N/A 0.81 0.61 0.32 5C BETA
52039-X Synchro 60 90 2 1 1.1 1.14 .42 5D DDC
24133-X Reference 60 115 3/6 **** N/A 1.125 1.125 .42 5D DDC
* ±10% Frequency (Hz) and Line-to-Line input v oltage (Vrms) tolerances Note 1: Available from refer’s to the company that the trans-
** 2 Vrms Output Magnitudes are -2 Vrms ±0.5% full scale former is available from.
*** Angle Accuracy (Max Minutes)
**** 3 Vrms to ground or 6 Vrms differential (±3% full scale) Beta Transformer Technology Corporation
Dimensions are for each individual main and teaser www.bttc-beta.com
60 Hz Synchro transformers are active (requires ±15 Vdc power supplies)
400 Hz transformer temperature range: -55°C to +125°C
60 Hz transformer (52039-X, 24133-X) temperature ranges: add to part number -1 or -3,
-1 = -55°C to +85°C
-3 = 0 to +70°C

0.61 MAX 0.61 MAX

(15.49) (15.49)
0.61 MAX 0.61 MAX
(15.49) 0.15 MAX 0.09 MAX (15.49) 0.15 MAX 0.09 MAX
(3.81) (2.29) (3.81) (2.29)
0.30 MAX 0.09 MAX 0.15 MAX 0.30 MAX 0.09 MAX 0.15 MAX
(7.62) (2.29) (3.81) (7.62) (2.29) (3.81)

1 3 4 5 11 12 14 15 1 3 4 5 11 12 14 15
0.81 MAX 0.81 MAX
(20.57) (20.57)
T1A T1B 0.600 T1A T1B 0.600
(15.24) (15.24)
10 9 8 7 6 20 19 18 17 16 10 9 8 7 6 20 19 18 17 16
0.115 MAX 0.115 MAX
(2.92) (2.92)
SIDE VIEW 0.100 (2.54) TYP SIDE VIEW 0.100 (2.54) TYP
BOTTOM VIEW BOTTOM VIEW
TOL NON CUM TOL NON CUM
TERMINALS TERMINALS
0.025 ±0.001 (6.35 ±0.03) DIAM BOTTOM VIEW 0.025 ±0.001 (6.35 ±0.03) DIAM BOTTOM VIEW
PIN NUMBERS FOR REF. ONLY PIN NUMBERS FOR REF. ONLY
0.125 (3.18) MIN LENGTH 0.125 (3.18) MIN LENGTH
SOLDER PLATED BRASS SOLDER PLATED BRASS

Dimensions are shown in inches (mm). Dimensions are shown in inches (mm).

T1A T1A
1 6 -SIN S1 1 6 -SIN
S1
5
3 10 3 10
S3 +SIN S3 +SIN
SYNCHRO RESOLVER
RESOLVER RESOLVER
INPUT INPUT
OUTPUT T1B OUTPUT
T1B
11 16 -COS 11 16 -COS
S4

15 20 S2 15 20 +COS
S2 +COS

FIGURE 5A. TRANSFORMER LAYOUT AND FIGURE 5B. TRANSFORMER LAYOUT AND
SCHEMATIC (SYNCHRO INPUT - 52034/52035) SCHEMATIC (RESOLVER INPUT - 52036/52037/52038)

Data Device Corporation RDC-19220 SERIES

www.ddc-web.com 8 R-12/05-0
 CASE IS BLACK AND
NON-CONDUCTIVE

1.14 MAX 0.25

(28.96) (6.35)
MIN.
• • • • +
S3 S1 +15 V +S
(+15 V) (-R)
*
* * *
0.32 MAX 0.61 MAX
(8.13) (15.49)
0.125 MIN
(3.17) 0.09 MAX 0.15 MAX
(2.29) (3.81) 1.14 MAX 52039 0.85 ±0.010
(28.96) or (21.59 ±0.25)
24133

1 2 3 5
0.600 0.81 MAX (RH) (RL) (V) (+R) (-Vs)
T1A (15.24) (20.57) S2
* V +C -Vs
• + • • •
10 9 8 7 6 (BOTTOM VIEW)
0.42
0.13 ±0.03 (10.67)
0.105 (2.66) (3.30 ±0.76) MAX.
SIDE VIEW 0.100 (2.54) TYP 0.21 ±0.3
TOL NON CUM (5.33 ±0.76)
TERMINALS 0.175 ±0.010 (4.45 ±0.25)
BOTTOM VIEW NONCUMULATIVE
0.025 ±0.001 (6.35 ±0.03) DIAM TOLERANCE
0.125 (3.18) MIN LENGTH 0.040 ±0.002 DIA. PIN.
SOLDER PLATED BRASS
SOLDER-PLATED BRASS

Dimensions are shown in inches (mm).

+15 V +15 V

Input Output Input Output

1 6 RH +R (RH) S1 +S
24133 S2 52039
INPUT OUTPUT RL -R (RL) S3 +C

5 10
V -Vs V -Vs
(Analog (-15 V) (Analog (-15 V)
Gnd) Gnd)
The mechanical outline is the same f or the synchro input tr ansformer (52039) and
the reference input transformer (24133), except for the pins. Pins for the reference
transformer are shown in parenthesis ( ) below. An asterisk * indicates that the
pin is omitted.

FIGURE 5C. TRANSFORMER LAYOUT AND FIGURE 5D. 60 HZ SYNCHRO AND REFERENCE
SCHEMATIC (REFERENCE INPUT - B-426) TRANSFORMER DIAGRAMS
(SYNCHRO INPUT - 52039 / REFERENCE INPUT - 24133)

EXTERNAL
REFERENCE
LO HI
1 6 RB CBW
B-426 10
5 CBW/10 RV

-S SIN -R +R -VSUM VEL

S1 -VCO
RH +S
RL 1 10
S3 TIA DIGITAL
3 6 OUTPUT
+C RDC-19220
S4 16
11 20 -C
TIB COS CB
S2
15 16 BIT
AGND
52036(11.8V) INH
OR EM
52037(26V) GND Rs Rc
OR EL
52038(90V)
A B +5V -5V 30K Ω 30K Ω
OR
}

SYNCHRO INPUT
RESOLUTION
CONTROL
S1 +S
RL RH 1 10
S3
3 TIA
5 6
+C
11 20
S2 TIB
15 AGND
16
GND
52034(11.8V)
OR
52035(90V)

FIGURE 6. TYPICAL TRANSFORMER CONNECTIONS

Data Device Corporation RDC-19220 SERIES

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TYPICAL INPUT CONNECTIONS
FIGURES 7 through 9 illustrate typical input configurations

EXTERNAL
REF
LO HI
R1 R2

R3 R4

S3 10k Ω (1%) +S
-R +R

-S
SIN Note: The five external BW components as
S1 COS shown in FIGURE 1 and 2 are necessar y
-C for the R/D to function.

+C
S2 10k Ω (1%)
S4 A GND
RESOLVER GND
Notes:
1) Resistors selected to limit Vref peak to between 1 V and 5 V.
2) External reference LO is grounded, then R3 and R4 are not
needed, and -R is connected to GND.
3) See thin film network DDC-55688-1.

FIGURE 7A. TYPICAL CONNECTIONS, 2 V RESOLVER, DIRECT INPUT

R1
S3 -S SIN
+S
R2

S1

Note: The five external BW components as

shown in FIGURE 1 and 2 are necessar y for
R1 the R/D to function.
S2 +C

R2

S4 A GND

-C COS
R2 = 2
R1 + R2 X Volt

R1 + R2 should not load the Resolv er too much; it is recommended to use a R2 = 10k.

R1 + R2 Ratio Errors will result in Angular Errors ,

2 cycle, 0.1% Ratio Error = 0.029° Peak Error.

FIGURE 7B. TYPICAL CONNECTIONS, X- VOLT RESOLVER, DIRECT INPUT

Data Device Corporation RDC-19220 SERIES
www.ddc-web.com 10 R-12/05-0
 SIN

Rf
Ri -S
S1 -

Ri +S
S3 +

Rf
Note: The five external BW components as
RESOLVER A GND shown in FIGURE 1 and 2 are necessar y
INPUT COS for the R/D to function.

Rf
Ri -C
S4 -

Ri +C
S2 +
8 10
Rf

CONVERTER

Ri x 2 Vrms = Resolver L-L rms voltage

Rf
Rf ≥ 6 kΩ
S1 and S3, S2 and S4, and RH and RL should be ideally twisted shielded, with the shield tied to GND at the con verter.
Note : For 2V direct input use 10k Ω matched resistors for Ri & Rf.

FIGURE 8A. DIFFERENTIAL RESOLVER INPUT

SIN
3
Rf
Ri -S
1 -
S1
2
Ri +S
S3 6 +
5
Rf

RESOLVER A GND 4
INPUT COS
13 Note: The five external BW components as
Rf shown in FIGURE 1 and 2 are necessary
Ri -C for the R/D to function.
16
S4 -
15
Ri +C
7 +
S2
8 10
Rf
12
CONVERTER

S1 and S3, S2 and S4, and RH and RL should be ideally twisted shielded, with the shield tied to GNDat the converter. For DDC-49530
or DDC-57470: Ri = 70.8 kΩ, 11.8 V input, synchro or resolver. For DDC-49590: Ri = 270 kΩ, 90 V input, synchro or resolver. Maximum
addition error is 1 minute using recommended thin film pac kage.

Note on DC Offset Gains: Input options affect DC offset gains and theref ore affect carrier frequency r ipple and jitter. Offsets gains
associated with differential mode, (offset gain for differential configuration = 1 + RF/RI) and direct mode (offset gain f or direct config-
uration = 1), sho w differential will alw ays be higher . Higher DC offsets cause higher carr ier frequency r ipple due to demodulati on
process. This carrier frequency ripple because it is r iding on the top of the DC error signal causes jitter . A higher carrier frequency vs
bandwidth ratio will help decrease r ipple and jitter associated with offsets . Summary: R/D’s with differential inputs are more su scepti-
ble to offset problems than R/D’s in single ended mode. RD’s in higher resolutions, such as 16 bit, will further compound offset issues
due to higher inter nal voltage gains. Although the differential configuration has a higher DC offset gain, the diff erential configuration’s
common mode noise rejection mak es it the pref erred input option. The tradeoffs should be considered on a design to design basis .
Also refer to FAQ-GIQ-021.

FIGURE 8B. DIFFERENTIAL RESOLVER INPUT, USING DDC-49530, DDC-57470 (11.8 V),
DDC-73089 (2V), OR DDC-49590 (90 V)
Data Device Corporation RDC-19220 SERIES
www.ddc-web.com 11 R-12/05-0
 SIN

Rf
Ri -S
S1 -

Ri +S
S3 + Note: The five external BW components as
shown in FIGURE 1 and 2 are necessar y
Rf for the R/D to function.

A GND
COS
Ri
Rf / 3
Ri
-C
-

Ri /2 +C
S2 +

Rf / 3

CONVERTER

Ri x 2 Vrms = Synchro L-L r ms voltage

Rf
Rf ≥ 6 kΩ
S1, S2, and S3 should be triple twisted shielded; RH and RL should be twisted shielded, In both cases the shield should be tied to GND at the
converter.

FIGURE 9A. SYNCHRO INPUT

SIN
3
Rf
Ri -S
1
S1 -
2
Ri +S
6 +
S3
5
Rf Note: The five external BW components as
shown in FIGURE 1 and 2 are necessary
A GND 4 for the R/D to function.

COS
Ri 14
16
Rf / 3
Ri 8 -C
7
-
15 15
Ri /2 +C
9
S2 +
10
Rf / 3
11
CONVERTER
S1, S2, and S3 should be tr iple twisted shielded; RH and RL should be twisted shielded, In both cases the shield should be tied to GND at the converter.
90 V input = DDC-49590: Ri = 270 kΩ, 90 V input, synchro or resolver.
11.8 V input = DDC-49530 or DDC-57470: Ri = 70.8 kΩ, 11.8 V input, synchro or resolver.
Maximum addition error is 1 min ute.

FIGURE 9B. SYNCHRO INPUT, USING DDC-49530/DDC-57470 (11.8 V), DDC-73089 (2V) OR DDC-49590 (90 V)
Data Device Corporation RDC-19220 SERIES
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tor to an inverting integrator with a 50 pF nominal feedback capac- Magnitude of Error is in r adians
itor. When it integ rates to -1.25 V, the con verter counts up 1 LSB Quadrature Voltage is in volts
and when it integrates to +1.25 V, the con verter counts do wn 1 Full Scale signal is in v olts
LSB. When a count is taken, a charge is dumped on the capaci α = signal to REF phase shift

VELOCITY TRIMMING An example of the magnitude of error is as f ollows:

RDC-19220 Ser ies specifications f or v elocity scaling, re versal Let: Quadrature Voltage = 11.8 mV
error and offset are contained in TABLE 1. Velocity scaling and Let: F.S. signal = 11.8 V
offset are e xternally tr immable for applications requir ing tighter Let: α = 6°
specifications than those a vailable from the standard unit. FIG-
URE 10 sho ws the setup f or tr imming these par ameters with Then: Magnitude of Error = 0.36 min @ 1 LSB in the 16th bit.
external pots. It should also be noted that when the resolution is
changed, VEL scaling is also changed. Since the VEL output is Note: Quadrature is composed of static quadr ature which is
from an integrator with capacitor feedback, the VEL voltage can- specified by the synchro or resolver supplier plus the speed
not change instantaneously . Therefore, when changing resolu- voltage which is deter mined by the following formula:
tion while moving there will be a tr ansient with a magnitude pro-
portional to the v elocity and a dur ation deter mined by the con- Speed Voltage = (rotational speed/carr
ier frequency) • F.S. signal
verter bandwidth.
Where:
INCREASED TRACKING/DECREASED SETTLING
(GEAR SHIFTING) Speed Voltage is the quadrature due to rotation.
Connecting the BIT output to the resolution control lines (A and Rotation speed is the rps (rotations per second) of the synchro
B) will change the resolution of the con verter down (“gear shift”) or resolver.
and make the con verter settle f aster and tr ack at higher r ates. Carrier frequency is the REF in Hz.
The converter bandwidth is independent of the resolution.
PHASE SHIFT COMPENSATION
ADDITIONAL ERROR SOURCES FIGURE 11 illustr ates a circuit to LEAD or LA G the ref erence
Quadrature voltages in a resolver or synchro are b y definition the into the con verter that will compensate f or phase-shift betw een
resulting 90° fundamental signal in the nulled out error voltage (e)
in the converter. This voltage is due to capacitive or inductive cou- LAG

pling in the synchro or resolver signals. A digital position error will R

+ REF + REF
result due to the interaction of this quadrature voltage and a refer- C
ence phase shift betw een the con verter signal and ref erence - REF - REF

inputs. The magnitude of this error is giv

en in the following formula:

Magnitude of Error = (Quadrature Voltage/F.S.signal) • tan α LEAD

C
Where: + REF + REF
R
- REF - REF

RDC-19220
Xc
tan ϕ =
+5 V R
100 RV
100 kΩ
(OFFSET) Where ϕ = desired phase-shift
-5 V
-VCO 0.8 R V 1
Xc =
2πfc
0.4 RV (SCALING)
Where f = carrier frequency
VEL Where c = capacitance

FIGURE 10. VELOCITY TRIMMING FIGURE 11. PHASE-SHIFT COMPENSATION

Data Device Corporation RDC-19220 SERIES

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the signal and the reference to reduce the effects of the quadra- of the LVDT. The value of scaling constant “b” is selected to pro-
ture. This should be used for greater than 6° phase shift between vide an input of 1 Vrms at n ull of the L VDT. Suggested compo-
Ref and COS/SIN inputs. nents for implementing the input scaling circuit are a quad op-
amp, such as a 4741 type , and precision film resistors of 0.1%
LVDT MODE tolerance. FIGURE 12A illustrates a 2-wire LVDT configuration.
As shown in TABLE 1 the RDC-19220 Series units can be made
to oper ate as L VDT-to-digital con verters b y connecting Data output of the RDC-19220 Ser ies is Binar y Coded in LVDT
Resolution Control inputs A and B to “0,” “1,” or the -5 volt supply. mode. The most negativ e stroke of the L VDT is represented b y
In this mode the RDC-19220 Ser ies functions as a r atiometric all zeros and the most positive stroke of the LVDT is represent-
tracking linear converter. When linear ac inputs are applied from ed by all ones. The most significant 2 bits (2 MSBs) may be used
a LVDT the converter operates over one quarter of its range. This
results in two less bits of resolution for LVDT mode than are pro- TABLE 7. LVDT OUTPUT CODE (14-BIT R/D OR
vided in resolver mode. 12-BIT LVDT)

OVER MSB LSB

FIGURE 12B shows a direct LVDT 2 Vrms full scale input. Some LVDT OUTPUT
RANGE
LDVT output signals will need to be scaled to be compatible with DATA
the converter input. FIGURE 12C is a schematic of an input scal- + over full travel 01 xxxx xxxx xxxx
ing circuit applicab le to 3-wire L VDTs. The value of the scaling + full travel -1 LSB 00 1111 1111 1111
constant “a” is selected to provide an input of 2Vrms at full stroke +0.5 travel 00 1100 0000 0000
+1 LSB 00 1000 0000 0001
null 00 1000 0000 0000
- 1 LSB 00 0111 1111 1111
-0.5 travel 00 0100 0000 0000
C1 - full travel 00 0000 0000 0000
SIN - over full travel 11 xxxx xxxx xxxx
aR

2 WIRE LVDT -S Note: TABLE 7 refers to FIGURE 12C.

R
-
R
REF IN +S
R aR
+ FS = 2 V
C2 aR SIN
VB R
- -S
COS FS=2V R'
+S
bR R R
R + R'
2R aR
-C REF
R R bR
-
2R
+C 2R' R'
R COS
+ R
2V R - -C
VA
bR R'
R/2 -2V 2R'
+ +C
+REF
bR +REF
-REF
-REF

Notes;
C1 = C2, set for phase lag = phase lead through the L VDT. 1. R 10kΩ
2. Consideration for the value of R is LVDT loading.
3. RMS values given.
4. Use the absolute values of Va and Vb when subtracting per the formula for calculating
resistance values, and then use the calculated sign of "Va and Vb" for calculating SIN
FIGURE 12A. 2-WIRE LVDT DIRECT INPUT and COS. The calculations shown are based upon full scale travel being to the Va side
of the LVDT.
5. See the RDC application manual for calculation examples.
6. Negative voltages are 180˚ phase for the reference.

-S SIN
+S
b= 1 = 1
A GND VAnull VBnull
LVDT RDC-19220
-REF RDC-19220 OUTPUT a=
2
(VA - VB )max.
INPUT
2V SIN
+REF VA a
SIN=-1V+ (V - VB )
2 A 1V
+C VB
-C COS a
COS=-1V - (VA - VB ) COS
+FS NULL -FS 2
-FS NULL +FS

FIGURE 12B. 3-WIRE LVDT DIRECT INPUT FIGURE 12C. 3-WIRE LVDT SCALING CIRCUIT
Data Device Corporation RDC-19220 SERIES
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as overrange indicators. Positive overrange is indicated b y code the timing to CB “Figure 15” before setting the INH latch.
“01” and negativ e o verrange is indicated b y code “11” (see Therefore, there is no need to monitor the CB line when
TABLE 7). applying an inhibit signal to the con verter.

INHIBIT, ENABLE, AND CB TIMING BUILT-IN-TEST (BIT)

The Inhibit (INH) signal is used to freeze the digital output angle The Built-ln-Test output (BIT) monitors the level of error from the
in the tr ansparent output data latch while data is being tr ans- demodulator. This signal is the difference in the input and output
ferred. Application of an Inhibit signal does not interf ere with the angles and ideally should be zero. However, if it exceeds approx-
continuous tr acking of the con verter. As shown in FIGURE 13, imately 100 LSBs (of the selected resolution) the logic le vel at
angular output data is v alid 300 ns maxim um after the applica- BIT will change from a logic 1 to a logic 0.
tion of the negative inhibit pulse.
A 500ms dela y occurs bef ore the e xcessive error bit becomes
Output angle data is enab led onto the tr i-state data b us in tw o active. The dynamic delay is responsive to the active filler loop.
bytes. Enable MSBs (EM) is used for the most significant 8 bits
and Enable LSBs (EL) is used f or the least significant 8 bits . As This condition will occur dur ing a large step and reset after the
shown in FIGURE 14, output data is valid 150 ns maximum after converter settles out. BIT will also change to logic 0 f or an over-
the application of a negative enable pulse. The tri-state data bus velocity condition, because the con verter loop cannot maintain
returns to the high impedance state 100 ns maxim um after the input/output or if the con verter malfunctions where it cannot
rising edge of the enable signal. maintain the loop at a n ull.

The Converter Busy (CB) signal indicates that the tr acking con- BIT will also be set low for a detected total Loss-of-Signal (LOS).
verter output angle is changing 1 LSB. As shown in FIGURE 15, The BIT signal ma y pulse dur ing cer tain error conditions (i.e .,
output data is v alid 50 ns maxim um after the middle of the CB converter spin around or signal amplitude on threshold of LOS).
pulse. CB pulse width is 1/(40 x Fs), which is nominally 375 ns .
LOS will be detected if both sin and cos input v oltages are less
Note: The converter INH may be applied regardless of the CB than 800 mV peak. The LOS has a filter on it to filter out the ref-
line state. If the CB is b usy the converter INH will wait for erence. Since the lowest specified frequency is 47hz (-27ms) the
filter m ust ha ve a time constant long enough to filter this out.
Time constants of 50ms or more are possib le.
INHIBIT

ENCODER EMULATION
300 ns max The RDC-19220 ser ies can be made to em ulate incremental
optical encoder output signals , where such an interf ace is
desired. This is accomplished b y tying EL to -5 V, whereby CB
DATA
DATA VALID becomes Zero Index (Zl) Logic 1 at all 0s , the LSB+1 becomes
A, and the exclusive-or of the LSB and LSB+1 becomes B em u-
FIGURE 13. INHIBIT TIMING lating A QUAD B signals as illustrated in FIGURE 16A. Also, the
LSB byte is always enabled.

ENABLE
1/ (40 x FS )
(375 nsec nominal)
150 ns MAX
100 ns MAX CB
*
DATA HIGH Z DATA HIGH Z
VALID 50 ns

Note: For 16 BIT BUS operation, EM/EL may be tied to ground

DATA DATA
for transparent mode, as long as only 1 R/D channel is on DATA VALID VALID
the data bus.

* Next CB pulse cannot occur for a minimum of 150 nsec.

FIGURE 14. ENABLE TIMING FIGURE 15. CONVERTER BUSY TIMING
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 CB (ZI) (ZI)
LSB +1 A

B
LSB

EL

-5 V
FIGURE 16A. INCREMENTAL ENCODER EMULATION

R2 U2D
2k 74AC86
13
C2 11
RDC-19220 220 pF A
12

U2A
74AC86 R1 U2B
LSB +1 2 2k 74AC86
3 4
1 C1 6 B
LSB 220 pF 5

R3 U2C
2k 74AC86
9
CB/NRP
C3 8
120 pF 10 NRP
EL
D1
1N4148

-5 V
NOTE: CMOS LOGIC IS RECOMMENDED. TTL AND TTL
COMPATIBLE LOGIC WILL SKEW THE DELAYS.

FIGURE 16B. FILTERED/BUFFERED ENCODER EMULATOR CIRCUIT

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TYPICAL -5 VOLT CIRCUITS TABLE 9. RDC-19222 PINOUTS (44-PIN, +5 V ONLY)
Since the 40-pin DDIP RDC-19220 does not have a pinout f or
# NAME # NAME
the -5 V inverter, it may be necessary to create a -5 V from other
1 EL 23 -CAP
supplies on the board. FIGURE 17 illustr ates several possibili-
2 +5 V 24 GND
ties.
3 A 25 +CAP
PINOUT FUNCTION TABLES BY MODEL NUMBER 4 B 26 +5C (+5V)
TABLES 8 ,9, and 10 detail pinout functions b y the DDC model 5 INH 27 BIT
number. 6 +REF 28 CB
7 -REF 29 Bit 1 (MSB)
-15 79LO5 -5 8 -VCO 30 Bit 9
9 -VSUM 31 Bit 2
10 VEL 32 Bit 10
3 TERMINAL
NEGATIVE REGULATOR 11 +C 33 Bit 3
12 COS 34 Bit 11
-5
-15 -5 13 -C 35 Bit 4
10.2 V 14 +S 36 Bit 12
ZENER
5.1 V 15 SIN 37 Bit 5
ZENER
16 -S 38 Bit 13
-12 -5
-15 17 -5 V 39 Bit 6
6.8 V
ZENER 18 RS 40 Bit 14
FIGURE 17. TYPICAL -5 VOLT CIRCUITS 19 RC 41 Bit 7
20 EM 42 Bit 15
TABLE 8. RDC-19220 PINOUTS (40-PIN) 21 A GND 43 Bit 8
# NAME DESCRIPTION # NAME DESCRIPTION 22 -5C (-5 V) 44 Bit 16 (LSB)
1 A Resolution Control 40 +5 V Power Supply
Enable LSBs (see TABLE 10. RDC-19224 PINOUTS (44-PIN)
2 B Resolution Control 39 EL
note)
3 INH Inhibit 38 Bit 16 LSB # NAME # NAME

4 +REF +Reference Input 37 Bit 8 1 -REF 23 BIT 1 (MSB)

5 -REF -Reference Input 36 Bit 15 2 -VCO 24 BIT 9

6 -VCO Neg VCO Input 35 Bit 7 3 -VSUM 25 BIT 2

7 -VSUM Vel Sum Point 34 Bit 14 4 VEL 26 BIT 10

8 VEL Velocity Output 33 Bit 6 5 +C 27 BIT 3

9 +C Signal Input 32 Bit 13 6 COS 28 BIT 11

10 COS Signal Output 31 Bit 5 7 -C 29 BIT 4

11 -C Signal Input 30 Bit 12 8 +S 30 BIT12

12 +S Signal Input 29 Bit 4 9 SIN 31 BIT 5

13 +SIN Signal Output 28 Bit 11 10 -S 32 BIT13

14 -S Signal Input 27 Bit 3 11 -5V 33 BIT 6

15 -5 V Power Supply 26 Bit 10 12 RS 34 BIT 14

16 RS Sampling Set 25 Bit 2 13 RC 35 BIT 7

17 RC Current Set 24 Bit 9 14 EM 36 BIT 15

18 EM Enable MSBs 23 Bit 1 MSB 15 A GND 37 BIT 8

19 A GND Analog Ground 22 CB Converter Busy 16 -5C (-5V) 38 BIT 16 (LSB)

20 GND Ground 21 BIT Built-In-Test 17 -CAP 39 EL

18 GND 40 +5V
19 +CAP 41 A
20 +5C (+5V) 42 B
21 BIT 43 INH
22 CB 44 +REF

Data Device Corporation RDC-19220 SERIES

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 PIN NUMBERS
FOR REF ONLY
0.125 ±0.020
(3.18 ±0.508)
0.590 ±0.010 0.115 ±0.010
(14.99 ±0.25) (2.921 ±0.25) 0.050 ±0.010
(1.27 ±0.25)

1 40

0.100 ±0.010 TYP

(2.54 ±0.25)

0.018 ±0.006 TYP

2.000 ±0.020 (0.46 ±0.15)
(50.8 ±0.51)

0.050 ±0.020 TYP

(1.27 ±0.51)

20 21

0.012 ±0.004 TYP

(0.31 ±0.10)

DIMENSIONS SHOWN ARE IN INCHES (MM).

+0.050
0.095 ±0.010 0.600 - 0.020
(2.41 ±0.25) +1.27
(15.25 - 0.51 )

FIGURE 18. RDC-19220 (40-PIN DDIP) CERAMIC PACKAGE MECHANICAL OUTLINE

Data Device Corporation RDC-19220 SERIES

www.ddc-web.com 18 R-12/05-0
 PIN 1 IDENTIFIER
PIN #'S SHOWN
FOR REFERENCE ONLY ALTERNATE PIN 1 IDENTIFIER

6 40 5
200
3,
Q
UED
IN .155 MAX .020 MIN
NT (3.94)
O
SC
0.690 SQ. ±.005
DI
(17.53) .620 SQ
± .010
0.650 SQ. NOM LCC (15.75)
(16.51) P
.016 ± .005 (.41)

DIMENSIONS SHOWN ARE IN INCHES (MM) TOLERANCE IN INCHES

0.010 x 45˚ CHFR (3)
(0.25)
.050 ± .002
(1.27)

FIGURE 19. RDC-19222 (44-PIN PLASTIC J-LEAD) MECHANICAL OUTLINE

0.075 ±0.010
(1.91 ±0.25) 0.040 x 45˚
CHAMFER
0.500 ±0.010 (1.02)
0.020 x 45˚ (12.70 ±0.25) (3 PLACES)
0.143 ± 10 (REF)
(0.51) (3.63)
CHAMFER 0.050 TYP
(ORIENTATION (1.27) 0.095 ±0.007
MARK) (2.413 ±0.18)
6 1 40

7 39

0.630 ±0.020 TYP

(16.00 ±0.51)
0.500 ±0.010
(12.70 ±0.25)

0.017 TYP
(0.43)

17 29

18 28 PIN NUMBERS
FOR REF ONLY
0.075 ±0.010
(1.91 ±0.25) 0.650 SQ ±0.010
(16.51 ±0.25)

0.690 ±0.010 TYP DIMENSIONS SHOWN ARE IN INCHES (MM)

(17.53 ±0.25)
FIGURE 20. RDC-19222 (44-PIN CERAMIC J-LEAD) MECHANICAL OUTLINE
Data Device Corporation RDC-19220 SERIES
www.ddc-web.com 19 R-12/05-0
 D

D1

E E1
c

TOP VIEW

0.012 R (TYP)
(0.30)
A2 A
.009 (0.23) MAX
.005 (0.13) MIN
A1 L
0.008 R (TYP)
(0.20)

DIMENSIONS ARE IN INCHES (MM)

A A1 A2 D D1 E E1 L c b
.092 0.0039 0.0098 .078 .520 .394 .520 .394 .035 .0315 .0138
INCHES + .004 ± .010 ± .004 + .006
± .010 ± .004 BSC +.0020
MAX MIN MAX
- .002 - .004
2.35 .10 .25 2.00 13.20 10.00 13.20 10.00 .88 .80 .35
MM + .10 ± .25 ± .10 ± .25 ± .10 + .15 BSC +.05
MAX MIN MAX
- .05 - .10

FIGURE 21. RDC-19224 (44-PIN PLASTIC MQFP) MECHANICAL OUTLINE

Data Device Corporation RDC-19220 SERIES

www.ddc-web.com 20 R-12/05-0
ORDERING INFORMATION
RDC-1922X-XXXX (Ceramic Package)

Supplemental Process Requirements:

T = Tape and Reel (Not available in 40-pin DDIP package)
S = Pre-Cap Source Inspection
L = 100% Pull Test
Q = Pre-Cap Source and 100% Pull Test
K = One Lot Date Code
W = One Lot Date Code and Pre-Cap Source Inspection
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code , Pre-Cap Source Inspection and 100% Pull Test
Blank = None of the Abo ve

Accuracy:
2= 4 minutes + 1 LSB
3 = 2 minutes + 1 LSB

Process Requirements:
0 = Standard DDC Processing, without Bur n-In
1 = MIL-PRF-38534 Compliant
2 = Standard DDC Processing, with Bur n-In
3 = MIL-PRF-38534 Compliant, with PIND testing
4 = MIL-PRF-38534 Compliant, with Solder Dip (Not a vailable in lead free.)(Note 4)
5 = MIL-PRF-38534 Compliant, with PIND testing, and Solder Dip (Not a vailable in lead free.)(Note 4)
6 = Standard DDC Processing, with PIND testing, and Burn-In
7 = Standard DDC Processing, with Solder Dip , and Burn-In (Not available in lead free.)(Note 4)
9 = Standard DDC Processing, with Solder Dip , without Burn-In (Not available in lead free.)(Note 4)

Temperature Grade / Data Requirements:

1 = -55 to +125°C
4 = -55 to +125°C, with Variables Test Data

Package: (Lead Free) (Note 3)

0 = 40-Pin DDIP, (“+5 volt only” power supply feature - not available)
2 = 44-Pin J-Lead

STANDARD DDC PROCESSING

FOR HYBRID AND MONOLITHIC HERMETIC PRODUCTS
MIL-STD-883
TEST
METHOD(S) CONDITION(S)
INSPECTION 2009, 2010, 2017, and 2032 —
SEAL 1014 A and C
TEMPERATURE CYCLE 1010 C
CONSTANT ACCELERATION 2001 3000g
BURN-IN 1015 (note 1), 1030 (note 2) TABLE 1

Notes:
1. For Process Requirement "B*" (refer to ordering information), devices may be non-compliant with
MIL- STD-883, Test Method 1015, Paragraph 3.2. Cont act factory for details.
2. When applicable.
3. Consult factory for lead-time of lead free product.
4. Solder dip options contain tin-lead solder finish as applicable to solder dip requirement s.

External Component Selection Software (refer to General Setup

Conditions section) can be downloaded from DDC’s web site:
www.ddc-web.com.

Data Device Corporation RDC-19220 SERIES

www.ddc-web.com 21 R-12/05-0
ORDERING INFORMATION
RDC-19224_ -XXXX (Plastic Package:)

Supplemental Process Requirements:

T = Tape and Reel (Note 2)
Blank = None of the Abo ve

Accuracy:
2 = 4 minutes + 1 LSB
3 = 2 minutes + 1 LSB

Process Requirements:
0 = No Bur n-In
9 = Solder Dip, without Burn-In (Note 3)

Temperature Grade:
2 = -40 to +85°C
3 = 0 to +70°C
A = -40 to +125°C

Package Options: (Note 1)

Blank = Standard
G = Lead free

Package Type:
2 = PLCC 44-Pin J-Lead (Discontin ued Q3, 2005)
4 = MQFP 44-Pin (Available January 3, 2006)

Note 1: The lead-free option is available with a Matte Tin finish. DDC can provide the reliability
and tin whisker growth data associated with these products ; however, tin whisker growth is
dependent on the application enviornment and customers should collect their o wn reliability data
and perform a risk assesment based on their individual requirements .
Note 2: DDC does not recommend Tape and Reel due to potential lead damage .
Note 3: Solder DIP is not available on the MQFP package.

THIN FILM RESISTOR NETWORKS

FOR MOTION FEEDBACK PRODUCTS

Description

DDC converters such as the RDC-19220 ser ies require closely matched 2Vrms Sin/Cos input voltages to minimize digital error. DDC
has custom thin film resistor networks that provide the correctly matched 2Vrms converter outputs for 11.8Vrms Resolver/Synchro or
90Vrms synchro applications.

Any imbalance of the resistance ratio between the Sin/Cos inputs will create errors in the digital output. DDC’s custom thin film resis-
tor networks have very low imbalance percentages. The networks are matched to 0.02%, which equates to 1LSB of error f or a 16-bit
application.
THIN FILM RESISTOR INPUT VOLTAGE OUTPUT VOLTAGE
PACKAGE TYPE
NETWORK (VRMS) (VRMS)

DDC-55688-1 2 Single Ended 2 Ceramic DIP

DDC-49530 11.8 2 Plastic DIP

DDC-57470 11.8 2 Surface Mount

DDC-49590 90 2 Ceramic DIP

DDC-73089 2 Differential 2 Surface Mount

DDC-57471 90 2 Surface Mount

Note: For thin film network specifications see the “Thin Film Network Specifications for Motion Feedback Products”
Data Sheet available from the DDC website. (Operating Temperature Range : -55 to +125°C)

Data Device Corporation RDC-19220 SERIES

www.ddc-web.com 22 R-12/05-0
 The information in this data sheet is belie ved to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or r ights are
granted by implication or otherwise in connection there with.
Specifications are subject to change without notice .

Please visit our web site at www.ddc-web.com for the latest information.

105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2482

For Technical Support - 1-800-DDC-5757 ext. 7771

Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358

Southeast, U.S.A. - Tel: (703) 450-7900, Fax: (703) 450-6610
West Coast, U.S.A. - Tel: (714) 895-9777, Fax: (714) 895-4988
United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264
Ireland - Tel: +353-21-341065, Fax: +353-21-341568
France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425
Germany - Tel: +49-(0) 89-150012-11, Fax: +49-(0) 89-150012-22
Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
World Wide Web - http://www.ddc-web.com

U
REG

RM

®
ST
FI
I

ERED
DATA DEVICE CORPORATION
REGISTERED TO ISO 9001:2000
FILE NO. A5976

R-12/05-0 23 PRINTED IN THE U.S.A.