a 10-Bit, 100 MSPS

A/D Converter
AD9070
FEATURES FUNCTIONAL BLOCK DIAGRAM
10-Bit, 100 MSPS ADC
Low Power: 600 mW Typical at 100 MSPS VREF VREF REF
On-Chip Track/Hold IN OUT COMP BYPASS

230 MHz Analog Bandwidth SOIC (BR)

SINAD = 54 dB @ 41 MHz AD9070 –2.5V PACKAGE
ONLY
On–Chip Reference
1 V p-p Analog Input Range AIN
T/H ADC 10
Single Supply Operation: +5 V or –5 V AIN
D9 – D0
Differential Clock Input SUM DAC
ENCODE
LOGIC
Available in Standard Military Drawing Version AMP

ENCODE OR
APPLICATIONS ENCODE
TIMING ADC
DIP
Digital Communications PACKAGE
ONLY
Signal Intelligence VEE GND
Digital Oscilloscopes
Spectrum Analyzers
Medical Imaging
Radar
HDTV

GENERAL DESCRIPTION The input amplifier supports single-ended interfaces. An

The AD9070 is a monolithic sampling analog-to-digital internal –2.5 V reference is included in the SOIC packaged
converter with an on-chip track-and-hold circuit and ECL device (an external voltage reference is required for the DIP
digital interfaces. The product operates at a 100 MSPS version).
conversion rate with outstanding dynamic performance over Fabricated on an advanced bipolar process, the AD9070
its full operating range. is available in a plastic SOIC package specified over the
The ADC requires only a single –5 V supply and an encode industrial temperature range (–40°C to +85°C), and a full
clock for full performance operation. The digital outputs are MIL-PRF-38534 QML version (–55°C to +125°C) in a
ECL compatible, while a differential clock input accommodates ceramic Dual-in-Line Package (DIP).
a wide range of logic levels. The AD9070 may be operated in a
Positive ECL (PECL) environment with a single +5 V supply.
An Out-of-Range output (OR) is available in the DIP version to
indicate that a conversion result is outside the operating range.
In both package styles, the output data are held at saturation
levels during an out-of-range condition.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000
 (VEE = –5 V, ENCODE = 100 MSPS, outputs loaded with 100 ⍀ to –2 V unless
AD9070–SPECIFICATIONS otherwise noted)
Test AD9070BR 5962-9756301HXC
Parameter Temp Level Min Typ Max Min Typ Max Units

RESOLUTION 10 10 Bit

DC ACCURACY
Differential Nonlinearity +25°C I ± 0.6 +1.25/–1.0 ± 0.6 +1.25/–1.0 LSB
Full VI ± 0.7 +1.5/–1.0 ± 0.9 +2.00/–1.0 LSB
Integral Nonlinearity +25°C I ± 0.6 ± 1.5 ± 0.6 ± 1.5 LSB
Full VI ± 0.9 ± 1.5 ± 2.25 LSB
No Missing Codes Full VI Guaranteed Guaranteed
Gain Error1 +25°C I ±1 ±4 ±1 ±4 % FS
Full VI ±2 ±6 % FS
Gain Tempco1 Full V 115 130 ppm/°C

ANALOG INPUT
Input Voltage Range (with Respect to AIN) Full V ± 512 ± 512 mV p-p
Common-Mode Voltage Full V –2.5 ± 0.2 –2.5 ± 0.2 V
Input Offset Voltage +25°C I ±7 ± 18 ±7 ± 18 mV
Full I ±8 ±9 ± 20 mV
Input Resistance +25°C I 10 40 10 40 kΩ
Full I 40 10 40 kΩ
Input Capacitance +25°C V 3 3 pF
Input Bias Current +25°C I 75 200 75 200 µA
Full I 75 75 200 µA
Analog Bandwidth, Full Power +25°C V 230 230 MHz

REFERENCE OUTPUT
Output Voltage Full VI –2.4 –2.5 –2.6 N/A V
Temperature Coefficient Full V 170 N/A ppm/°C

SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 100 100 MSPS
Minimum Conversion Rate Full IV 40 40 MSPS
Encode Pulse Width High (t EH) +25°C IV 4.5 13 4.5 13 ns
Encode Pulse Width Low (t EL) +25°C IV 4.5 13 4.5 13 ns
Aperture Delay (tA) +25°C V 0.85 0.85 ns
Aperture Uncertainty (Jitter) +25°C V 2.5 2.5 ps rms
Output Valid Time (tV)2 Full VI 1.5 2.6 1.5 2.6 ns
Output Propagation Delay (t PD)2 Full VI 3.0 4.0 3.0 4.0 ns
Output Rise Time (tR) Full VI 0.5 0.5 1.2 ns
Output Fall Time (tF) Full VI 0.5 0.5 1.2 ns

DIGITAL INPUTS
Logic “1” Voltage Full IV –1.1 –0.4 –1.1 –0.4 V
Logic “0” Voltage Full IV –1.5 –1.5 V
Logic “1” Current Full VI ± 10 ± 10 µA
Logic “0” Current Full VI ± 10 ± 10 µA
Input Capacitance +25°C V 3 3 pF

DIGITAL OUTPUTS
Logic “1” Voltage Full VI –1.1 –1.15 V
Logic “0” Voltage Full VI –1.65 –1.60 V
Output Coding Twos Complement Twos Complement

POWER SUPPLY
VEE Supply Current (VEE = –5 V) Full VI 80 120 150 80 120 150 mA
Power Dissipation3 Full VI 400 600 750 400 600 750 mW
Power Supply Sensitivity 4 +25°C I 0.005 0.012 0.005 0.012 V/V

–2– REV. B
 AD9070
Test AD9070BR 5962-9756301HXC
Parameter Temp Level Min Typ Max Min Typ Max Units

DYNAMIC PERFORMANCE 5
Transient Response +25°C V 3 3 ns
Overvoltage Recovery Time +25°C V 4 4 ns
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 10.3 MHz +25°C I 55 57 55 57 dB
Full V 56 55 dB
fIN = 41 MHz +25°C I 54 56 54 56 dB
Full V 55 54 dB
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
fIN = 10.3 MHz +25°C I 54 56 54 56 dB
Full V 55 54 dB
fIN = 41 MHz +25°C I 51 54 51 54 dB
Full V 53 52 dB
Effective Number of Bit
fIN = 10.3 MHz +25°C I 8.8 9.2 8.8 9.2 Bits
fIN = 41 MHz +25°C I 8.3 8.9 8.3 8.9 Bits
2nd Harmonic Distortion
fIN = 10.3 MHz +25°C I 63 70 63 70 dBc
fIN = 41 MHz +25°C I 58 63 58 63 dBc
3rd Harmonic Distortion
fIN = 10.3 MHz +25°C I 65 71 65 71 dBc
fIN = 41 MHz +25°C I 57 61 57 61 dBc
Two-Tone Intermod Distortion (IMD)
fIN = 10.3 MHz +25°C V 70 70 dBc
fIN = 41 MHz +25°C V 60 60 dBc
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed –2.5 V external reference).
2
tV and tPD are measured from the threshold crossing of the ENCODE input to the 50% levels of the digital outputs. The output ac load during test is 10 pF.
3
Power dissipation is measured under the following conditions: f S 100 MSPS, analog input is –1 dBfs at 10.3 MHz. Power dissipation does not include the current of
the external ECL pull-down resistors that set the current in the ECL output followers.
4
A change in input offset voltage with respect to a change in V EE.
5
SNR/harmonics based on an analog input voltage of –1.0 dBfs referenced to a 1.024 V full-scale input range.
Typical thermal impedance for the R style (SOIC) 28-lead package: θJC = 23°C/W, θCA = 48°C/W, θJA = 71°C/W.
Typical thermal impedance for the DH style (Ceramic DIP) 28-lead package: θJC = 8°C/W, θCA = 43°C/W, θJA = 51°C/W.
Contact DSCC to obtain the latest revision of the 5962-9756301 drawing.
Specifications subject to change without notice.

SAMPLE N–1 SAMPLE N SAMPLE N+3 SAMPLE N+4

AIN

SAMPLE N+1 SAMPLE N+2

tA
tEH tEL 1/fs
ENCODE

ENCODE
tPD tV

D9–D0 DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N DATA N+1

Figure 1. Timing Diagram

REV. B –3–
AD9070
ABSOLUTE MAXIMUM RATINGS* Table I. Output Coding
VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . VEE –1 V to +1.0 V Twos
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE to 0.0 V Step AIN–AIN Code Complement OR
VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . . VEE to 0.0 V
1024 ≥ 0.512 V >511 01 1111 1111 1
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
1023 0.511 V 511 01 1111 1111 0
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
1022 0.510 V 510 01 1111 1110 0
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
• • • • •
Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C
• • • • •
Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150°C
• • • • •
*Stresses above those listed under Absolute Maximum Ratings may cause perma- 513 0.001 V 1 00 0000 0001 0
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
512 0.000 V 0 00 0000 0000 0
sections of this specification is not implied. Exposure to absolute maximum ratings 511 –0.001 V –1 11 1111 1111 0
for extended periods may affect device reliability. • • • • •
• • • • •
• • • • •
EXPLANATION OF TEST LEVELS 1 –0.511 V –511 10 0000 0001 0
Test Level 0 –0.512 V –512 10 0000 0000 0
I – 100% production tested. –1 ≤ –0.513 V <512 10 0000 0000 1
II – 100% production tested at +25°C and sample tested at
specified temperatures.
III – Sample tested only. ORDERING GUIDE
IV – Parameter is guaranteed by design and characterization
Model Temperature Range Package Option*
testing.
V – Parameter is a typical value only. AD9070BR –40°C to +85°C R-28
AD9070/PCB +25°C Evaluation Board
VI – 100% production tested at +25°C; guaranteed by design 5962-9756301HXC –55°C to +125°C DH-28
and characterization testing for industrial temperature
range; 100% production tested at temperature extremes *DH = Ceramic DIP; R = Small Outline IC (SOIC).
for military devices.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD9070 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. B
 AD9070
PIN FUNCTION DESCRIPTIONS

Pin Numbers
AD9070BR AD9070DIP
R Package D Package Name Function

1, 7, 12, 21, 23 1, 7, 9, 14, 21 VEE Negative Power Supply. Nominally –5.0 V.

2, 8, 11, 20, 22 2, 6, 8, 10, 13, 15, 22 GND Ground.
3 N/A VREF OUT Internal Reference Output (–2.5 V typical); Bypass with 0.1 µF to Ground.
4 3 VREF IN Reference Input for ADC (–2.5 V typical).
5 N/A COMP Internal Amplifier Compensation, 0.1 µF to VEE.
6 N/A REF BYPASS Reference Bypass Node, 0.1 µF to VEE.
9 4 AIN Analog Input – Complement.
10 5 AIN Analog Input – True.
13 11 ENCODE Encode Clock for ADC (ADC Samples on Rising Edge of ENCODE).
14 12 ENCODE Encode Clock Complement (ADC Samples on Falling Edge of ENCODE).
28–24, 19–15 27–23, 20–16 D9–D0 Digital Outputs of ADC. D9 is the MSB. Data is twos complement.
N/A 28 OR Out-of-Range Output. Goes HIGH when the converted sample is more
positive than 1FFh or more negative than 200h (Twos Complement Coding).

PIN CONFIGURATIONS

SOIC Ceramic DIP

VEE 1 28 D9 (MSB) VEE 1 28 OR

GND 2 27 D8 GND 2 27 D9 (MSB)

VREF OUT 3 26 D7 VREF IN 3 26 D8

VREF IN 4 25 D6 AIN 4 25 D7

COMP 5 24 D5 AIN 5 24 D6

REF BYPASS 6 AD9070BR 23 VEE GND 6 AD9070DIP 23 D5

VEE 7 TOP VIEW 22 GND VEE 7 TOP VIEW 22 GND
(Not to Scale) (Not to Scale)
GND 8 21 VEE GND 8 21 VEE

AIN 9 20 GND VEE 9 20 D4

AIN 10 19 D4 GND 10 19 D3

GND 11 18 D3 ENCODE 11 18 D2

VEE 12 17 D2 ENCODE 12 17 D1

ENCODE 13 16 D1 GND 13 16 D0 (LSB)

ENCODE 14 15 D0 (LSB) VEE 14 15 GND

REV. B –5–
AD9070–Typical Circuit Applications

AIN AIN
D9 – D0
OR

VEE VEE

Figure 2. Equivalent Analog Input Circuit Figure 5. Equivalent Digital Output Circuit

VREF
OUT
VREF IN

VEE

VEE
Figure 6. Equivalent Reference Output Circuit

Figure 3. Equivalent Reference Input Circuit

ENCODE ENCODE

VEE

Figure 4. Equivalent Encode Input Circuit

–6– REV. B
 Typical Performance Characteristics–AD9070
0 0

FUNDAMENTAL = –1.0dBfs –10 F1 = 40.1MHz

–10
SNR = 58.5dB F2 = 41.0MHz
–20 SINAD = 58.0dB –20 F1 = F2 = –7.0dBfs
2nd HARMONIC = –76.8dB
–30 3rd HARMONIC = –68.1dB –30

–40 –40

dB
–50
dB

–50

–60 –60

–70 –70

–80 –80

–90 –90

–100 –100
0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50
MHz MHz

Figure 7. Spectrum: fS = 100 MSPS, fIN = 10 MHz Figure 10. Two Tone Intermodulation Distortion

0 60
FUNDAMENTAL = –1.0dBfs
–10 55
SNR = 56.8dB
SINAD = 55.0dB SNR
–20
2nd HARMONIC = –66.6dB 50
–30 3rd HARMONIC = –60.8dB

45
–40 SINAD

dB
40
dB

–50
NYQUIST
–60 35 FREQUENCY
(50 MHz)
–70
30
–80
25
–90

–100 20
0 5 10 15 20 25 30 35 40 45 50 0 20 40 60 80 100 120 140 160
MHz FIN – MHz

Figure 8. Spectrum: fS = 100 MSPS, fIN = 40 MHz Figure 11. SNR vs. fIN; fS = 100 MSPS

0 60

F1 = 9.57MHz 58
–10
F2 = 10.3MHz
SNR
F1 = F2 = –7.0dBfs 56
–20 SINAD
–30 54

–40 52
dB

50
dB

–50

–60 48

–70 46

44
–80

–90 42

–100 40
0 5 10 15 20 25 30 35 40 45 50 0 20 40 60 80 100 120 140 160
MHz FS – MSPS

Figure 9. Two Tone Intermodulation Distortion Figure 12. SNR vs. fS: fIN = 10.3 MHz

REV. B –7–
AD9070
60 60

59 59

SNR 58
58
57
57
SINAD
56
56

dB
55
55
dB

FS = 100MSPS
FS = 100MSPS 54
54 FIN = 10.1MHz
FIN = 10.1MHz
53
53
52
52
51
51
50
50 0 1 2 3 4 5 6 7 8 9 10
–60 –40 –20 0 20 40 60 80 100 120 140 ENCODE PULSEWIDTH – ns
T C – ⴗC

Figure 13. SNR vs. TC: BR Package (SOIC) Figure 15. SNR vs. Clock Pulse Width (tEH)

60 0

59
SNR –1
58

57
SINAD
56
dB –2

55 NYQUIST
dB

FREQUENCY
FS = 100MSPS –3 50MHz
54
FIN = 10.1MHz
53
–4
52

51
–5
50 0 50 100 150 200 250 300
–60 –40 –20 0 20 40 60 80 100 120 140 FIN – MHz
T C – ⴗC

Figure 14. SNR vs. TC: DIP Package Figure 16. Frequency Response

–8– REV. B
 AD9070
APPLICATION NOTES recommended. A better approach is to develop the required
Theory of Operation voltage from the internal or external converter voltage reference
The AD9070 employs a two-step subranging architecture with (VREF OUT).
digital error correction. Very small timing errors can reduce the performance of an A/D
The sampling and conversion process is initiated by a rising dramatically. Total jitter of only 3.2 ps will limit the perfor-
edge at the ENCODE input. The analog input signal is mance of an A/D sampling a full-scale 50 MHz signal to nine
buffered by a high speed differential amplifier and applied to a effective bits. The AD9070’s specified aperture jitter of 2.5 ps
track-and-hold (T/H) circuit that captures the value of the leaves only 2.0 ps of jitter budget for the clock source (an RSS
input at the sampling instant and maintains it for the duration calculation).
of the conversion. The cleanest clock source is only a crystal oscillator producing a
The coarse quantizer (ADC) produces a five-bit estimate of the pure sine wave. In this configuration, or with any roughly
input value. Its digital output is reconverted to analog form by symmetrical clock input, the input can be ac coupled and biased
the reconstruction DAC and subtracted from the input signal in to a reference voltage that also provides the ENCODE input
the SUM AMP. The second stage quantizer generates a six-bit (Figure 17). This ensures that the reference voltage is centered
representation of the difference signal. The eleven bits are on the ENCODE signal.
presented to the ENCODE LOGIC, which corrects for range Digital Outputs
overlap errors and produces an accurate ten-bit result. The digital outputs are compatible with 10K ECL logic. The
Data are strobed to the output on the rising edge of the ENCODE suggested pull-down is 100 Ω to –2 V. However, to reduce
input, with the data from sample N appearing on the output power consumption, higher value pull-down resistors can be
following ENCODE rising edge N+3. used when driving very low capacitance loads or at reduced
encode rates. The falling edge slew rate of the output bits will be
USING THE AD9070 degraded with higher value pull-down resistors.
ENCODE Input Analog Input
Any high speed A/D converter is extremely sensitive to the quality The analog input to the AD9070 is a differential amplifier, but
of the sampling clock provided by the user. A Track/Hold circuit is the design has been optimized for a single-ended input. The
essentially a mixer, and any noise, distortion or timing jitter on AIN input should be connected or bypassed to the ground
the clock will be combined with the desired signal at the A/D reference of the input signal. For best dynamic performance,
output. For that reason, considerable care has been taken in the impedances at AIN and AIN should match.
design of the ENCODE input of the AD9070 and the user is
The circuit in Figure 18 illustrates a simple ac-coupled inter-
advised to give commensurate thought to the clock source.
face. The midscale input voltage and the AIN levels are both
The ENCODE input is fully differential and may be operated in provided by the internal reference (VREF OUT).
a differential or a single-ended mode. It has a common-mode
range of –1 V to –3 V, and is easily driven by a differential ECL
driver. Proper termination at the A/D is important.
0.1␮F GND
VIN
–5V 1Vp-p AIN
AD9070
RT 500⍀ AIN
(MSB) D9 D9
500⍀ 510⍀
VEE GND (OR 100⍀ TO –2V)
VREF OUT
AD9070 0.1␮F VREF IN –5V
0.1␮F
CLKIN
ENCODE (LSB) D0 D0
(1Vp-p) ENCODE ENCODE
RT 10k⍀ 510⍀
ENCODE ENCODE (OR 100⍀ TO –2V)
ENCODE REF
VEE BYPASS
COMP –5V
0.1␮F 1k⍀ 3k⍀
0.1␮F 0.1␮F
–5V

Figure 17. Single-Ended ENCODE: AC Coupled –5V

In single-ended mode, the ENCODE input must be tied to an Figure 18. AD9070 in –5 V (ECL) Environment
appropriate reference voltage, generally midway between the
high and the low levels of the incoming logic signal. Many ECL
circuits provide a VBB reference voltage intended for this
purpose. If a reference voltage is produced by dividing the
power supply voltage, any noise on the supply used will couple
to the clock input and then to the output data. This is not

REV. B –9–
AD9070
Figure 19 shows typical connections for the analog inputs when The input is protected to one volt outside of the power supply
using the AD9070 in a dc-coupled system with single-ended rails. For nominal power (–5 V and ground), the analog input
signals. The AD820 is used to offset the ground referenced will not be damaged with signals ranging from –6.0 V to +1.0 V.
input signal to the level required by the AD9070. A very high Voltage Reference
performance amplifier, such as the AD9631, is required to avoid A stable and accurate –2.5 V voltage reference is built into the
degrading the analog signal presented to the ADC. A buffered AD9070 (VREF OUT) in the SOIC (BR) package. In normal
ac interface is easily implemented, with even fewer components operation, the internal reference is used by strapping Pins 3
(Figure 20). and 4 of the AD9070 together. The internal reference can
–5V
provide 100 µA of extra drive current that may be used for other
350⍀ circuits.
+5V
VEE GND
Some applications may require greater accuracy, improved
VIN 350⍀
ⴞ0.5V
temperature performance or adjustment of the gain of the
AIN
RT AD9631 AD9070, which cannot be obtained by using the internal
–5V reference. For these applications, an external –2.5 V reference
AD9070 can be connected to VREF IN, which requires 5 µA of drive
0.1␮F
current (Figure 21).
1k⍀ 1k⍀
–5V
AIN
AD820
–5V 0.1␮F 1k⍀
VREF OUT VEE GND
VREF IN
NC VREF OUT
0.1␮F +VIN
AD9070
AD780
VOUT GND VREF IN
Figure 19. DC-Coupled Input
1.25k⍀ 0.1␮F
–5V
350⍀ –5V

+5V VEE
Figure 21. Using the AD780 Voltage Reference
VIN 350⍀ GND
0.1␮F
1Vp-p
AIN The input range can be adjusted by varying the reference
RT
0.1␮F
AD9631 voltage applied to the AD9070. No appreciable degradation in
500⍀
–5V AD9070 performance occurs when the reference is adjusted ± 4%. The
500⍀
AIN full-scale range of the ADC tracks reference voltage changes
0.1␮F linearly.

VREF OUT
Timing
VREF IN
The performance of the AD9070 is insensitive to the duty cycle
0.1␮F of the clock over a wide range of operating conditions: pulse
width variations of as much as ± 20% will cause no degradation
in performance (see Figure 15).
Figure 20. AC-Coupled Input
The AD9070 provides latched data outputs, with three pipeline
Special care was taken in the design of the analog input section
delays. Data outputs are available one propagation delay (tPD)
of the AD9070 to prevent damage and corruption of data when
after the rising edge of the encode command (Figure 1). The
the input is overdriven. The nominal input range is –1.988 V to
length of the output data lines and loads placed on them should
–3.012 V (1.024 V p–p centered at –2.5 V). Out-of-range
be minimized to reduce transients within the AD9070; these
comparators detect when the analog input signal is out of this
transients can detract from the converter’s dynamic performance.
range and set the OR output signal HIGH. The digital outputs
are locked at plus or minus full scale (1FFh or 200h) for The minimum guaranteed conversion rate of the AD9070 is
voltages that are out of range but between –1 V and –5 V. Input 40 MSPS. At clock rates below 40 MSPS, dynamic performance
voltages outside of this range may result in invalid codes at the may degrade. The AD9070 will operate in bursts, but the user
ADCs output. must flush the internal pipeline each time the clock restarts.
Valid data will be produced on the fourth rising edge of the
When the analog input signal returns to the nominal range, the
ENCODE signal after the clock is restarted.
out-of-range comparators return the ADC to its active mode
and the device recovers in approximately 3 ns.

–10– REV. B
 AD9070
+5 V Operation Package Options
The AD9070 may be operated above ground, with a single +5 V The AD9070 is available in two packages. The BR package is a
power supply. All power supply ground pins are connected to standard 28-lead Small Outline IC (SOIC). The DIP package is
+5 V, and VEE pins are connected to ground (Figure 22). Care a ceramic Dual-in-Line Hybrid. The SOIC is offered in a commer-
must be taken in connecting signals and determining bypass rails. cial grade, and specified over the industrial (–40°C to +85°C)
The reference voltage (REF OUT) is still generated with respect temperature range. The DIP is a full MIL-PRF-38534 QML
to the positive rail, which is now +5 V. It is nominally +2.5 V, version that operates from (–55°C to +125°C).
but its voltage with respect to ground will vary directly with The SOIC version includes the on-chip voltage reference,
changes in the power supply voltage (for example, if the power whereas the DIP does not. The DIP, however, provides the
supply goes to +5.1 V, the reference becomes +2.6 V). The Overrange (OR) output, and includes reference and power
reference input is likewise processed with respect to +5 V. This supply bypassing, along with an internal compensation capacitor.
dictates that these pins be bypassed to +5 V as well. However, Equivalent performance may be obtained with either part
the COMP and REF BYPASS pins must continue to be though, due to the internal bypassing, the DIP is not as sensitive
bypassed to the most negative supply, which is now ground. The to board layout and parasitics.
AIN input must still be connected or bypassed to the ground
reference of the input signal.
+5V

0.1␮F
VIN GND
1Vp-p AIN
RT 500⍀
AD9070
AIN
10␮H (MSB) D9 D9
VREF OUT 510⍀
0.1␮F (OR 100⍀ TO +3V)
VREF IN
0.1␮F

+5V (LSB) D0 D0
ENCODE ENCODE 510⍀
(OR 100⍀ TO +3V)
ENCODE ENCODE
REF
COMP VEE BYPASS

0.1␮F 0.1␮F

Figure 22. AD9070 in +5 V (PECL) Environment

REV. B –11–
AD9070
AD9070BR EVALUATION BOARD Data Out
Data goes single-ended into the 10H116 flip flops but comes
E2
E1
AD780 REFERENCE out differentially. The data coming out of the AD9070 is in twos
E3
complement format, but is changed to straight binary by
VREF OUT
1k⍀ 1 OF 2
inverting the MSB at the connector (on the schematic Bit 1 and
VREF IN
AIN 10H176 TO CARD Bit 1B are swapped).
1k⍀ COMP HEX D FF CONNECT
50⍀ –5V BYPASS Voltage Reference
AIN The AD9070 can be operated using its internal bandgap
AIN
AD9070 1 OF 4 reference (connect E2 to E3) or the on board AD780 external
10H116
reference (connect E1 to E3). The board is shipped utilizing the
ENC ENC internal voltage reference.
CLK
J2 10H176
ECL
Layout
50⍀ RECVR The AD9070 is not layout sensitive if some important guide-
E4 E6
PIN 2
lines are met. The evaluation board layout provides an
E19
example where these guidelines have been followed to
CLKB
J4
E8 E9 BUFFERED optimize performance.
AND CARD
50⍀ LATCHED CONNECTOR • Provide a good ground plane connecting the analog and
ON-CARD
ENCODE E7 E5 digital sections.
PIN 21 • Excellent bypassing is essential. Chip caps with 0.1 µF values
Figure 23. and 0603 dimensions are placed flush against the pins.
Placing any of the caps on the bottom of the board can
The AD9070 evaluation board is a convenient and easy way to degrade performance. These techniques reduce the amount
evaluate the performance of the AD9070 in the SOIC package. of parasitic inductance which can impact the bypassing ability
The board consists of an AD780 voltage reference (configured of the caps.
for –2.5 V), two 10H176 (hex D flip flop) for capturing data
from the A/D converter and five 10H116 triple line receivers for • Separate power planes and supplies for the analog and digital
buffering the encode signal and driving the data via the edge sections are recommended.
connector. Termination resistors (RP11, RP12, and RP14) are The AD9070 evaluation board is provided as a design example
provided for the data leaving the board via the connector; (they for customers of Analog Devices. ADI makes no warranties
can be removed if termination resistors are already provided by express, statutory, or implied regarding merchantability or
the user). fitness for a particular purpose.
Analog Input
The evaluation board requires a 1 V peak-to-peak signal
centered at ground (J1). This signal is ac coupled and then dc
shifted –2.5 V before it is input to the A/D converter.
Encode
The AD9070 encode inputs can be driven single ended
(connect E9 to E19 and drive J2 with an ECL signal) or
differentially (connect E8 to E19 and drive J2 and J4 with
differential ECL signals). The board is shipped in single ended
configuration. The differential encode signal leaving the board
via the connector can be inverted by interchanging E4, E5, E6,
and E7 (connect E4 to E7 and E5 to E6 or E4 to E6 and E7 to
E5). This ensures that the user will be able to capture the data
coming from the evaluation board.

–12– REV. B
 10PT - 5.2 10PT - 5.2 10PT - 5.2 10PT - 5.2 10PB - 5.2 U7
RP11 RP12 RP14 RP15 RP17 10H116 C37DRPF
CON1

REV. B
U2 2 ADRB 2 BIT4B 2 BIT8B 2 DR 2 13 15
Q2 D2 Q2 BIT1 1
AD780N 3 ADR 3 BIT4 3 BIT8 3 DRB 3 Q6 12 14 GND
BIT1 BIT9B Q1 Q7 D2 Q2 BIT2B 2
C2 1 8 4 4 BIT5B 4 4 4 10 7 E4 E6 ADRB
NC OP DR D1 Q1 ADRB 3
1␮F 5 BIT1B 5 BIT5 5 BIT9 5 Q2 5 Q8 6 E5 BIT1B
2 +VIN 7 DRB 9 D1 Q1
E7 ADR 4
NC 6 BIT2B 6 BIT6B 6 BIT10B 6 Q3 6 Q9 5 3 BIT2B 5
3 6 Q1 D0 Q0 BIT1
TB1 R1 TEMP VOUT 7 BIT2 7 BIT6 7 BIT10 7 Q4 7 Q10 4 2 BIT3B 6
1.25k⍀ D0 Q0 BIT2B BIT4B
–5V 4 5 8 BIT3B 8 BIT7B 8 8 8 GND 11
GND TRIM VBB 7
GND BIT3 BIT5B
9 9 BIT7 9 9 8
BIT6B
TB2 9
–5V BIT7B 10
–5.2V E1 BIT8B
E3 C15 11
GND E2 U5 U8 BIT9B
0.1␮F 12
10H176 10H116 BIT10B
GND 13
U1 13 15 14
AD9070BR 5 D0 2 Q5 D2 Q2 BIT5 15
C8 Q0 Q1 14
3 12
0.1␮F VEE 21 6 D1 Q1 Q2 D2 Q2 BIT5B 16
3 7 4 7
VREFOUT 23 D2 Q2 Q3 Q3 10 D1 Q1 BIT3 17
4 VEE 9 6
10 D3 13 BIT3B 18
VREFIN 28 Q3 Q4 D1 Q1
5 14 5 3 19
COMP (MSB) D9 11 D4
Q4 Q5 Q4 D0 Q0 BIT4 GND
6 27 12 15 4 2 20
C6 REF D8 D5 Q5 D0 Q0 BIT4B
R5 R6 26 11 21
R4 C3 1.0k⍀ 0.1␮F C7 BYPASS D7 LCLK
9 CLK VBB ADR
1k⍀ 50⍀ 25 22
0.1␮F 0.1␮F D6 BIT1B
BNC C4 –5V –5V 24 23
9 D5 BIT2
J1 0.1␮F 19 24
AIN D4 BIT3
10 18 U15 C14 25
AIN D3 10H176 U9 0.1␮F
BIT4 26
13 17
R2 ENCODE D2 10H116 BIT5
50⍀ 14 16 27
ENCODE D1 BIT6
15 5 D0 2 28
1 V (LSB) D0 Q0 Q6 13 15 BIT7
ENCB ENC –5V EE 6 3 Q8 D2 Q2 29
BNC D1 Q1 Q7 BIT8 BIT8
CLK –5V
7 V
EE 22 7 4 12 14 30
J2 GND GND D2 Q2 Q8 D2 Q2 BIT8B
9 7 –5V
12 V
EE 20 10 13 10 D1 Q1 7 BIT9 31
2 GND GND D3 Q3 Q9 Q6 BIT6 BIT10
GND GND 11 14 9 6 32
D4 Q4 Q10 D1 Q1 BIT6B
R10 10 6 11 5 3 33
GND GND 12 Q5 15 Q7 D0 Q0 BIT7

–13–
50⍀ U11 8 D5 4 34
GND GND 9 2
10H116 LCLK CLK D0 Q0 BIT7B 35
VBB 11
CLKB U11 36
BNC 10H116 37
J4 6PB - 5.2
E19 12 15
CLK DR RP9
E8 E9 13 14 –5.2 C12
CLKB DRB U10 0.1␮F
R3 2
11 R15 10H116
50⍀ U11 3 ENC
10H116 260⍀
4 ENCB 13 15
U11 C16 Q10 D2 Q2 BIT10
4 3 5 LCLK

Figure 24. Evaluation Board Schematic

10H116 0.1␮F CLKB 12 14
2 D2 Q2 BIT10B
CLK 5 LCLK 6 GND 10 7
D1 Q1
R16 9 6
160⍀ D1 Q1
5 3
8PB - 5.2 8PB - 5.2 Q9 D0 Q0 BIT9
4 2
RP1 RP2 GND D0 Q0 BIT9B
VBB 11
2 2
3 D1 3 D1 –5V
C52 C37 C58 C32 C34 C35
4 D2 4 D2
0.1␮F 0.1␮F 10␮F 0.1␮F 0.1␮F 0.1␮F C11
5 D3 5 D3 GND
0.1␮F
6 D4 6 D4
7 D5 7 D5
8 GND 8 GND

C41 C42 C38 C39 C40 C43 C44

0.1␮F 0.1␮F 0.1␮F 0.1␮F 0.1␮F 0.1␮F 0.1␮F
–5.2V
C17 C18 C20 C22 C28 C23 C24 C25 C26 C29
0.1␮F 0.1␮F 0.1␮F 0.1␮F 0.1␮F 0.1␮F 0.1␮F 0.1␮F 0.1␮F 0.1␮F
GND
AD9070
AD9070

Figure 25. Component Side Figure 27. Bottom Side Trace + Components

Figure 26. Component Side Signal Traces Figure 28. Analog/Digital Split Power Plane

–14– REV. B
 AD9070
Table II. Evaluation Board Bill of Materials

ITEM QTY REFD DESCRIPTION

1 5 U7–U11 10H116 – TRIPLE DIFFERENTIAL LINE RECEIVER
2 2 U5, U15 10H176 – 10KH HIGH SPEED ECL
3 4 RP11, RP12, RP14, RP15 10PT-5.2 – 10P TER RES NTWK
4 1 RP9 6PB-5.2 – 6P BUSED RES NTWK
5 2 TB1, TB2 8291Z2 – 2-PIN TERMINAL BLOCK
6 3 RP1, RP2, RP7 8PB-5.2 – 8P BUSED RES NTWK
7 1 U2 AD780N – HIGH PREC VOLT REF
8 1 U1 AD9070R – AD9070 SOIC ECL ADC
9 10 C3, C4, C6, C7, C8, C32, C34, C35, C37, C52 BCAP0603 – CER CHIP CAP 0603, .1 µF
10 24 C11, C12, C14–C18, C20, C22–C26, C28, BCAP0805 – CER CHIP CAP 0805, .1 µF
C38–C44
11 2 C29, C58 BCAPTAJD – CHIP TANT CAP, 10 µF
12 3 J1, J2, J4 BNC – BNC COAX CONN PCMT
13 1 R1 BRES1206 – SURF MT RES 1206, 1.25K
14 1 R16 BRES1206 – SURF MT RES 1206, 160
15 2 R4, R6 BRES1206 – SURF MT RES 1206, 1K
16 1 R15 BRES1206 – SURF MT RES 1206, 260
17 4 R2, R3, R5, R10 BRES1206 – SURF MT RES 1206, 50
18 1 CON1 C37DRPF – 37P D CONN RT ANG PLASTIC PCMT
FEMALE
19 1 C2 T330A – TANT CAP, 1 µF
20 10 E1–E9, E19 W-HOLE – WIRE HOLE

REV. B –15–
AD9070
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

28–Lead SOIC
(R–28)

0.7125 (18.10)

C2996a–0–3/00 (rev. B)
0.6969 (17.70)

28 15

0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
1 14

PIN 1 0.1043 (2.65) 0.0291 (0.74)

x 45°
0.0926 (2.35) 0.0098 (0.25)

8° 0.0500 (1.27)
0.0118 (0.30) 0.0500 0.0192 (0.49) 0° 0.0157 (0.40)
(1.27) SEATING 0.0125 (0.32)
0.0040 (0.10) 0.0138 (0.35) PLANE 0.0091 (0.23)
BSC

28-Lead Hermetic Ceramic DIP

(DH-28)

28 15

0.595 ± 0.010
(15.11 ± 0.25)

1 14

PIN 1 IDENTIFIERS
1.400 ± 0.014 0.050 ± 0.010
(35.56 ± 0.35) (1.27 ± 0.25)
0.225
(5.72)
MAX 0.150
(3.81) 0.010 ± 0.002
MIN (0.25 ± 0.05)

0.018 ± 0.002 0.100 (2.54) 0.05 (1.27) SEATING 0.600 (15.24)

(0.46 ± 0.05) TYP TYP PLANE REF

PRINTED IN U.S.A.

–16– REV. B