44th International Symposium on Microelectronics | October 9-13, 2011 | Long Beach, California USA

Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV)

Heng-Chieh Chien, John H. Lau, Yu-Lin Chao, Ra-Min Tain, Ming-Ji Dai, Sheng-Tsai Wu, Wei-Chung Lo, and
Ming-Jer Kao

Electronics and Optoelectronics Research Laboratories

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Industrial Technology Research Institute (ITRI)
Bldg. 14, 195 Sec.4, Chung Hsing Rd.
Chutung, Hsinchu, Taiwan
886-03591-2075; [email protected]

ABSTRACT

Thermal performance of 3D IC integration is investigated in this study. Emphasis is placed on the determination
of a set of equivalent thermal conductivity equations for Cu-filled TSVs with various TSV diameters, TSV pitches,
TSV thicknesses, passivation thicknesses, and microbump pads. Also, the thermal behavior of a TSV cell is
examined. Furthermore, 3D heat transfer simulations are adopted to verify the accuracy of the equivalent equations.
Finally, the feasibility of these equivalent equations is demonstrated through a simple 3D IC integration structure.

Key Words: 3D IC integration, through silicon via (TSV), SiO2, equivalent thermal conductivities of Cu-filled
TSVs

(1) INTRODUCTION microbump pads are determined. Also, the thermal

Thermal management is one of the critical issues of behavior of a Cu-filled TSV cell with SiO2 layer is
3D IC integration [1-19]. This is because [9-19]: (1) examined. Furthermore, 3D heat transfer simulations
the heat flux generated by stacked multifunctional are performed to verify the accuracy of the equivalent
chips in miniature packages is extremely high; (2) 3D equations. Finally, the feasibility of these equivalent
circuits increase total power generated per unit surface equations is demonstrated through a simple 3D IC
area; (3) chips in the 3D stack may be overheated if integration SiP.
cooling is not properly and adequately provided; (4)
the space between the 3D stack may be too small for (2) CU-FILLED TSV EQUIVALENT THERMAL
cooling channels (i.e., no gap for fluid flow); and (5) CONDUCTIVITY EXTRACTION
thin chips may create extreme conditions for on-chip (2a) Simulated Model Establishment
hot spots. Thus effective thermal management design
methods, tools, guidelines and solutions are
desperately needed for widespread use of 3D IC
integration.
Even with the most advanced software and high-
speed hardware, it is very time consuming to model all
the TSVs in a 3D IC integration system-in-package
(SiP). In [10, 15, 16], empirical equations for the
equivalent thermal conductivities of TSV
chips/interposers with various copper (Cu)-filled TSV
diameters, pitches, and aspect ratios have been
determined. Unfortunately, the passivation layer (SiO2)
was not considered.
In this study, empirical equations for the equivalent
thermal conductivities of Cu-filled TSV chips/
interposers with various passivation thicknesses, TSV Fig.1 Schematic diagram of a TSV cell
diameters, TSV pitches, TSV thicknesses, and

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 44th International Symposium on Microelectronics | October 9-13, 2011 | Long Beach, California USA

Figure 1 shows and defines a TSV cell for For extracting the Cu-filled TSV cross-plane
extracting its equivalent thermal conductivities, and equivalent thermal conductivity (kz), we add one buffer
Tables 1 shows the parameter matrix for simulations. block on the top-side of the TSV and one at the
In the figure and table, DTSV is the diameter of the TSV bottom-side as shown in Figure 3. The buffer blocks
(from 10 to 50μm); H is chip thickness (from 10 to are served to smooth the heat flow that enters in and
200μm; the thinner chips are meant for stacked exits from the cell for obtaining a more reliable and
memories while the thicker chips are for active/passive accurate result.
interposers); P denotes the TSV pitch and tSiO2 denotes Again, by using the Fourier's law, the equivalent
the thickness (from 0.2 to 1.0μm) of the deposited SiO2. thermal conductivity kz can be expressed as

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Thot  Tcold
Q"in  k z 
ΔH
where Thot and Tcold are defined as the average
temperature of the hot section and the cold section,
respectively, and ΔH is the spacing between both
Table 1 The analyzed parameters matrix sections and assumed to be 2μm. The hot and cold
The equivalent thermal conductivities to be sections are mutually parallel and symmetry to the cell
extracted include kxy and kz. The subscripts "xy" and horizon central line of the Cu-filled TSV.
"z" mean, respectively the in-plane direction and cross-
plane direction of the chip/interposer. For Cu-filled
TSV in-plane equivalent thermal conductivity (kxy), we
apply a positive heat flux (Q"in) to one of its sidewall
(called hot surface) and a negative heat flux (-Q"out) to
the opposite sidewall (called cold surface) for sucking
the heat as shown in Figure 2. Based on Fourier's law
we have the equivalent kxy which expressed as

Thot  Tcold
Q"in  k xy 
P
where Thot and Tcold are the average temperature of the
hot surface and the cold surface, respectively and P is
the TSV pitch. Fig. 3 TSV cell for kz extraction. (a) The stereogram
of the cell, and (b) The cross-section of the cell.
(2b) Boundary Conditions and Material Properties
In this study, we use Icepak 12.1.6 as the
simulation tool to solve the heat conduction problems
using finite volume method. The thermal
conductivities of silicon, TSV filled copper, copper
pad, and SiO2 are 148, 401, 401 and 1.38 W/m.K,
respectively. As for the thermal conductivity of the
buffer block, the value is flexible because the purpose
of this block is to smooth the heat flow that enters in
and exits from the TSV cell. Thus, in this study, the
thermal conductivity of the buffer blocks is assumed to
be 500W/m.K and their thickness is 50μm.
The boundary conditions for the simulations are
shown in Figures 2 and 3. A constant heat flux (Q"in) is
applied to the heating surface and the value is assumed
to be 108 W/m2. Also, at the cooling surface, a negative
heat flux (Q"out) is applied to suck the heat. According
Fig. 2 TSV cell for kxy extraction. (a) The to the law of energy conservation the absolute values
stereogram of the cell, and (b) the cross-section of of both heat fluxes must be equal. As for other
the cell

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 44th International Symposium on Microelectronics | October 9-13, 2011 | Long Beach, California USA

boundary conditions, all other surfaces are defined as block the heat to enter the filled Cu, and curve (make)
adiabatic for structure symmetry. the heat flow path longer. All the equivalent lateral
(2c) Equivalent Thermal Conductivity Calculation thermal conductivities (kxy) are smaller than that of
For demonstration purposes, let’s consider: DTSV silicon (148 W/m.K), especially for larger TSV
= 20μm, tSiO2 = 1μm, H = 50μm, P = 65μm and the diameters.
heat flux Q"in = 108 W/m2.
For equivalent kxy extraction, from the simulation
results, we determine the average temperature
difference (Thot–Tcold=48.3℃) between the hot surface

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and cold surface. Since P = 65μm and Q"in = 108 W/m2,
then the equivalent kxy can be calculated from the
Fourier’s law and is equal to 134.57 W/m.K.
For equivalent kz extraction, from the simulation
results, we determine the average temperature
difference (Thot – Tcold = 1.06℃) between the hot
section and cold section. Since Q"in = 108 W/m2, and
ΔH = 2μm, then from the Fourier’s law, the equivalent
kz is 188.68 W/m.K.
Fig. 5 Typical ccorrelations between equivalent kxy
(3) THERMAL BEHAVIOR OF A TSV CELL and SiO2 thickness: the chip thickness (H) is 50μm
(3a) The lateral heat transport of the cell and the pitch is 65μm.
Figure 4 shows the temperature distribution on The effect of SiO2 thickness on equivalent kxy is
the horizon central portion of a TSV cell. The length noticeable as shown in Figure 5. It can be seen that a
and width of the cell are the same and equal to the thicker SiO2 layer (>0.2μm) and a larger TSV diameter
TSV pitch. The passivation layer (SiO2) and the filled (>10μm) result in a lower equivalent kxy. However, for
copper is embedded in the cell. It can be observed that, thinner SiO2 layer (≦0.2μm), regardless of the TSV
for a thick (>0.2μm) passivation layer, the heat flow diameters, the equivalent kxy approach to that of silicon
detour around the TSV because the passivation layer (148 W/m.K) as shown in Figure 5.
has a rather poor thermal conductivity (k=1.38W/m.K The effect of TSV pitch on the equivalent kxy is
for SiO2) compared with the silicon (k=148 W/m.K). noticeable as shown in Figure 6. In general, a larger
In fact, even though the filled copper of the TSV has a TSV density (smaller TSV pitch), a thicker (>0.2μm)
very high thermal conductivity (k=401W/m.K), the SiO2 layer and a larger TSV diameter (>10μm) result
heat flow is still blocked by the passivation layer and in a lower equivalent kxy. However, when the SiO2
thus wears down the contribution of copper for thermal thickness is ≦0.2μm, regardless of the TSV diameter
performance enhancement in the chip lateral direction.
and the TSV pitch, the equivalent kxy approach to that
of silicon (148 W/m.K) as shown in Figure 6.

Fig. 4 Heat flow path and temperature distribution Fig. 6 Typical correlations between equivalent kxy
in lateral direction of a TSV cell. and TSV diameter with different TSV pitch. The
Based on parameter studies, it is found that the chip thickness (H) is 50μm and the SiO2 thicknesses
effect of chip thickness (H) on equivalent kxy is very (tSiO2) are 0.2 and 0.5μm.
insignificant compared to other parameters. Besides, The diameter and pitch of TSV are the other two
for thicker (>0.2μm) passivation (SiO2) layers, which significant parameters for equivalent kxy. Figure 6

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 44th International Symposium on Microelectronics | October 9-13, 2011 | Long Beach, California USA

shows the correlation between kxy and TSV diameter, (2) the smaller the TSV pitch the larger the kz; and (3)
and between kxy and TSV pitch. A larger equivalent kxy again, for all the SiO2 thickness, TSV thickness, TSV
is caused by a smaller TSV dimension ratio that pitch, and TSV diameter, the kz is larger than that of
expressed as DTSV P . In other words, the silicon (due to the positive effect of Cu and the
negative effect of SiO2).
chip/interposer with higher TSV density will have a
worse thermal conductivity in the lateral direction.

(3b) The longitudinal heat transport of the cell

Figure 7 shows the temperature distribution in

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the vertical direction of a Cu-filled TSV cell. Since
copper having a higher thermal conductivity than
silicon, more heat flow inpour and outflow the cell via
the filled copper. Also, the temperature of the filled
copper and silicon must equalize at the vertical central
portion due to energy equilibrium. Therefore, some
heat flow may cross the passivation layer from copper
to silicon after entering the TSV cell, and the heat flow
may cross the passivation layer again from silicon to
the filled copper before exiting the TSV cell. Fig. 8 Typical correlations between equivalent kz
and passivation layer thickness: the TSV pitch is
50μm, and the TSV diameter is 10μm.
The simple explanation of pervious results is a
thicker passivation layer may obstructs the heat
exchange between the filled Cu and Si; thus more heat
flux remains to flow through the Cu that consequently
enhances the weight (influence) of the filled Cu for the
cell thermal performance. On the other hand, a TSV
with higher aspect ratio (H/DTSV) leads to a lower
equivalent kz because more heat exchange has been
happened between the Cu and Si during the heat flow
through the TSV cell, that reduces the influence of the
filled Cu for the TSV cell thermal performance.

Fig. 7 Temperature distribution in the vertical

direction of a TSV cell.
The passivation layer (SiO2) serves as a thermal
barrier in the TSV cell. Figure 8 shows the effect of
SiO2 thickness and TSV thickness (H) on the
equivalent longitudinal thermal conductivity (kz) for
the case of TSV pitch = 50μm and TSV diameter =
10μm. It can be seen that in general: (1) for all the
SiO2 thickness and TSV thickness, the kz is larger
than that of silicon (due to the positive effect of Cu
and the negative effect of SiO2); (2) for H = 100μm
(like interposers) the SiO2 thickness has no effect on Fig. 9 Correlations between equivalent kz and the
the kz; (3) for H = 50μm (like memory-chip stacking) TSV diameter. The chip thickness (H) is 50μm
the SiO2 thickness (from 0.2 to 0.5μm) has little and the SiO2 thickness (tSiO2) is 0.2μm.
effect on the kz; and (4) at SiO2 = 0.2μm, the kz is
almost the same for H = 50μm (memory-chip (4) CU-FILLED TSV EQUIVALENT THERMAL
stacking) and H = 100μm (interposers). CONDUCTIVITY EQUATIONS
Figure 9 shows the effect of TSV diameter and (4a) Equivalent Thermal Conductivity Equations
TSV pitch on the kz for TSV thickness (H) = 50μm kxy and kz
and SiO2 thickness = 0.2μm. It can be seen that: (1) in By curve fitting of the simulation results for all
general the larger the TSV diameter the larger the kz; the cases considered in Table 1, we have the empirical

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 44th International Symposium on Microelectronics | October 9-13, 2011 | Long Beach, California USA

equations of the Cu-filled TSV equivalent thermal thermal simulations. Figure 12 shows how a detail
conductivity equations. TSV model can be converted into an equivalent model.
For equivalent kxy, the empirical equation is


k xy  90  t SiO 2
0.33
 D
 148   TSV
 0.1
  H  160  t SiO 2
0.07

 P 

For equivalent kz, the empirical equation is

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t SiO2 D 
0.002   0.01  k z  128  exp TSV 
H  P 

where
0.2 m  tSiO 2  0.5m
Fig. 11 Comparison between the simulation data
10m  DTSV  50m (dot) and equivalent kz equation (curve). The error
bar is ±10%.
H  20m
The equivalent model regards the TSV group as an
0.1  DTSV P  0.77 equivalent zone (block) which is represented with the
calculated equivalent kxy and kz. The passivation layers
(4b) Comparison between the Results Obtained (SiO2) outside the TSVs are modeled. The solder balls
from kxy and kz and from 3D Heat Transfer (or bumps) and the traces are converted to other
Simulations equivalent zones by using the common thermal
Figures 10 and 11 show the comparisons between resistance (series/parallel) calculations.
the 3D simulation data and the equivalent equations.
For equivalent kxy and equivalent kz, it can be seen that
the largest error of the empirical equations is less than
15%. Most simulation data agree with the equivalent
equations to an error of less than 10%.

Fig. 12 The conversion from a detail model to an

equivalent model. (a) The detail model and (b) The
equivalent model.
Fig. 10 Comparison between the simulation data (5) VERIFICATION OF THE TSV EQUIVALENT
(dot) and equivalent kxy equation (curve). The error THERMAL CONDUCTIVITY EQUATIONS
bar is ±10%. Figure 13 shows a 3D IC integration SiP. There
are 4 memory chips (each with 3 TSVs and the TSV
(4c) How to Use Equivalent Thermal Conductivity diameter is DTSV=10μm) bonded together (with a 20μm
Equations (kxy and kz) for 3D IC Integration? diameter microbump) on top of an interposer. Each
The equivalent equations can be used for the chip has two heaters (on opposite directions) and each
design and analysis of 3D IC SiPs by establishing an heater generates a heat flux of 1×106 W/m2. The chip
equivalent model. This equivalent model is used to thickness is 50μm. The SiO2 thickness = 0.2μm. Since
replace the real detail TSV model for simplifying the

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 44th International Symposium on Microelectronics | October 9-13, 2011 | Long Beach, California USA

each chip size is 10mm x 10mm and each dissipates chip #1 (this is because the main dissipation path of
0.8W of heat. Thus, for the 4-chip stacking the total the heat is via the model topside to the ambient); and
power generated from the heat is 3.2W.) (3) except the top chip, the smaller the TSV pitch (a
The boundary conditions are: h=10000 W/m2K denser TSV arrangement) the lower the heater
on the topside of the model and h=500 W/m2K on the temperature (this is caused by the higher longitude
equivalent thermal conductivity (kz) of TSV and
microbumps).
What’s thermal path and temperature distribution
of the memory-chip stacking with microbumps but

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without TSVs? The simulation results show that all
the chip temperatures are higher than those of the
model with TSVs (Cu-filled TSVs provide a better
thermal conducting path than Si). It is about 2.5℃ for
chip #4, 2℃ for chip #3, 1.2℃ for chip #2 and 0.1℃
for chip #1. These results indicate that TSVs indeed
increase the chips’ heat dissipation effect and thermal
performance. For this simple example, the thermal
Fig. 13 Detail and equivalent models for feasibility performance enhancement is about 6%.
verification. (a) The detail model and (b) The
equivalent model. There are two heaters on a chip
and each heater generates 106 W/m2.
bottom of the interposer. Physically, it means the SiP
has an air cooling heat sink on the topside and a natural
convection cooling on the bottom side. The slice model
is introduced: (1) because it is a semi-2D model that
can simplify the simulation effort, and (2) for the
verification and demonstration of its accuracy and
feasibility.
Figure 14 shows the temperature distributions of
the detail model (left) and the equivalent model (right).
It can be seen that: (1) the TSVs are dissipating the
Fig. 15 Heater temperature comparison: DTSV, H,
accumulated heat from the chips to ambient (left), and
tSiO2 and bump diameter are 10, 50, 0.2, 20μm,
(2) even the heat flow insides both models is different,
respectively. The ambient temperature is 35C.
however, the temperatures of the heaters of the two
models are quite the same.
(6) SUMMARY AND RECOMMENDATIONS
Empirical equations for the equivalent thermal
conductivities of Cu-filled TSV chips/interposers with
various passivation thicknesses, TSV diameters, TSV
pitches, TSV thicknesses, and microbump pads have
been determined in this investigated. Also, the thermal
behavior of a SiO2-Cu-filled TSV cell has been
discussed. Furthermore, the accuracy of the equivalent
equations has been verified by 3D heat transfer
Fig. 14 A typical temperature distribution of the simulations. Finally, the feasibility of these equivalent
detail model (left) and the equivalent model (right). equations has been demonstrated through a simple 3D
Here, DTSV, tSiO2, H and bump diameter are 10, 0.2, memory-chip stacking structure. Some important
50 and 20μm, respectively. The boundary results and recommendations are summarized as
conditions and heat generation are shown in Fig.13. follow.
Figure 15 shows the heater temperature (1) kxy and kz for SiO2-Cu-filled TSV memory-chip
comparisons between the detail model and the stacking and interposer have been provided and
equivalent model. It can be seen that: (1) for all the they are very useful for 3D IC integration
TSV pitches, both models predict almost the same design and analysis.
heater temperature; (2) for all the TSV pitch, the (2) Based on the 3D simulation results, most errors
smallest heater temperature occurs at the top chip #4 of kxy and kz are within 10% and in a few cases
and the largest heater temperature occurs at the bottom the maximum error is 15%.

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 44th International Symposium on Microelectronics | October 9-13, 2011 | Long Beach, California USA

(3) For thermal performance of 3D IC integration, the validation of thermal modelling of hot spot
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flow into the filled Cu). However, for the Measurement and Management Symposium, 2011,
practical cases (real applications) such as SiO2 = pp. 131-137.
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and H = 100 – 200μm for interposer, the value three-dimensional integrated circuits with
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(6) The guidelines for using kxy and kz for 3D IC Thermal Performance of Three-Dimensional
integration SiP have been provided through Integrated Circuits”, IEEE Transactions on
examples. Components and Packaging Technologies,Vol. 33 ,
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