Unit -3

Part – B
1. (a) Explain the frequency response characteristics and compensation of op-amp
with neat diagrams. (May 2016)
Frequency Response:
 The variation in operating frequency will cause variations in gain magnitude
and its phase angle. The manner in which the gain of the op-amp responds to different
frequencies is called the frequency response. Op-amp should have an infinite bandwidth
Bw =∞ (i.e.) if its open loop gain in 90dB with dc signal its gain should remain the same
90 dB through audio and onto high radio frequency.
 The op-amp gain decreases (roll-off) at higher frequency what reasons to de-
crease gain after a certain frequency reached. There must be a capacitive component in
the equivalent circuit of the op-amp.
 For an op-amp with only one break (corner) frequency all the capacitors effects
can be represented by a single capacitor C. Below fig is a modified variation of the low
frequency model with capacitor C at the o/p.

There is one pole due to R0 C and one -20dB/decade. The open loop voltage gain of an
op-amp with only one corner frequency is obtained from above fig.
− j XC
v 0= A v
R 0− jX C OL d
v0 A OL
A= =
v d 1+2 πfR 0 C
A OL
A=
1+ j
( )
f
f1
1
Where, f 1=
2 π Ro C
f1 is the corner frequency or the upper 3 dB frequency of the op-amp. The magnitude
and phase angle of the open loop volt gain can be written as,

A OL
| A|=

√ ( )
2
f
1+
f1

∅ =−tan−1
f
f1 ( )
The magnitude and phase angle characteristics from above equation.
 For frequency f<< f1 the magnitude of the gain is 20 log AOL in dB.
 At frequency f = f1 the gain in 3 dB down from the dc value of A OL in dB. This frequency
f1 is called corner frequency.
 For f>>f1 the fain roll-off at the rate off -20dB/decade or -6dB/decade.

Phase Characteristics
From the phase characteristics that the
 Phase angle = zero ,at frequency f =0.

 Phase angle = -450 ,at f=f1

 phase angle = -900 ,at f= infinite frequency.

It shows that a maximum of 90 0 phase change can occur in an op-amp with a

single capacitor C.

Stability of an Op-amp:
Op-amps are rarely used in open loop configuration because of its high gain. Let us
now consider the effect of feedback on op-amp frequency response.
 It uses resistor feedback network and may be used as an invertingamplifier for V2 = 0 and
as non-inverting amplifier for V1 = 0.

 From the negative feedback concepts, we may write the closed looptransfer function as
A
ACL=
1+ Aβ
whereA is the open loop voltage gain and is the feedback ratio.

 If characteristic equation( 1+ Aβ ) =0, the circuit will become just unstable, that is, leads
into sustained oscillation.
 Rewriting the characteristic equation as,1−( Aβ)=0 , leads to loop gain,− Aβ=1
 Since Aβ is a complex quantity , the magnitude condition become
| Aβ|=1
 A has an additional phase shift of 180˚ which makes the total phase shift equal to zero.
 In this case, there is every possibility that the amplifier may begin to oscillate as both the
magnitude and phase conditions.
 This may be noted that oscillation is just the starting point of instability.

 when( 1+ Aβ ) <0

Aβ<0 i . e . negative ,and then ACL> A, i.e. the closed loop gain increases and leads to in-
stability.

 When Aβ>0 , and obviously ACL< A and the system is stable.

a. Dominant Pole Compensation

Dominant pole is introduced by adding RC network in series with op-amp.
Consider an op-amp with three break frequencies and its loop gain is A.
 AOL
A=
(1+ j ff )(1+ j ff )(1+ j ff )
1 2 3

The transfer function of the compensating network can be obtained as

V0
A 1= '
V0
By applying voltage division rule to the network,
V 0 − j XC
A 1= ' =
V 0 R− j X C

−j
2 πfc
A 1=
j
R−
2 πfc

1
A 1=
1+ j2 πfRC
Let,
1
f d=
2 πRC

1
A 1=
1+ j
f
fd ( )
Where, f d=break frequency of the compensating network
Hence the compensated transfer function becomes
'
A = A A1
' AOL
A=
( 1+ j
f
fd)(
1+ j
f
f1 )(
1+ j
f
f2
1+ j
f
f3 )( )
 It can be observed from the plot that 3 dB down bandwidth for non-compensated system
is BW 1 while for compensated it becomes BW2. There is drastic reduction in the band-
width.
Advantages :
i) As the noise frequency components are outside the smaller bandwidth, the noise
immunity of the system improves.
ii) Adjusting value of f, adequate phase margin and the stability of the system is
assured.

Disadvantage :
i) The only disadvantage of the method is that the bandwidth reduces drastically,
as mentioned earlier.

b. Pole-Zero Compensation
Consider the same op-amp described by the open loop gain A with three break
frequencies as
AOL
A=
( 1+ j
f
)(
f1
1+ j
f
f2)( 1+ j
)
f
f3
In this method, the transfer function A is modified by adding a pole and zero with the help
of compensating network.

The zero added is at higher frequency while a pole is at lower frequency. Such a
compensating network is shown in the Fig. 2.125

The transfer function of the compensating network can be obtained as

V0
A 1= '
V0
By applying voltage division rule to the network,
Z1
A 1=
Z 1+ Z 2
 From fig., Z1 =R 1
Z 2=R2− j X C 2
R1
A 1=
R 1 + R2− j X C 2
1+ j2 πf R2 C 2
A1=
1+ j2 πf (R1+ R ¿ ¿ 2)C 2 ¿
1
f 1=
2 π R2 C 2
1
f 2=
2 π (R1 + R ¿ ¿2)C2 ¿

A1=
1+ j
f
( )
f1

1+ j
f
( )
f0
The values of R1, R2 and C2 are so selected that the break frequency for the zero matches
with the first comer frequency f1 of the uncompensated system. While the pole of the
compensating network at f0is selected in such a way that the compensated transfer
function A' passes through 0 dB at the second comer frequency f 2 of the uncompensated
system. The resultant loop gain becomes
'
A = A A1

A=
(
AOL 1+ j
f
f1 )
(1+ j
)(
f
f0
1+ j
f
f1 )(1+ j
f
f2 )( )
1+ j
f
f3

(b) In response to square wave input, the output of an op-amp voltage follower
changed from -3V to +3V in 0.25µsec. What is the slew rate of the op-amp?

Slew rate is the maximum rate of change of output voltage with respect to time.
Specified in V/μs

Given:

Change of voltage at output : -3v to +3v

Time taken for change of output : 0.25 µsec

Slew rate = change of output voltage/time taken

Hence, S.R = 6V/0.25 µsec = 24V/ µsec

 Theory :
There is a capacitor with-in or outside of an op-amp to prevent oscillation. It is this
capacitor which prevents the output voltage from responding immediately to a fast
changing input.
The rate at which the volt across the capacitor increases is given by
dv c I
=
dt C
d v c I max
SR= =
d t max C
For a sine wave input, the effect of slew rate can be calculated as below
consider a volt follower circuit,

If V s =V m sinωt then, the output V o =V m sinωt . The rate of change of

output is given by

dv 0
¿ V m ω cosωt
dt
 The max rate of change of output across when cosω t =1

(i.e)
d vc
SR= ¿ωV m
d t max
Therefore, SR = 2πf VmV/Sec
 Thus the maximum frequency fmax at which we can obtain an undistorted output volt
of peak value Vm is given by

Slew Rate
f max ( Hz)=
6.28 × V m
It is maximum frequency of a large amplitude sine wave with which op-amp can have
without distortion.

2. Explain the DC and AC characteristics of an op-amp. (May 2013, Nov 2013, Nov
2016, Dec 2017)
 DC Characteristics of op-amp are,
a. Input bias current
b. Input offset current
c. Input offset voltage
d. Thermal drift
a. Input bias current:
 Input bias current is defined as the average value of two base currents entering in two
Opamp i/p terminals.
 The op-amp’s input is differential amplifier, which may be made of BJT or FET.
 In an ideal op-amp, we assumed that no current is drawn from the input terminals.
 The base currents entering into the inverting and non-inverting terminals (I B-& IB+ respec-
tively).
 Even though both the transistors are identical, I B- and IB+ are not exactly equal due to in-
ternal imbalance between the two inputs.

−¿
IB
+¿+ ¿
2
I B=I B ¿
 The output is driven to 500mV with zero input, because of the bias currents.
 In application where the signal levels are measured in mV, this is totally unacceptable.
This can be compensated. Where a compensation resistor R comp has been added between
the non-inverting input terminal and ground as shown in the figure below.

Current IB+ flowing through the compensating resistor Rcomp, then by KVL we get,
V1+0+V2-Vo = 0
Vo = V2 – V1 (1)
By selecting proper value of R comp, V2 can be cancelled with V1 and the Vo = 0.
The value of Rcomp is
V1 = IB+Rcomp
 V1
+¿= ¿
IB
Rcomp (2)
The node ‘a’ is at voltage (-V 1). Because the voltage at the non-inverting input
terminal is (-V1). So with Vi = 0 we get,
V1
I 1=
R1
V2
I 2=
Rf
For compensation, Vo should be zero for Vi=0, that is from Eq.(1) V2=V1
V1
So that, I 2=
Rf
KCL at node ‘a’ gives,
V1 V1 ( R1 +R f )
−¿=I 2+ I 1= + =V 1 ¿
IB R f R1 R1 Rf (3)
+¿ ¿
−¿=I ¿
Assuming I B and using equ. (2) and (3), We get
B

( R1 + R f ) V 1
V1 =
R1 R f Rcomp
Rcomp = R1 || Rf (4)
i.e. to compensate for bias current, the compensating resistor, R comp should be equal to the
parallel combination of resistor R1 and Rf.

b. Input offset current:

 Bias current compensation will work if both bias currents IB+ and IB- are equal.
 Since the input transistor cannot be made identical. There will always be some small dif-
ference between IB+ and IB-. This difference is called the offset current
|Ios| = IB+-IB-
 Offset current Ios for BJT op-amp is 200nA and for FET op-amp is 10pA. Even with bias
current compensation, offset current will produce an output voltage when Vi = 0.

V1 = IB+ Rcomp
And I1 = V1/R1
KCL at node ‘a’ gives,
I
I2 = ( B− - I1)

I + R comp
B
I 2=I − −( )
B R1
R comp
V o =I 2 R f −V 1=I 2 R f −I + R comp=( I − −I + )R f −I + R comp
B B B R1 B

Substitute equation (9) and after algebraic manipulation,

V o =R f ( I − −I + )
B B
V o =R f I os
So even with bias current compensation and with feedback resistor of 1M, a BJT
op-amp has an output offset voltage
Vo = 1M Ω X 200nA
Vo = 200mV with Vi = 0
Offset current compensation:
 Offset current can be minimized by keeping feedback resistance small.
 Unfortunately to obtain high input impedance, R1 must be kept large.
 R1 large, the feedback resistor Rf must also be high. So as to obtain reasonable gain.
 The T-feedback network is a good solution. This will allow large feedback resistance,
while keeping the resistance to ground low (in dotted line).

c.Input offset voltage:

 Inspite of the use of the above compensating techniques, it is found that the output volt-
age may still not be zero with zero input voltage [V o ≠ 0 with Vi = 0]. This is due to un-
avoidable imbalances inside the op-amp and one may have to apply a small voltage at the
input terminal to make output (Vo) = 0.
 This voltage is called input offset voltage Vos. This is the voltage required to be applied
at the input for making output voltage to zero (Vo = 0).

Rf
V o =( 1+ )V ios
R1

 Thus, the output offset voltage of an op-amp in closed loop is given by above equa-
tion

Total output offset voltage:

 The total output offset voltage VOT could be either more or less than the offset volt-
age produced at the output due to input bias current (IB) or input offset voltage alone(Vos).
 This is because IB and Vos could be either positive or negative with respect to ground.
Therefore the maximum offset voltage at the output of an inverting and non-inverting am-
 plifier (figure b, c) without any compensation technique used is given by many op-amp
provide offset compensation pins to nullify the offset voltage.
 10K potentiometer is placed across offset null pins 1&5. The wipes connected to the
negative supply at pin 4.
 The position of the wipes is adjusted to nullify the offset voltage.

When the given (below) op-amps does not have these offset null pins, external
balancing techniques are used.
Rf
V OT =( 1+ )V ios + R f I B
R1
With Rcomp, the total output offset voltage
Rf
V OT =( 1+ )V ios + R f I os
R1

d.Thermal drift
Bias current, offset current, and offset voltage change with temperature. A circuit carefully
nulled at 25ºC may not remain. So when the temperature rises to 35ºC. This is called drift.
Offset current drift is expressed in nA/ºC and offset voltage drift in mV/ 0C. . These indi-
cate the change in offset for each degree Celsius change in temperature.

AC Characteristics:
1. Frequency response
2. Slew-rate.

1. Frequency Response:
 The variation in operating frequency will cause variations in gain magnitude and its phase
angle. The manner in which the gain of the op-amp responds to different frequencies is
called the frequency response. Op-amp should have an infinite bandwidth Bw =∞ (i.e.) if
its open loop gain in 90dB with dc signal its gain should remain the same 90 dB through
audio and onto high radio frequency.
 The op-amp gain decreases (roll-off) at higher frequency what reasons to decrease gain
after a certain frequency reached. There must be a capacitive component in the equivalent
circuit of the op-amp.
 For an op-amp with only one break (corner) frequency all the capacitors effects can be
represented by a single capacitor C. Below fig is a modified variation of the low fre -
quency model with capacitor C at the o/p.

There is one pole due to R0 C and one -20dB/decade. The open loop voltage gain of an
op-amp with only one corner frequency is obtained from above fig.
− j XC
v 0= A v
R 0− jX C OL d
v0 A OL
A= =
v d 1+2 πfR 0 C
A OL
A=
1+ j
( )
f
f1
1
Where, f 1=
2 π Ro C
f1 is the corner frequency or the upper 3 dB frequency of the op-amp. The magnitude and
phase angle of the open loop volt gain can be written as,

A OL
| A|=

√ ( )
2
f
1+
f1

∅ =−tan−1
f
f1( )
The magnitude and phase angle characteristics from above equation.
 For frequency f<< f1 the magnitude of the gain is 20 log AOL in dB.
 At frequency f = f1 the gain in 3 dB down from the dc value of A OL in dB. This frequency
f1 is called corner frequency.
 For f>>f1 the fain roll-off at the rate off -20dB/decade or -6dB/decade.
 Fig. Phase Characteristics
From the phase characteristics that the
 Phase angle = zero ,at frequency f =0.

 Phase angle = -450 ,at f=f1

 phase angle = -900 ,at f= infinite frequency.

It shows that a maximum of 900 phase change can occur in an op-amp with a single
capacitor C.

Stability of an Op-amp:
Op-amps are rarely used in open loop configuration because of its high gain.
Let us now consider the effect of feedback on op-amp frequency response.

 It uses resistor feedback network and may be used as an inverting amplifier for
V2 = 0 and as non-inverting amplifier for V1 = 0.
 From the negative feedback concepts, we may write the closed loop transfer
function as
 A
ACL=
1+ Aβ
Where A is the open loop voltage gain and is the feedback ratio.
 If characteristic equation( 1+ Aβ ) =0, the circuit will become just unstable, that
is, leads into sustained oscillation.
Rewriting the characteristic equation as,1−( Aβ)=0 , leads to loop gain,− Aβ=1
 Since Aβ is a complex quantity , the magnitude condition become
| Aβ|=1
 A has an additional phase shift of 180˚ which makes the total phase shift equal
to zero.
 In this case, there is every possibility that the amplifier may begin to oscillate
as both the magnitude and phase conditions.
 This may be noted that oscillation is just the starting point of instability.

 when( 1+ Aβ ) <0

Aβ<0 i . e . negative ,and then ACL> A, i.e. the closed loop gain increases and leads to in-
stability.

 When Aβ>0 , and obviously ACL< A and the system is stable.

2.Slew Rate:
{What is Slew rate? List the causes of the Slew rate and explain its significance in
applications Dec2015,May 2019}
Slew rate is the maximum rate of change of output voltage with respect to time. Specified
in V/μs

There is a capacitor with-in or outside of an op-amp to prevent oscillation. It is this

capacitor which prevents the output voltage from responding immediately to a fast
changing input.

The rate at which the volt across the capacitor increases is given by
dv c I
=
dt C
d v c I max
SR= =
d t max C
 For a sine wave input, the effect of slew rate can be calculated as below
consider a volt follower circuit,

If V s =V m sinωt then, the output V o =V m sinωt . The rate of change of output is given by

dv 0
¿ V m ω cosωt
dt
 The max rate of change of output across when cosω t =1

(i.e)
d vc
SR= ¿ωV m
d t max
Therefore, SR = 2πf VmV/Sec
 Thus the maximum frequency fmax at which we can obtain an undistorted output volt
of peak value Vm is given by

Slew Rate
f max ( Hz)=
6.28 × V m
It is maximum frequency of a large amplitude sine wave with which op-amp
can have without distortion.
3. List the six characteristics of an ideal op-amp and explain in detail. Give the
practical op-amp equivalent circuit. (May 2013)
a. Infinite voltage gain A.
It is denoted as AoL. It is the differential open loop gain and is infinite for an ideal op-
amp.
b. Infinite input resistance Ri
The input impedance is denoted as Rin and is infinite for an ideal op-amp. This ensures
that no current can flow into an ideal op-amp.
c. Zero output resistance Ro
The output impedance is denoted as R o and is zero for an ideal op-amp. This ensures
 that the output voltage of the op-amp remains same, irrespective of the value of the
load resistance connected.
d. Zero output voltage
The presence of the small output voltage though V 1 = V2 = 0 is called an off voltage. It
is zero for an ideal op-amp. This ensures zero output for zero input signal voltage.
e. Infinite bandwidth
The range of frequency over which the amplifier performance is satisfactory is called
its bandwidth. The bandwidth of an ideal op-amp is infinite. This means the operating
frequency range is from 0 to infinity. This ensures that the gain of the op-amp will be
constant over the frequency range from d.c. (zero frequency) to infinite frequency. So
op-amp can amplify d.c. as well as a.c. signals.
f. Infinite common mode rejection ratio
The ratio of differential gain and common mode gain is defined as CMRR.Thus infinite
CMRR of an ideal op-amp ensures zero common mode gain. Due to this common
mode noise output voltage is zero for an ideal op-amp.
g. Infinite slew rate
The slew rate is defined as the maximum rate of change of output voltage caused by a
step input voltage. An ideal slew rate is infinite which means that op-amp’s output
voltage should change instantaneously in response to input step voltage.It is expressed
d vo
as s= and measured in
d t max
voltage/second.
h. No effect of temperature
The characteristics of op-amp do not change with temperature.

Practical Opamp equivalent circuit

4. (a) The input offset voltage of op-amp is 0.5mV. The bias current is 30pA. Find
the value of Rcomp to take care of the effect of IB for a non-inverting amplifier
having a gain of 15.

( )
V 0=V ios 1+
Rf
R1
+ Rf I B
 The gain of the non-inverting amplifier is 15.
Rf
1+ =15
R1
Assume R1= 1 K ohms
Rf
=15−1=14
R1
R f =¿14 K ohms¿
The value of Rcomp is
Rf R 1∗14
Rcomp = 1
= =933.33 ohms
R f + R1 1+ 14

(b) In a practical non-inverting, amplifier, R 1=1kΩ, Rf=10kΩ, AOL=2 X 105,

Rin=2mΩ, Ro=75 Ω and fo=5Hz. Supply voltages = ±12V. Calculate A CL, Rinf,
Rof and ff.

R1 1∗10
3
β= = = 0.091
R 1+ R f 3
1∗10 +10∗10
3

A OL 2∗10
5
2∗10
5
ACL = = = = 10.988
1+ A OL∗β 5
1+ 2∗10 ∗0.091 18201
b

Rinf = Rin (1+ AOL∗β ) = 1000* 18201 = 18.2MΩ

3
R0 10∗10 10000
Rof = = 3 = = 10.98 Ω
1+ R 0∗β 1+ 10∗10 0∗0.091 910

ff = f 0 (1+ AOL∗β ¿ = 5 *18201 = 91 KHz

5. Explain the ideal and non-ideal DC characteristics of an op amp.

(Dec 2018)(Nov 2019)

Ideal DC characteristics of an op amp: Refer Question number 3

Non-ideal DC characteristics of an op amp

6. With neat diagram explain the types of feedback configurations available.
 The two basic amplifiers circuits with negative feedback are:
 The non-inverting amplifier
 The inverting amplifier

Inverting operational amplifier:

 This is perhaps the most widely used of all the op-amp circuits.
 Input signal is applied to the inverting input terminal through R1and non-inverting input
terminal of op-amp is grounded.

Analysis: For simplicity, assume an ideal op-amp. As Vd= 0, node 'a' is at ground potential and
the current i1 through R1is
Vi
i 1=
Ri

Also since op-amp draws no current, all the current flowing through R1 must flow through Rf.
The output voltage,
Rf
V 0=−i1 Rf =−V i
R1

Hence, the closed loop gain of the inverting amplifier is,

V 0 −Rf
ACL= =
Vi R1

Alternatively, the nodal equation at the node 'a' in Fig. 2.11 (a) is

V a−V i V a−V 0
+ =0
R1 Rf

Where Va is the voltage at node 'a'. Since node 'a' is at virtual ground Va= 0. Therefore, we get,

V 0 −Rf
ACL= =
Vi R1
The negative sign indicate a phase shift of 180̊ between Vi and V0. If the resistance is replaced
by impedance, then the closed loop gain is given by,
V 0 −Z f
ACL= =
Vi Z1

Non-Inverting operational amplifier:

If the signal is applied to the non-inverting input terminal and feedback is given as
 shown in Fig. 2. 7 (a), the circuit amplifies without inverting the input signal. Such a circuit is
called non-inverting amplifier.
It may be noted that it is also a negative feed-back system as output is being fed back to the
inverting input terminal.

As the differential voltage Vd at the input terminal of op-amp is zero, the voltage at node 'a'
in Fig. 2.7 (a) is Vi, same as the input voltage applied to non-inverting input terminal. Now
Rf and R1forms a potential divider. Hence

V0
V i= R
R1 + Rf 1

As no current flows into the op-amp,

V 0 R1 + R f Rf
= =1+
Vi R1 R1

Hence, the closed loop gain of the Non-inverting amplifier is,

V0 Rf
ACL= =1+
Vi R1

7. Draw the circuits for inverting, non-inverting and difference amplifier using op
amp. Derive an expression for gain for these three configurations. (Dec 2018)
(Nov/Dec 2019)
Inverting, non-inverting amplifier: Refer question number 6
Difference amplifier
A circuit that amplifies the difference between two signals is called a difference or differential
amplifier.
 Since, the differential voltage at the input terminals of the op-amp is zero, nodes 'a' and 'b' are
at the name potential, designated as v3. The nodal equation at 'a' is.

v 3−v 1 v 3 −v 0
+ =0
R1 R2
and at 'b' is
v 3−v 2 v 3
+ =0
R1 R2
Rearranging, we get

( R1 + R1 ) v − R = R
v2 vo
3
1 2 1 2

( )
1 1 v1
+ v 3 − =0
R1 R2 R1

1 vo
R1
( v1 −v 2 )=
R2

R2
v o= ( v −v )
R1 1 2
8. Briefly explain summing amplifier. Draw an adder circuit for the given expression
V0= - (0.1V1 +V2 +5V3).

Summing Amplifier:
 Definition: Op-amp may be used to design a circuit whose output is the sum of several
input signals. Such a circuit is called a summing amplifier or a summer.
 Types:

(i) Inverting summer and (ii) non-inverting summer

(i)Inverting Summing Amplifier:

 A typical summing amplifier with three input voltages V 1, V2 and V3, three input resis-
tors R1, R2, R3 and a feedback resistor Rf is shown in above figure.

 The following analysis is carried out assuming that the op-amp is an ideal one, that is,
AOL = ∞. Since the input bias current is assumed to be zero, there is no voltage drop across the
resistor Rcomp and hence the non-inverting input terminal is at ground potential.
 The voltage at nod ‘a’ is zero as the non-inverting terminal is grounded. The nodal
equation be KCL at node ‘a’ is

V 1−V a V 2−V a V 3 −V a V 0−V a

+ + + =0
R1 R2 R3 Rf
Sub ,V a =0 ,Then
V1 V2 V3 V0
+ + + =0
R1 R2 R 3 R f
V0 V1 V2 V3
=−( + + )
Rf R1 R 2 R3
V 1 R f V 2 Rf V 3 R f
V 0 =−( + + )
R1 R2 R3
Sub , R 1=R 2=R 3=R f
(V 1 +V 2 +V 3 )R f
Then , V 0 =−
Rf

V 0 =−(V 1 +V 2 +V 3 )−−−−−−−−−−−−−(1 )
If , R1 =R2 =R 3 =3 R f ,Then
(V 1 + V 2 +V 3 )
V 0 =− −−−−−−−−−−−−−(2)
3
Thus eqn (1) output Vo is the inverted sum of the input signals. Eqn (2) is output is the aver-
age of the input signals (inverted).To find Rcomp, make all inputs V1 = V2 = V3 = 0. So the ef-
fective input resistance Ri = R1 || R2 || R3. Therefore, Rcomp = Ri || Rf = R1 || R2 || R3 || R,f.
Non-Inverting Summing Amplifier:

Definition: A summer that gives a non-inverted sum is the non-inverting summing

amplifier of figure 3. Let the voltage at the (-) input terminal be Va.
The voltage at (+) input terminal will also be V a. The nodal equation at node ‘a’ is
given by
 V 1−V a V 2−V a V 3 −V a V 0−V a
+ + + =0
R1 R2 R3 Rf
V1 V2 V3 Va Va Va
+ + = + +
R1 R2 R 3 R1 R2 R 3
V V V
Va
( 1 1 1
+ +
)
= 1+ 2+ 3
R1 R 2 R3 R 1 R2 R3
V1 V 2 V3
+( + )
R1 R2 R 3
V a=
1 1 1
( + + )
R1 R2 R 3

The op-amp and two resistors and R constitute a non-inverting amplifier with
Rf
V 0 =(1+ )V a
R
Therefore, the output voltage is,
V 1 V2 V3
( + + )
Rf R1 R 2 R3
V 0 =(1+ )
R 1 1 1
( + + )
R1 R 2 R 3

which is a non-inverting weighted sum of inputs.

Let R1 = R2 = R3 = R = Rf/2,
Then, Vo = V1+V2+V3

Adder Circuit for the given expression Vo=-(.1V1+V2+10V3):

The output is given by
V 0=−
[( ) ( ) ( )
Rf
R1
R R
V 1+ f V 2+ f V 3
R2 R3
Assume R f =10 kΩ ,
]
Rf
=0.1⇒ R 1=100 kΩ
R1
Rf
=1⇒ R 2=10 kΩ
R2
Rf
=10⇒ R3=1 kΩ
R3
9. Explain briefly about how an operational amplifier is used as summer, Differentia-
tor and Integrator. (Nov 2013, May 2016)
Operational amplifier is used as summer: Refer question number 8
Differentiator:
As the name implies, the circuit performs the mathematical operation of differentiation (i.e)
the output waveform is the derivative of the input waveform.
The differentiator may be constructed from a basic inverting amplifier if an input resistor R1
is replaced by a capacitor C1.

 The expression for the output voltage can be obtained KCL eqn written at node V 2
as follows,
i c + i f =I B 1 −−−−−−−−−− (1 )
¿ , I B 1=0 ,
d ( v ¿ −V N )d v¿
C1 =C 1
dt dt
At node VN is at virtual ground potential i.e., VN=0, From eqn (1)
d ( v in −v N ) ( v o −V N )
C1 + =o
dt RF
d ( v in ) V o
C1 + =0
dt RF
Vo d ( v in )
=−C1
RF dt
d ( v in )
V o =−R F C 1 −−−−−−−−( 2)
dt

Since the differentiator performs the reverse of the integrator function.

Thus the output V0 is equal to RF C1 times the negative rate of change of the input voltage
Vin with time. The negative sign indicates a 180˚phase shift of the output waveform V 0with
 respect to the input signal.

The phasor equivalent is Vo(s) =

|V o /V in|=|−iωR F C1|=ωR F C1 ----------------- (3)
The above eqn can be rewritten as
f
|A 1|=
fa
1
f a=
2 πR F C1
Disadvantages:
|A 1|=1
 At f=fa, i.e., 0 dB, and the gain increases at a rate of 20dB/decade. This
makes the circuit unstable and break into oscillation.

 Sensitive to high frequency noise.

Practical Differentiator:

 Both stability and high frequency noise problems can be corrected by the addition of 2 com-
ponents. R1 and CF . This circuit is a practical differentiator.

 The input signal will be differentiated properly, if the time period T of the input signal is
larger than or equal to RF C1 (i.e) T > RF C1

Practical Differentiator
 A workable differentiator can be designed by implementing the following steps.

(i)Select fa equal to the highest frequency of the input signal to be differentiated then as-
suming a value of C1 < 1μf. Calculate the value of RF .
 (ii) Choose fb = 20fa and calculate the values of R1 and CF so that R1 C1 = RF CF .
Uses:
 Its used in wave shaping circuits to detect high frequency components in an input signal and
also as a rate of change and detector in FM modulators.

i/p and o/p waveform of practical differentiator.

Integrator:
Definition:A circuit in which the output voltage waveform is the integral of the input
voltage waveform is the integrator or Integration Amplifier. Such a circuit is obtained
by using a basic inverting amplifier configuration if the feedback resistor R F is re-
placed by a capacitor CF .

The expression for the output voltage V0 can be obtained by KVL eqn at node VN.

I B=i1 +i F −−−−−−−−−−( 1 )
 V ¿−V N d ( V 0−V N )
+C F =0
R1 dt

¿ , V N =0

V¿ d (V 0)
+CF =0
R1 dt

d V 0 −V ¿
CF =
dt R1
t
−1
V 0= ∫ V ¿ dt−−−−−−−−−(2)
R1 C F 0

 Eqn (2) indicates that the output is directly proportional to the negative integral of the
input volts and inversely proportional to the time constant R1 CF .
 Ex: If the input is sine wave -> output is cosine wave.
 If the input is square wave -> output is triangular wave.

These waveform with assumption of R1 Cf = 1, Vout =0V (i.e) C =0.

Practical Integrator:
  Practical Integrator to reduce the error voltage at the output, a resistor R F is connected
across the feedback capacitor CF .

 Thus RF limits the low frequency gain and hence minimizes the variations in the
output voltages. The frequency response of the basic integrator, shown from this fb is
the frequency at which the gain is dB and is given by,
1
f b=
2 πR F C F
 Both the stability and low frequency roll-off problems can be corrected by the addition
of a resistor RF in the practical integrator.
 Stability -> refers to a constant gain as frequency of an input signal is varied over a
certain range.
 Low frequency -> refers to the rate of decrease in gain roll off at lower frequencies.
 From the fig of practical Integrators, f is some relative operating frequency and
for frequencies f to fa to gain R F / R1 is constant. After fa the gain decreases at a rate
of 20dB/decade or between fa and fb the circuit act as an integrator. The gain limiting
frequency fa is given by
1
f a=
2 πR F C F
 Generally the value of fa and in turn R 1 CF and RF CF values should be selected
such that fa<fb. In fact, the input signal will be integrated properly if the time period
T of the signal is larger than or equal to RF CF, (i.e)
T≥RFCF
1
Where, R F C F = 2 πf
a

Uses:
 Most commonly used in analog computers.

 ADC

 Signal wave shaping circuits

10. Draw the circuit of a symmetrical emitter coupled differentail amplifier and derive
for CMRR. (Dec 2017, May 2018)
11. i) Draw the inverting amplifier circuit of an op amp in closed loop configuration. Obtain
the expression for the closed loop gain. (May 2018) ii) For an non inverting amplifier
using op amp assume R1=470 ohm and R2=4.7 Kohm. Calculate the closed loop voltage
gain of the amplifier. (May 2018) (Probable Part C)
Inverting amplifier: Refer question number 7
V0 Rf
ACL= =1+
Vi R1
3
4.7∗10
= 1+
470
ACL = 11

12. i) Explain the differential amplifier using op-amp. (Nov 2016)

Differential amplifier using op-amp:Refer question number 7
ii) Derive the expression for the output voltage Vo for the circuit shown below.
 Since, the differential voltage at the input terminals of the op-amp is zero, nodes 'a' and 'b' are
at the name potential, designated as v3. The nodal equation at 'a' is.

v 3−v 1 v 3 −v 0
+ =0
R1 R3
Rearranging, we get

( )
1 1 v1 vo
+ v3− =
R1 R3 R1 R3

and at 'b' is
v 3−v 2
=0
R2

v 3=v 2

Therefore

( )
1 1 v1 vo
+ v2− =
R1 R3 R1 R3

R3
(( 1 1
+
R 1 R3 )
v 2−
v1
R1)=V 0

13. Explain with neat circuit expressions about the working of (i) Inverting Amplifiers
(ii) Integrating circuit and derive the gain. (May 2019)
(i) Inverting Amplifiers : Refer question Number 7
(ii) Integrating circuit: Refer question Number 9
14. (i) Draw and explain the integrator circuit using an Op-Amp.
(ii) (ii) An inverting amplifier using the 741 IC must have a flat response upto
40Khz.The gain of the amplifier is 10. What maximum peak to peak input signal
can be applied without distorting the output. (Dec 2018) (Probable Part C)
i) Integrating circuit: Refer question Number 9
ii) F= 40KHz
Gain =10
Slew rate of OPAMP IC741 = 0.5V/µs
We know that
−6
Slewrate 0 . 5∗10
Vm(max) = = 3 = 1.99V Peak
2 πf 2∗3 . 14∗40∗10
 = 3.98 V peak to peak
The maximum peak to peak voltage for undistorted output is
Vid = Vm/A = 3.98/10 = 0.398 peak to peak

15. Determine the output voltage of the following circuits. (May 2017)

Solution:
i)Non inverting op-amp

(
V o = 1+
Rf
R¿
V¿ )
(
V o = 1+
5K
1K
5 )
V o =6 ×5=30V
ii)Non inverting adder
V o =−Rf
(
V 1 V 2 V3
+ +
R1 R2 R3 )
¿−2 K (2
+
1K 2K 2K
1
+
2
)
(1
¿−2 2+ −1
2 )
−2
3
2 ()
=−3 V

16. (i) Design an adder-subtractor circuit for Vo = 2V1+5V2-10V3. (Nov 2014)

The positive and negative terms can be added separately using two adders and then a
subtractor can be used.

For 2V1+5V2

Let Rf1=100KΩ
−Rf 1 Rf 1
V 01= V 1− V
R1 R2 2
Rf 1 100
=2 => R1=
R1 2
R1=50 K Ω
Rf 1 100
=5 => R2=
R2 5
R2=20 K Ω
⇒ V 01=−2V 1−5 V 2

For -10V3

Let Rf2=120KΩ
−Rf 2
V 02= V3
R3
Rf 2 120
=10 => R3=
R3 10
R3=12 KΩ
⇒ V 02=−10 V 3
Use the subtractor with all the resistance of same value of R=100 KΩ
The output of the subtractor is V0 = V02 – V01
V0 = -10V3 - (-2V1-5V2)
V0 = 2V1+5V2-10V3

(ii) Consider a lossy integrator as shown in figure. For the component values R 1 =
10kΩ,Rf= 100kΩ, Cf = 1nF. Determine the lower frequency limit of integration
and study the response for the inputs. (i) Step Input (ii) Square Input (iii) Sine In-
put. (Nov 2014)

R1 = 10kΩ,Rf= 100kΩ, Cf = 1nF

The lower frequency limit of integration and study the response for the Step Input
1 1
F1= = 3 −9 = 1.592 KHz
2 πRf Cf 2 π∗100∗10 ∗1∗10
For accuracy, input frequency shoud be ateast one decade (10 times) above.
Therfore lower frequency limit of integration = 15.92 KHz.
For step input of 1V peak step input 0≤ t ≤ 0.3ms, then the output votage at t=0.3ms
 (iii)Sine input

17.
For a max frequency of 100Hz, design a differentiator circuit and draw the frequency
response for the same. (Nov 2014)
1
f a=
2 π R F C1

1
select , f a=f max=100 Hz=
2 π RF C 1

Let C 1=0. 1 μF

1
Then R F= =15.9 kΩ
2 π ( 10 2 )( 10−7 )

Now,

1
f b=
2 π R1 C 1

1
Choose f b=10 f a=1 KHz=
2 π R1 C 1

Therefore

1
R 1= =1.59 kΩ
2 π ( 10 3 )( 10−7 )

Since R F C F =R 1 C 1

We get,
 3 −7
1.59 × 10 × 10
CF= 3
=0.01 μF
15.9× 10

Frequency Response:

Find the following for the given op-amp differential amplifier: (i) The gain of the
amplifier (ii) Input resistance (iii) Output voltage, when the inputs are 1sin(2000t)
V and 1.2sin(2000t) and the R1=R3=1.2K and R2=R4=22K. (May 2019)

(i) The gain of the amplifier = R2/R1 = (22*10^3)/(1.2*10^3) = 18.33

(ii) Since R1=R3&R2=R4, It acts as a sutractor.

Vo = (V2-V1)(R2/R1)
= (1.2sin(2000t) - 1sin(2000t))(22*10^3/1.2*10^3)
= 3.67 sin2000t V

18. Explain the operation of inverting and non-inverting configurations of Operation

Amplifiers. (Nov 2020)(May 2021)
Refer: Question number: 7
19. Discuss the various frequency compensation techniques for Operational Amplifiers. (Nov
2020) (May 2021)
Refer :Question number: 1
20. With neat illustration explain the various steps involved in the IC fabrication
process. (May 2017)
The basic processes involved in the fabrication of ICs are as follows:
 Silicon wafer preparation.
 Epitaxial growth
 Oxidation
4. Photolithography
 Diffusion
 Ion implantation
 Isolation Techniques
 Metallization
 Assembly Processing and packaging.

 Silicon Wafer preparation:

The following steps are involved in the preparation of Si-wafers:
• Crystal growth and doping
• Ingot trimming and grinding
• Ingot slicing
• Wafer polishing and etching
• Wafer cleaning
 Crystal growth and doping:
• The starting material for crystal growth is highly purified polycrystalline sil-
icon.
• The primary method of the crystal growth is The Czochralski method.
• The apparatus used for the crystal growth is called as Czochralski
crystal growth apparatus or puller.
• The puller has 4 important subsystems namely furnace, crystal puling
mechanism, ambient control and control systems. The simplified version
of Czochralski crystal puller is shown as:

• The furnace consists of a cru-

cible, crucible support, rotation mechanism and heating element
housed in a chamber.
• The Polycrystalline silicon together with an appropriate amount of
dopant is put in a quarts crucible.
• The material in the crucible is heated to temperature which is greater than
the melting point of the silicon, i.e. 1420°C.
• Then a small single crystal rod of silicon is immersed into molten mate-
rial. The rod is called as seed crystal.
• Lowering the seed crystal in molten silicon allows the crystal ingot
to form on the seed by solidification.
• The main function of crystal pulling assembly is to control the pull rate of
 seed crystal and crystal rotation both, with minimum vibrations and preci-
sion.
• During crystal growth the crystal is rotated slowly by stirring the
molten and averaging out
temperature gradients leading to inhomogeneous solidification.

 The silicon growth is generally conducted in a vacuum or in an inert gas like helium
or argon.
 Epitaxial Growth: (Describe about epitaxial growth process.Dec 2016)
The word epitaxy is derived from Greek word epi meaning 'upon' and the past tense
of the word teinon meaning 'arranged'. So, the epitaxy can be described as, arranging atoms
in single crystal fashion upon a single crystal substrate.

The basic chemical reaction used for the epitaxial growth of pure silicon is the hy-
drogen reduction of silicon tetrachloride.

The epitaxial films with specific impurity concentration are accomplished by introducing
phosphine (PH3) for the n-type and bi-borane (B2H6) for p-type doping into the silicon-tetra-
chloride hydrogen gas stream.

The process is carried out in a reaction chamber consisting of a long cylindrical quartz tube
encircled by an RF induction coil.

The silicon wafers are placed on a rectangular graphite rod called a boat. This boat is then
placed in the reaction chamber where the graphite is heated inductively to a temperature
1200°C. The various gases required for the growth of desired epitaxial layers are introduced
into the system through a control console.

 Oxidation:
The process in which a thin layer of silicon dioxide (SiO 2) formed on the surface of silicon
wafer using thermal growth technique is called Oxidation.

Si02 serves two very important purposes.

• Si02 is an extremely hard protective coating and is unaffected by al-
most all reagents except hydrofluoric acid.
• By selective etching, diffusion of impurities through carefully defined
windows in the Si02 can be accomplished to fabricate various compo-
nents.

The silicon wafers are stacked up in a quartz boat and then inserted into quartz furnace tube.
The Si-wafers are raised to a high temperature in the range of 950 to 1115°C and at the same
time, exposed to a gas containing O2 or H20 or both. The chemical reaction is

Si + 2H20 Si02 + 2H2

This oxidation process is called thermal oxidation because high temperature is used to
grow the oxide layer. The thickness of the film is governed by time, temperature and the
moisture content. The thickness of oxide layer is usually in the order of 0.02 to 2 µm.
Photolithography is the process of transferring geometric shapes on a mask to
the surface of a silicon wafer.
The Photolithography involves - two processes, namely:
i. Making of a photographic mask
ii. Photo etching
i. Making of a photographic mask
 The making of a photographic mask involves the following sequence of operations
-first the preparation of initial artwork and secondly, its reduction.
 The initial layout or artwork of an IC is normally done at a scale several hundred
times larger than the final dimensions of the finished monolithic circuit. This is be-
cause, for a tiny chip, larger the artwork, more accurate is the final mask.
 This initial layout is then decomposed into several mask layers, each corresponding
to a process step in the fabrication schedule, e.g., a mask for base diffusion, another
for collector diffusion, another for metallization and so on.
 The artwork is usually produced on a precision drafting machine, known as coordi-
natograph. The coordinatograph has a cutting head that can be positioned accurately
and moved along two perpendicular axes. The coordinatograph outlines the pattern
cutting through the red mylar without damaging the clear layer underneath.
 This rubylith pattern of individual mask is photographed and then reduced in steps
by a factor of 5 or 10 several times to finally obtain the exact image size. The final
image also must be repeated many times in a matrix array, so that many ICs will be
produced in one process.

ii. Photo etching

 Photo-etching is used for the removal of Si02 from desired regions so that the de-
sired impurities can be diffused.
  The wafer is coated with a film of photosensitive emulsion (Kodak Photoresist KPR).
 The thickness of the film is in the range of 5000-10000 A as shown in Fig.(a).
 The mask negative of the desired pattern) as prepared by steps described earlier is
placed over the photoresist coated wafer as shown in Fig.(b). This is now exposed to
ultraviolet light, so that KPR becomes polymerized beneath the transparent regions
of the mask. The mask is then removed and the wafer is developed using a chemical
(trichloroethylene) which dissolves the
unexposed/unpolymerized regions on the photoresist and leaves the pattern as shown in
Fig. (c).
 The polymerized photoresist is next fixed or cured, so that it becomes immune to
certain chemicals called etchants used in subsequent processing steps.
 The chip is immersed in the etching solution of hydrofluoric acid, which removes
the Si02 from the areas which are not protected by KPR as shown in Fig.(d).
 The etching process described is a wet etching process and the chemical
reagents used are in liquid form. A new process used these days is a dry etching
process called plasma etching.
 A major advantage of the dry etching process is that it is possible to achieve
smaller line openings compared to wet process.

5. Diffusion:{Explain the process of diffusion in detail? (Apr/May-2005, Nov/Dec-2011)}

The process of doping or adding impurity to the silicon wafer is called as diffusion.

 Diffusion is used to form bases, emitters and resistors in bipolar device.

 This uses a high temperature furnace having a flat temperature profile over a useful
length (about 20" length).
 A quartz boat containing about 20 cleaned wafers is pushed into the hot zone with
temperature maintained at about a 1000°C.
 Impurities to be diffused are rarely used in their elemental forms. Normally, com-
pounds such as B203 (Boron oxide), BCl3 (Boron chloride) are used for Boron and
P205 (Phosphorous pentaoxide) and POCl3 (Phosphorous oxychloride) are used as
sources of Phosphorous.
 A carrier gas, such as dry oxygen or nitrogen is normally used for sweeping the
impurity to the high temperature zone.
  The depth of diffusion depends upon the time of diffusion which normally extends to
2 hours.
 The diffusion of impurities normally takes place both laterally as well as vertically.
Therefore, the actual junction profiles will be curved as shown in the following Fig.

6. Ion Implantation:{Explain in detail about Ion implantation process? (Nov/Dec-2005)}

This is another technique used to introduce impurities into a silicon wafer. In this
process, silicon wafers are placed in a vacuum chamber and are scanned by a beam of high
energy dopant ions (borons for p-type and phosphorus for n-type). These ions are acceler-
ated by energies between 20 kV to 250 kV. As the ions strike the silicon wafers, they pene-
trate some small distance into the wafer. The depth of penetration of any particular type of
ion increases with increasing accelerating voltage.

It has two main advantages:

1. It is performed at low temperature.
In Ion implantation process, accelerating potential and the beam current are electrically
controlled from outside.
The main blocks of the ion-implanter are ion source, bending analyzer magnet, aperture,
acceleration tube, X-Y scanner plates, target chamber.
-The bending analyzer magnet selects the ions with desired charge to mass ratio with the
help of properly applied magnetic field.

7. Isolation Techniques {Describe in detail any two isolation techniques used to provide
isolation between various components in IC fabrication with illustrations? (May/June
2014)}
The most commonly used isolation techniques are:
i. p-n junction isolation
ii. Dielectric isolation

i.p-n junction isolation

In this isolation technique, p+ type impurities are selectively diffused into the n-type
epitaxial layer so as to reach p-type substrate as shown in Fig.

 This produces islands surrounded by p-type moats. It can be seen that these regions
are separated by two back-to-back p-n junction diodes.
 If the p-type substrate material is held at the most negative potential in the circuit,
the diodes will be reverse biased providing electric isolation between these islands.
The different components are fabricated in these isolation islands.

ii.Dielectric isolation
Here a layer of solid dielectric such as silicon dioxide or ruby completely surrounds
each component, thereby producing isolation, both electrical and physical.

 This isolating dielectric layer is thick enough so that its associated capacitance is
negligible. Also, it is possible to fabricate both pnp and npn transistor within the
same silicon substrate.
 Since this method requires additional fabrication steps, it becomes more expensive.
 This technique is mostly used for fabricating professional grade lCs required for spe-
cialised applications viz, aerospace and military, where higher cost is justified by su-
perior performance.
8. Metallization: {Describe the metallization process (May 2016)}
The purpose of this process is to produce a thin metal film layer that will serve to
make interconnections of the various components on the chip. Aluminium is usually used for
the metallization of most lCs as it offers several advantages.
The advantages are as follows:
1. It is relatively a good conductor (Aluminium)
2. Aluminium makes good mechanical bonds with silicon.
3. It forms low-resistance and so it is used for
metallization. Metallization process:
The process takes place in a chamber which is called as vacuum evaporation chamber.
 The chamber pressure is adjusted to range 10-6 to 10-7 Torr. The material to be evap-
orated is placed in a basket.
 Then using electron gun high power density electron beam is focused at the surface of
the material.

 After the metallization process is over, the thin film is patterned to form required in-
terconnections.
By using proper etching process aluminium is removed from unwanted regions.
Assembly processing and packaging: {Describe theAssembly processing and packaging
process with neat diagram (May 2016)}
Each chip is then mounted on a ceramic wafer and attached to a suitable package.
There are 3 different package configurations available:
1. Metal can package.
2. Ceramic flat package.
3. Dual –in-line type.
  The metal can packages are available in 8, 10 or 12 leads, whereas the flat or dual-
in-line package is commonly available in 8, 14 or 16 leads, but even 24 or 36 or 42
leads are also available for special circuits.
Ceramic packages, whether of flat type or dual-in-line are costly due to fabrication
process, but have the advantage of best hermetic sealing.
21. Describe metallization process, assembly processing and packaging with diagram.
(May 2016)
Metallisation process:
The purpose of this process is to produce a thin metal film layer that will serve to make in-
terconnections of the various components on the chip. Aluminium is usually used for the
metallization of most lCs as it offers several advantages.
The advantages are as follows:
1. It is relatively a good conductor (Aluminium)
2. Aluminium makes good mechanical bonds with silicon.
3. It forms low-resistance and so it is used for
metallization. Metallization process:
The process takes place in a chamber which is called as vacuum evaporation chamber.
 The chamber pressure is adjusted to range 10-6 to 10-7 Torr. The material to be evap-
orated is placed in a basket.
Then using electron gun high power density electron beam is focused at the surface of the
material
  After the metallization process is over, the thin film is patterned to form required in-
terconnections.
 By using proper etching process aluminium is removed from unwanted regions.

Assembly processing and packaging: {Describe the Assembly processing and packaging
process with neat diagram (May 2016)}
Each chip is then mounted on a ceramic wafer and attached to a suitable package.
There are 3 different package configurations available:
1. Metal can package.
2. Ceramic flat package.
3. Dual –in-line type.

 The metal can packages are available in 8, 10 or 12 leads, whereas the flat or dual-
in-line package is commonly available in 8, 14 or 16 leads, but even 24 or 36 or 42
leads are also available for special circuits.
Ceramic packages, whether of flat type or dual-in-line are costly due to fabrication
process, but have the advantage of best hermetic sealing.
22.  Impurities to be diffused are rarely used in their elemental forms. Normally, com-
 pounds such as B203 (Boron oxide), BCl3 (Boron chloride) are used for Boron and
P205 (Phosphorous pentaoxide) and POCl3 (Phosphorous oxychloride) are used as
sources of Phosphorous.
 A carrier gas, such as dry oxygen or nitrogen is normally used for sweeping the
impurity to the high temperature zone.
 The depth of diffusion depends upon the time of diffusion which normally extends to
2 hours.
 The diffusion of impurities normally takes place both laterally as well as vertically.
Therefore, the actual junction profiles will be curved as shown in the following Fig.

23. Describe in detail about the diffusion process of IC fabrication.

(May 2013)

Diffustion:
The process of doping or adding impurity to the silicon wafer is called as diffusion.

 Diffusion is used to form bases, emitters and resistors in bipolar device.

 This uses a high temperature furnace having a flat temperature profile over a useful
length (about 20" length).
 A quartz boat containing about 20 cleaned wafers is pushed into the hot zone with
temperature maintained at about a 1000°C.
 Impurities to be diffused are rarely used in their elemental forms. Normally, com-
pounds such as B203 (Boron oxide), BCl3 (Boron chloride) are used for Boron and
P205 (Phosphorous pentaoxide) and POCl3 (Phosphorous oxychloride) are used as
sources of Phosphorous.
 A carrier gas, such as dry oxygen or nitrogen is normally used for sweeping the
impurity to the high temperature zone.
 The depth of diffusion depends upon the time of diffusion which normally extends to
2 hours.
 The diffusion of impurities normally takes place both laterally as well as vertically.
Therefore, the actual junction profiles will be curved as shown in the following Fig.
24. Distinguish diffusion and ion implantation process in IC fabrication. (May 2016)
Diffusion: refer Q.No.23
Ion Implantation:
This is another technique used to introduce impurities into a silicon wafer. In this
process, silicon wafers are placed in a vacuum chamber and are scanned by a beam of high
energy dopant ions (borons for p-type and phosphorus for n-type). These ions are acceler-
ated by energies between 20 kV to 250 kV. As the ions strike the silicon wafers, they pene-
trate some small distance into the wafer. The depth of penetration of any particular type of
ion increases with increasing accelerating voltage.

It has two main advantages:

1. It is performed at low temperature.
2. In Ion implantation process, accelerating potential and the beam current are electrically
controlled from outside.

The main blocks of the ion-implanter are ion source, bending analyzer magnet, aperture,
acceleration tube, X-Y scanner plates, target chamber.
-The bending analyzer magnet selects the ions with desired charge to mass ratio with the
help of properly applied magnetic field.

25. Explain the basic processes used in silicon planar technology with neat diagram.
 (Dec 2017, Dec 2018)(Nov/Dec 2019)
Refer:20
26. Explain about the following:
Epitaxial growth and diffusion. ii) Photolithography iii) Masking and Photo etching.
(Nov 2013, Nov 2014, May 2016, Nov 2016)
Refer:Q.No.20

27. Elucidate the process of Oxidation in the IC Fabrication. (Nov 2020)(May 2021)
Refer:Q.No.20

28. Explain the principle of Instrumentation amplifier and derive the gain for that
circuit. Give its applications. (May 2013, May 2016, May 2017)

Introduction to instrumentation amplifier:

The special amplifier which is used for such a low level amplification with high
CMRR, high input impedance to avoid loading, low power consumption and some
other features is called as instrumentation amplifier.

The instrumentation amplifier is also called data amplifier and is basically a difference
amplifier.
The expression for its voltage gain is generally of the form,
𝑉0
𝐴=
𝑉2 − 𝑉1

Where 𝑉0 = output of the amplifier

𝑉2 − 𝑉1 = differential input which is to be amplified

Three Op-amp Instrumentation Amplifier:

Analysis of 3 Op-amp Instrumentation Amplifier

The output V0 is given by,

𝑅2
𝑉𝑜 = (𝑉02 − 𝑉01) − − − − − (1)
𝑅
The node A potential op-amp 𝐴1 is 𝑉1. From the realistic assumption, the potential of
node B is also 𝑉1. And hence potential of G is also 𝑉1.

The node D potential of op-amp A2 is V2. From the realistic assumption, the potential
of node C is also V2. And hence potential of H is also V2.

The input current of op-amp A1 andA2 both are zero. Hence current I remains same
through
Rf1RG and Rf2.

Applying ohm’s law between the nodes E and F we get,