Unit 1

DIGITAL LOGIC

Digital Logic:
Boolean Algebra, Basic and Universal Logic gates, Half adder, Full adder, Simplification of
logic expressions using K-maps, Multiplexer, De-multiplexer, Encoder and Decoder.

BOOLEAN ALGEBRA
George Boole in 1854 invented a new kind of algebra known as Boolean algebra. It is sometimes
called switching algebra. Boolean algebra is the mathematical frame work on which logic design
based. It is used in synthesis & analysis of binary logical function.
Laws of Boolean Algebra:
1. 0’=1
2. 1’=0
3. If A=0, A’=1
4. IF A=1, A’=0
5. A’’=A
6. A.0=0
7. A.1=A
8. A.A=A
9. A.A’=0
10. A+0=A
11. A+1=1
12. A+A=A
13. A+A’=1
14. A+AB=A(1+B)=A
15. A+A’B=A+AB+A’B=A+B(A+A’)=A+B

LOGIC GATES
• It is an electronic circuit which makes logic decisions. A logic gate is a digital circuit
with one or more input signal and only one output signal. All input or output signals
either low voltage or high voltage. A digital circuit is referred to as logic gate for simple
 reason i.e. it can be analyzed on the basis of Boolean algebra.
• To make logical decisions, three gates are used. They are OR, AND and NOT gate. These
logic gates are building blocks which are available in the form of IC.
• The input and output of the binary variables for each gate can be represented in a tabular
column or truth table.
1. OR Gate: The OR gate performs logical additions commonly known as OR function. The OR
gate has two or more inputs and only one output. The operation of OR gate is such that a
HIGH(1) on the output is produced when any of the input is HIGH. The output is LOW(0) only
when all the inputs are LOW.
• If A & B are the input variables of an OR gate and c is its output, then A+B. similarly for
more than two variables, the OR function can be expressed as Y=A+B+C.

• Logical Symbol:

A
Y
B

 Truth table

Input Output

A B Y= A+B

0 0 0

0 1 1

1 0 1

1 1 1
2. AND Gate : The AND gate performs logical multiplication, commonly known as AND
function. The AND gate has two or more inputs and a single output. The output of an AND gate
is HIGH only when all the inputs are HIGH. Even if any one of the input is LOW, the output will
be LOW. If a & b are input variables of an AND gate and c is its output, then Y=A.B

Logic Symbol

A
Y
B
Truth table

Input Output
A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1

3. Not Gate ( Inverter): The NOT gate performs the basic logical function called inversion or
complementation. The purpose of this gate is to convert one logic level into the opposite logic
level. It has one input and one output. When a HIGH level is applied to an inverter, a LOW level
appears at the output and vice-versa.
4.NAND Gate: The output of a NAND gate is LOW only when all inputs are HIGH and
output of the NAND is HIGH if one or more inputs are LOW.

A
Y
B

5. NOR Gate: The output of the NOR gate is HIGH only when all the inputs are LOW.
 A
Y
B

6.XOR Gate or Exclusive OR gate: In this gate output is HIGH only when any one of the
input is HIGH. The circuit is also called as inequality comparator, because it produces
output when two inputs are different. When both the inputs are high, then the output is
low.

A
Y
B

7. XNOR Gate or Exclusive NOR Gate: An XNOR gate is a gate with two or more inputs
 and one output. XNOR operation is complimentary of XOR operation. i.e. The output of
XNOR gate is High, when all the inputs are identical; otherwise it is low.

A
Y
B

Universal Logic Gate

NAND and NOR gates are called Universal gates or Universal building blocks, because both
can be used to implement any gate like AND,OR an NOT gates or any combination of these
basic gates.

• NAND gate as Universal gate

NOR gate as Universal gate:
De Morgan’s Theorems:
It is one of the important properties of Boolean algebra. It is extensively useful in simplifying
complex Boolean expression.
Theorem 1: It states that “the compliments of product of two variables equal to sum of the
compliments of individual variable”.

X Y  X  Y

Theorem 2: It states that compliment of sum of two variables is equal to product of compliment
of two individual variables.

X  Y  X Y
1. Realize EXOR Gate using only minimum NAND Gates

2. Realize EXOR Gate using only NOR Gates

XNOR + NOR = XOR i.e. Add NOR gate to the ouptut of XNOR gate. Here is the boolean
algebra for XOR gate:

3. Realize EX-NOR Gate using only minimum NOR Gates

4. Realize EX-NOR Gate using only NAND Gates
XOR + NAND Inverter(NOT) = XNOR i.e. Add NOT Gate to the output of XOR gate as shown
in the image above. Here is the boolean algebra for XNOR gate:
Half Adder:
A combinational circuit which performs the arithmetic addition of two binary digits is called
Half Adder. In the half adder circuit, there are two inputs, one is addend and augends and two
outputs are Sum and Carry.

A Sum
Half Adder
Carry
B

Logic Expression :

Circuit Symbol of Half adder:

Full Adder: The full adder is a combinational circuit that performs the arithmetic sum of three
input bits.
• It consists of three inputs and two outputs. Two of the inputs are variables, denoted by A
and B, represent the two significant bit to be added. The third input Cin represents carry
form the previous lower significant position.

A Sum
B Full Adder
Carry
Cin
Truth Table for Full Adder
Full adder Circuit using two Half adders:

Fig 5.4: Full adder Circuit using two Half adders

SIMPLIFICATION USING BOOLEAN ALGEBRA
A simplified Boolean expression uses the fewest gates possible to
implement a given expression.

Example
Using Boolean algebra techniques, simplify this expression:

AB + A(B + C) + B(B + C)
Solution
Step 1: Apply the distributive law to the second and third terms in the
expression, as follows:
AB + AB + AC + BB + BC
Step 2: Apply rule 7 (BB = B) to the fourth term.
AB + AB + AC + B + BC
Step 3: Apply rule 5 (AB + AB = AB) to the first two terms.
AB + AC + B + BC
Step 4: Apply rule 10 (B + BC = B) to the last two terms.
 AB + AC + B
Step 5: Apply rule 10 (AB + B = B) to the first and third terms.
B+AC
At this point the expression is simplified as much as possible.

Boolean Algebra Practice Problems

1) a 0  14) y y y 

2) a 0  15) xy x y 
3) a a  16) x yx  

4) a a  17) (w x y z) y 

5) a ab  18) (x y)(x y) 
6) a ab  19) w [w (wx)] 
7) a(a b)  20) x[x (xy)] 
8) ab ab  21) (x x)  

22) (x x) 


9) (a b)(a b)  

 

10) a(a b c ...)  23) w (wxyz) 

For (11),(12), (13), f (a, b, c) a b c 24) w (wxyz) 
11) f (a, b, ab)  25) xz xy zy 
12) f (a, b, a b)  26) (x z)(x y)(z y) 
13) f [a, b, (ab)]  27) x y xyz 

Solutions to the Boolean Algebra Practice Problems

1) a 0 a
2) a 0 0
3) a a 1
1) a a a
5) a ab a(1 b) a
6) a ab (a a)(a b) a b
7) a(a b) aa ab ab
8) ab ab b(a a) b
9) (a b)(a b) aa ab ba bb a ab ab a(1 b b) a
10) a(a b c ...) aa ab ac ... a ab ac ... a
11) f (a, b, ab) a b ab a b
12) f (a, b, a b) a b ab a b a 1
13) f [a, b,(ab)] a b (ab) a b a b 1
14) y y y  y
15) xy x y x( y y) x
16) x yx x(1 y) x
17) (w x y z) y y
18) (x y)(x y) x
19) w [w (wx)] w
20) x[x (xy)] x
21) (x x) x
22) (x x) 0
23) w (wxyz) w(1 xyz) w
24) w (wxyz) w(w x y z) w
25) xz xy zy xz xy
26) (x z)(x y)(z y) (x z)(x y) xy xz
27) x y xyz x y z
 Draw a logic circuit for (A + B)C.

Soln:

 Draw a logic circuit for A + BC + D.

Soln:

 Draw a logic circuit for AB + AC.

Soln:

 Draw a logic circuit for (A + B)(C + D)C.

Soln:
MULTIPLEXER (MUX)

 A MUX is a digital switch that has multiple inputs (sources) and a single output
(destination).

 The select lines determine which input is connected to the output

 MUX Types
2-to-1(1selectline)
4-to-1(2selectlines)
8-to-1(3selectlines)
16-to-1(4selectlines)

 Normally there are 2n input lines and n select lines

 The basic multiplexer has several data input lines and a single output line and hence the
name „Many to One‟.
 2:1 Mux
 2:1 Mux contains 2 input lines, 1 select line and one output line

Fig 5.8: 2:1 MUX

 4:1 MUX
 4:1 MUX contains 4 input lines, 2 select lines and one input line

Logic Symbol
Truth Table

S0 S1 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

S0 S1
Logic Expression:

Y= S0’ S1’D0 +S0’ S1 D1 +S0 S1’ D2+ S0 S1 D3

No of AND Gates : 04
No of NOT Gates : 02
No of OR Gates : 01
Total Gates : 07
8:1 MUX:

 No of Inputs (2n): 08
 No of select inputs ‘n’ :03
 No of output : 01

Logic Expression:

Y= S0’ S1’ S2’ D0+S0’ S1’ S2 D1+ S0’ S1 S2’ D2+ S0’ S1 S2 D3+S0 S1’ S2’
D4+ S0 S1’ S2 D5+ S0 S1 S2’ D6+ S0 S1 S2 D7
DEMULTIPEXER (De-MUX)

• A DEMUX is a digital switch with a single input (source) and a multiple outputs
(destinations).

• The select lines determine which output the input is connected to. The selection
of specific output is controlled by the values of „n‟ select lines.

• DEMUX Types
1-to-2(1selectline)
1-to-4(2selectlines)
1-to-8(3selectlines)
1-to-16(4selectlines)
1:4 DEMUX:

Input = 01
Select lines ‘n’= 2
Outputs = 2n = 4

Logic symbol:

Truth Table:
S0 S1 D0 D1 D2 D3
0 0 X 0 0 0
0 1 0 X 0 0
1 0 0 0 X 0
1 1 0 0 0 X
Logic Expression:

D0=S0‟ S1‟ X
D1= S0‟ S1 X
D2= S0 S1‟ X
D3= S0 S1 X
1: 4 DEMUX Circuit:

S0 S1

 No of Gates for 1:4 DEMUX

AND Gates= 04
NOT Gates = 02
ENCODERS:

 Device which converts one binary code to another

 Multiple inputs , multiple outputs
 Converts complex to simplest form
 More inputs, less outputs
DECODER

 Device which transforms the coded bits to generate the original data again
 Multiple inputs multiple output logic circuit
 It converts coded inputs into coded outputs, where the inputs and outputs are different
 Less inputs with more outputs
 It takes in „n‟ input and gives out 2n outputs

2 to 4 Decoder Logic symbol and Truth table:

3 to 8 decoder: (Binary to Octal Converter)

A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0
 1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Circuit diagram for 3 to 8 decoder: