COMPUTER ARCHITECTURE

Optimizing Pipelined Data Paths: Strategies for Hazard Mitigation and

Performance Enhancement.

Word count: 6465

 GROUP E

NAMES ROLL NUMBERS

Uche-Ukah Chimzyterem Janet 10012200064

Papa Yaw Eyram Dartey 10022200129

Acsah Nhyira Okla 10012200009

Terence Anquandah 10022200077

Farima Konaré 10012200004

Yaw Acheampong Ahenkora Gyamera 10022200141

Gerald Nii Amamoo 10022200149

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 ABSTRACT

Computer organization and architecture are critical components in the creation of high-
performance computing systems. This study goes into the underlying ideas of pipelining, with an
emphasis on its application to improve processor performance. Pipelining enables the
simultaneous execution of many instructions through a number of steps, improving instruction-
level parallelism, throughput, and latency. The paper begins by discussing the reason for
pipelining and its advantages.

Key components of pipelined systems, such as input and output buffers, are discussed
in detail, emphasizing their role in facilitating efficient data flow. Additionally, the importance of
pipelined data path and control mechanisms is highlighted, underscoring the need for seamless
coordination between pipeline stages.

The research further explores various types of pipeline hazards, including structural,
data, and control hazards, along with strategies for detection and resolution. Techniques such as
forwarding and stalling are examined for mitigating data hazards, while the impact of branch
instructions on pipeline performance is also addressed.

The ARM Cortex-A72 pipeline architecture is used as a case study to demonstrate these
principles in action, offering useful insights into real-world implementation issues and
improvements.

In conclusion, this research offers a comprehensive understanding of pipelining

principles, pipeline hazards, and their significance in modern computer architecture. This
knowledge is essential for the design and optimization of high-performance processors and
computing systems.

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 Contents

ABSTRACT i

Contents
ii

List of Figures i
v

Chapter 1 Introduction
1

1.1 Research Aims and Outline of the Report .......................................................................

2

1.2 Background of this

Report .................................................................................................3

1.3 Importance of this

Report ..................................................................................................4

1.4 Motivation of this

Report ..................................................................................................5

1.4.1 Contributions of this Report ....................................................................................

6

1.5 Journey Ahead of this Report ...........................................................................................7

1.6 Organization of the

Report .................................................................................................8

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Chapter 2 Fundamentals of Pipelining
10

2.1
Introduction .....................................................................................................................11

2.2 Components of
Pipelining ...............................................................................................13

2.3 Types of
Pipelining ........................................................................................................15

2.4 Advantages of
Pipelining..................................................................................................22

2.5 Historical
Context ............................................................................................................22

2.6
Summary .........................................................................................................................23

Chapter 3 Pipelined Data Path and Control

25

3.1
Introduction ......................................................................................................................26

3.2
Components ......................................................................................................................27

3.3
Architecture ......................................................................................................................28

3.3.1 Trade-offs and

Challenges ........................................................................................28

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 3.4 Data Flow in Pipelined
Systems .......................................................................................29

3.5 Control Signals and Synchronization ..............................................................................31

3.6 Summary .........................................................................................................................32

Chapter 4 Pipeline Hazards

34

4.1
Introduction .......................................................................................................................35

4.2 Types of
Hazards ...............................................................................................................36

4.3 Structural
Hazards .............................................................................................................36

4.4 Data
Hazards .....................................................................................................................36

4.5 Control Hazards ...............................................................................................................36

4.6 Mitigation
Strategies ........................................................................................................36

4.6
Summary ...........................................................................................................................37

Summary
38

References
49

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 List of Figures

2.1 Diagram of the idea of a pipeline ........................................................................................12

2.2 Diagram of an instruction pipeline ....................................................................................17

2.3 Illustration of the arithmetic pipeline ..................................................................................20

3.1 Flow chart of Pipelining stages .........................................................................................26

3.4 A Pipeline Data path ...........................................................................................................30

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 Chapter 1

Introduction

1.1 Research Aims and Outline of the Report

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This report delves deeply into key topics in computer structure and design, with a particular
emphasis on pipelining, pipelined data path and control, and pipeline hazards. The key objectives
of this research project are as follows:

 Comprehensive Examination of Pipelining: The Research is to perform a detailed inquiry

into the notion of pipelining, attempting to understand its fundamental principles,
benefits, and potential pitfalls. The purpose of diving into pipelining is to give a
comprehensive understanding of its functioning, processes, and applications in current
computer systems.

 In-Depth Analysis of Pipelined Data Path and Control: Building on the basic concept of
pipelining, the study intends to dive into the numerous components and mechanisms that
regulate pipelined data route and control. The goal of thorough analysis is to untangle the
complexity of data flow orchestration inside pipelined systems, revealing light on the
vital role of control signals and synchronization techniques.

 Identification and Analysis of Pipeline Hazards: Pipeline hazards provide substantial

issues for the design and optimization of pipelined computer systems. As a result, a
primary goal of this research is to detect, categorize, and assess various types of pipeline
hazards, such as structural, data, and control hazards. By investigating the origins,
implications, and potential mitigation measures for pipeline risks, the study hopes to give
significant insights for addressing these challenges in computer architecture.

 Proposal of Effective Strategies for Hazard Mitigation: To address the issues provided by
pipeline hazards, the research seeks to suggest effective risk-mitigation techniques and
solutions. The goal is to establish strong procedures and strategies for dealing with
pipeline risks in computer organization and architecture by combining theoretical insights
and practical concerns. The project intends to contribute to the creation of durable and
high-performance computing systems by employing novel methodologies and rigorous
analysis.

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  Integration of Theory and Practice: To deepen research findings and increase their
practical significance, real-world examples and case studies will be used to support
theoretical discussions. The project aims to bridge the gap between theory and practice by
investigating the implementation of pipelining principles and hazard mitigation measures
in realistic settings, promoting a better understanding of their consequences in real-world
computing systems.

 Contribution to the Field of Computer Organization and Architecture: The ultimate goal
of this research project is to contribute to the improvement of computer organization and
architecture. By covering core concepts such as pipelining, pipelined data route and
control, and pipeline risks, the research intends to broaden the field's collective
knowledge base and give useful insights for future research and development efforts.

1.2 Background of this Report

In the dynamic landscape of computer organization and architecture, the intricate structure and
behavior of computing systems play a pivotal role in shaping their efficiency and performance.
At the heart of this domain lies the concept of pipelining, a fundamental technique that has
revolutionized processor performance by facilitating the simultaneous execution of multiple
instructions.

Pipelining operates on the principle of breaking down the execution of instructions

into discrete stages, each performing a specific operation. This enables overlapping execution,
where one instruction can be processed in a subsequent stage while another instruction is being
fetched or decoded, thus maximizing throughput and overall system performance.

Moreover, pipelined data path and control mechanisms form the backbone of pipelined
architectures, orchestrating the seamless flow of data and control signals across various pipeline
stages. These mechanisms ensure the efficient coordination and synchronization of operations,
enabling the smooth progression of instructions through the pipeline.
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 However, despite its benefits, pipelining also introduces the challenge of pipeline
hazards – situations where the smooth execution of instructions is disrupted, leading to delays or
errors. Structural hazards arise from resource conflicts, data hazards occur when instructions
depend on the results of previous instructions, and control hazards stem from branch instructions
altering the control flow.

Understanding these fundamental concepts – pipelining, pipelined data path and

control, and pipeline hazards – is indispensable for the design and optimization of high-
performance computing systems. By comprehending the intricacies of pipelining and its
associated challenges, architects and designers can develop strategies to maximize system
throughput, minimize latency, and ensure the efficient execution of instructions.

In summary, the background of this thesis underscores the critical importance of

pipelining in computer organization and architecture, emphasizing its role in enhancing
processor performance and highlighting the need for comprehensive understanding and effective
management of pipeline hazards.

1.3 Importance of this Report

The significance of this thesis extends beyond mere academic inquiry; it holds profound
implications for the advancement of computer organization and architecture. At its core, this
research endeavor aims to deepen the understanding of pivotal concepts such as pipelining,
pipelined data path and control, and pipeline hazards, thereby illuminating pathways toward the
design and implementation of computing systems that are not just efficient but also reliable.

By delving into these foundational concepts, this thesis endeavors to unravel the
complexities inherent in modern computing architectures. Through meticulous analysis and
exploration, it seeks to unearth the underlying principles and mechanisms that govern the
operation of pipelined systems. This deeper understanding, in turn, provides architects and
designers with invaluable insights into the optimization of computing systems, enabling them to
harness the full potential of pipelining techniques.

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 Moreover, the proposed strategies for handling pipeline hazards represent a significant
contribution to the field. In an era characterized by ever-increasing computational demands and
complexity, the effective mitigation of pipeline hazards is paramount. By devising innovative
solutions and methodologies for addressing these challenges, this thesis offers a pathway to
enhanced system reliability and performance.

Furthermore, the implications of this research extend beyond the confines of academia,
reverberating throughout the broader landscape of modern computing. In an age where
computing systems underpin virtually every aspect of society, from critical infrastructure to
cutting-edge research, the importance of efficient and reliable systems cannot be overstated. By
equipping practitioners and researchers with the knowledge and tools to navigate the intricacies
of pipelining and pipeline hazards, this thesis contributes to the collective effort to address the
critical challenges facing modern computing.

In essence, the significance of this thesis lies not only in its academic rigor and scholarly
contribution but also in its potential to drive real-world impact. By informing the design and
implementation of computing systems that are both efficient and reliable, it lays the groundwork
for a future where technology is not just powerful but also trustworthy, enabling transformative
advancements across a myriad of domains.

1.4 Motivation of this Report

The motivation driving this thesis is deeply rooted in the ever-evolving landscape of computer
organization and architecture, which is characterized by a relentless increase in complexity. As
computing systems evolve to meet the demands of modern applications and workloads, the
imperative for efficient and rapid processing becomes increasingly pronounced. In this context,
pipelining emerges as a fundamental concept, offering a promising avenue to enhance processing
speed through parallel execution.

The concept of pipelining revolutionizes the traditional sequential execution of

instructions by breaking down the execution process into a series of discrete stages. This allows
multiple instructions to be executed simultaneously, thereby maximizing the utilization of

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computational resources and improving overall system throughput. By harnessing the power of
pipelining, computing systems can achieve unprecedented levels of performance, enabling them
to tackle complex computational tasks with greater efficiency and agility.

However, the benefits of pipelining are not without their challenges. The presence of
pipeline hazards poses a significant obstacle to the seamless execution of instructions within a
pipelined architecture. Structural hazards, arising from resource conflicts, data hazards stemming
from dependencies between instructions, and control hazards resulting from branch instructions,
can all disrupt the smooth flow of instructions through the pipeline, leading to delays and
inefficiencies.

It is imperative, therefore, to confront these challenges head-on and develop effective

mitigation strategies to ensure the robustness and reliability of pipelined computing systems. The
motivation driving this thesis lies in the recognition of the critical importance of addressing these
pipeline hazards. By gaining a thorough understanding of the underlying causes and implications
of pipeline hazards, this research endeavor seeks to devise innovative solutions and
methodologies for mitigating their impact.

Ultimately, the motivation behind this thesis is fueled by the aspiration to advance the
state-of-the-art in computer organization and architecture. By addressing the challenges posed by
pipeline hazards and proposing effective mitigation strategies, this research aims to contribute to
the development of computing systems that are not only efficient and fast but also reliable and
resilient. In doing so, it seeks to pave the way for future advancements in the field, enabling the
realization of the full potential of pipelining in modern computing.

1.4.1 Contributions of this Report

This thesis endeavors to make substantial strides in the realm of computer organization and
architecture by delving into the intricate intricacies of pipelining, pipelined data path and control,
and pipeline hazards. Through an exhaustive exploration, it aims to not only deepen but also
broaden the collective understanding of these fundamental concepts within the field.

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 By offering a comprehensive overview of pipelining, the research aims to peel back the
layers of complexity surrounding this pivotal technique, shedding light on its underlying
mechanisms and operational principles. Through meticulous analysis and insightful examination,
it seeks to elucidate the nuances of pipelining, from its benefits and applications to its limitations
and challenges.

Moreover, the thesis ventures into the realm of pipelined data path and control,
unraveling the intricate components and mechanisms that govern data flow within pipelined
architectures. By shedding light on these critical aspects, the research aims to demystify the
complexities of data path management and control signal synchronization, thereby empowering
stakeholders to optimize the performance and efficiency of computing systems.

In addition to its comprehensive exploration of pipelining and pipelined data path and
control, the thesis delves into the realm of pipeline hazards – a formidable challenge confronting
modern computing architectures. By identifying, analyzing, and proposing strategies for
mitigating pipeline hazards, the research aims to fortify computing systems against potential
disruptions and inefficiencies. Through innovative approaches and effective mitigation strategies,
the thesis endeavors to enhance the reliability, robustness, and efficiency of computing systems,
thereby paving the way for advancements in high-performance computing.

Furthermore, the proposed strategies for handling pipeline hazards hold significant
promise for informing the design and implementation of more resilient and efficient computing
systems. By offering practical insights and actionable recommendations, the thesis aims to
empower researchers and practitioners to address critical challenges in modern computing
architecture. The findings of this research endeavor are poised to catalyze advancements in the
field, driving innovation and shaping the future trajectory of high-performance computing.

1.5 Journey Ahead of this Report

The journey ahead encompasses a multifaceted exploration of pipelining, pipelined data path and
control, and pipeline hazards.

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 Chapter 2 will delve into the intricacies of pipelining, highlighting its benefits,
drawbacks, and real-world applications. Chapter 3 will shift focus to the components and
mechanisms of pipelined data path and control, providing insights into data flow orchestration.

Chapter 4 will confront pipeline hazards head-on, dissecting their types, causes, and
implications. Chapter 5 will propose strategies for handling pipeline hazards, offering practical
solutions to mitigate risks.

Finally, Chapter 6 will synthesize the findings and contributions of the thesis,
providing a comprehensive conclusion to the research endeavor.

1.6 Organization of the Report

The report is meticulously structured into six cohesive chapters, each dedicated to elucidating
specific facets of the research topic. Chapter 1 serves as an introductory section, meticulously
delineating the research aims and providing a comprehensive outline of the subsequent chapters.

Chapters 2 through 5 constitute the core of the report, delving deeply into the intricacies
of pipelining, pipelined data path and control, pipeline hazards, and strategies for effectively
mitigating these hazards, respectively. Each chapter offers a comprehensive exploration of its
respective subject matter, drawing upon theoretical frameworks, empirical evidence, and
practical insights to provide a nuanced understanding.

Chapter 6 serves as the culminating section, presenting a comprehensive conclusion that

synthesizes the myriad findings and contributions articulated throughout the thesis. Through a
meticulous analysis of the research outcomes, this chapter offers valuable insights, implications,
and avenues for future research endeavors within the domain of computer organization and
architecture.

The structured organization of the report ensures coherence and clarity, facilitating a
systematic progression through the intricate layers of the research topic. By delineating each
aspect with precision and rigor, the report aims to provide readers with a comprehensive

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understanding of pipelining, pipelined data path and control, pipeline hazards, and effective
strategies for managing these hazards within the context of modern computing systems.

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 Chapter 2

Fundamentals of Pipelining

2.1 Introduction
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Pipelining is a method of implementing the execution of multiple instructions simultaneously by
overlapping their actions, exploiting the inherent parallelism in the instruction execution process.
In contemporary CPU design, pipelining is a crucial technique employed to enhance processor
speed.

Imagine a package boxing facility as a representation of pipelining, where the

packaging process mirrors an assembly line with distinct stages. In this setup, the first stage
involves inspecting and placing items into boxes, and concurrently, another worker is preparing
the next item for boxing. The second stage focuses on sealing boxes for shipment, with one box
being sealed while another receives final touches. Subsequently, the third stage handles labeling
and sorting, ensuring a continuous flow of packages ready for dispatch. In the final stage,
packages undergo quality control before being dispatched, while the next set is already in the
labeling and sorting stage. This parallel execution of tasks in different stages optimizes the
efficiency of the packaging process, akin to how an assembly line enhances the simultaneous
production of various items.

Similarly, in pipelining, different stages of instruction execution are overlapped,

optimizing the overall processing efficiency.

In a computer pipeline, each step in the pipeline completes a part of an instruction

throughput of an instruction pipeline is determined by how often an instruction exits the pipeline.
Because the pipe stages are hooked together, all the stages must be ready to proceed at the same
time, just as we would require in an assembly line. (Nitin J, 2010).

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 Figure 2.1: Diagram of the idea of a pipeline (Studytonight, n.d).

Pipeline system is like the modern-day assembly line setup in factories. For example,
in a car manufacturing industry, huge assembly lines are setup and at each point, there are robotic
arms to perform a certain task, and then the car moves on ahead to the next arm.

The pipeline is divided into logical stages connected to each other to form a pipe-like
structure. Instructions enter from one end and exit from the other. Pipelining is an ongoing,
continuous process in which new instructions, or tasks, are added to the pipeline and completed
tasks are removed at a specified time after processing completes. The processor executes all the
tasks in the pipeline in parallel, giving them the appropriate time based on their complexity and
priority. Any tasks or instructions that require processor time or power due to their size or
complexity can be added to the pipeline to speed up processing (Rahul Awati, 2022).

The performance of a pipeline is assessed using two primary metrics: throughput and
latency (Sharma et al., n.d). Throughput measures the number of instructions completed per unit
of time, reflecting the overall processing speed of the pipeline. Higher throughput indicates a
faster processing speed and can be influenced by factors such as pipeline length, clock frequency,
efficiency of instruction execution, and the presence of pipeline hazards or stalls. On the other

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hand, latency gauges the time taken for a single instruction to complete its execution,
representing the delay or time it takes for an instruction to pass through pipeline stages. Lower
latency signifies better performance and is influenced by pipeline length, depth, clock cycle time,
instruction dependencies, and pipeline hazards.

2.2 Components of Pipelining

The components of pipelining typically refer to the functional units or hardware elements that
perform specific tasks within each stage of the pipeline. These components work together to
execute instructions efficiently. The components of pipelining can vary depending on the specific
architecture and design choices, but some common components include:

 Instruction Fetch Unit (IFU): This component is responsible for fetching instructions
from memory or instruction cache. It retrieves the next instruction to be executed and
prepares it for decoding.

 Instruction Decode Unit (IDU): The instruction decode unit decodes the fetched
instruction, determining its opcode and operand references. It prepares the instruction for
execution by identifying the required resources and operations.

 Execution Unit (EU): The execution unit performs the actual computation or operation
specified by the decoded instruction. This unit can include various functional units such
as arithmetic logic units (ALUs), floating-point units (FPUs), and other specialized
execution units for specific instructions.

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 Memory Unit (MU): The memory unit handles memory-related operations, including data
accesses (reads and writes) to main memory or cache. It manages loading operands from
memory, storing results back to memory, and handling data dependencies.

 Write-back Unit (WBU): After the execution of an instruction is completed, the write-
back unit updates the processor's register file or internal registers with the results of the
computation. It ensures that the correct data is stored in the appropriate destination
register.

 Control Unit (CU): The control unit manages the control flow of instructions through the
pipeline. It coordinates the timing of instruction execution, controls the activation of
pipeline stages, and handles branching and control hazards.

 Pipeline Registers: These are storage elements located between pipeline stages that hold
the intermediate results of instructions as they progress through the pipeline. Pipeline
registers facilitate the flow of data between pipeline stages and help maintain proper
instruction sequencing.

 Forwarding Logic (or Data Hazard Unit): This component detects and resolves data
hazards by forwarding data from the output of one pipeline stage to the input of another,
bypassing intermediate pipeline registers. Forwarding logic ensures that instructions can
proceed without stalling due to dependencies on previous instructions.

 Branch Prediction Unit (BPU): In processors with branch prediction capabilities, the
branch prediction unit predicts the outcome of conditional branch instructions to
minimize the impact of branch mispredictions on pipeline performance. It helps maintain

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 the flow of instructions through the pipeline by predicting the target address of branch
instructions.

These components collaborate to allow for the concurrent execution of instructions in

a pipelined processor, improving performance and efficiency.

2.3 Types of Pipelining

Pipelining is divided into two categories which are:

 Instruction Pipelining
 Arithmetic Pipelining

Instruction Pipelining
Pipeline processing can occur not only in the data stream but in the instruction stream as well.

Most of the digital computers with complex instructions require instruction pipeline
to carry out operations like fetch, decode and execute instructions.

In general, the computer needs to process each instruction with the following sequence of steps:

1. Fetch instruction from memory.

2. Decode the instruction.
3. Calculate the effective address.
4. Fetch the operands from memory.
5. Execute the instruction.
6. Store the result in the proper place.

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Each step is executed in a particular segment, and there are times when different segments may
take different times to operate on the incoming information. Moreover, there are times when two
or more segments may require memory access at the same time, causing one segment to wait
until another is finished with the memory.

The organization of an instruction pipeline will be more efficient if the instruction

cycle is divided into segments of equal duration. One of the most common examples of this type
of organization is a four-segment instruction pipeline.

A four-segment instruction pipeline combines two or more different segments and

makes it as a single one. For instance, the decoding of the instruction can be combined with the
calculation of the effective address into one segment (javatpoint, n.d)

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Figure 2.2: Illustration above shows the diagram of an instruction pipeline (javapoint,
n.d).

 Segment 1

The implementation of the instruction fetch segment can be done using the FIFO or first-in, first-
out buffer.

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  Segment 2

In the second segment, the memory instruction is decoded, and the effective address is then
determined in a separate arithmetic circuit.

 Segment 3

In the third segment, some operands would be fetched from memory.

 Segment 4

The instructions would finally be executed in the very last segment of a pipeline organization.
(byjus, n.d).

Advantages of Instruction Pipelining:

 Enhanced Throughput: The Instruction Pipeline boosts overall system throughput by

concurrently processing multiple instructions, enabling the execution of a greater number
of instructions within a specified timeframe.

 Reduced Latency: The overlapping nature of pipeline stages diminishes the time taken
for an instruction to finish, leading to decreased latency and faster instruction execution.

 Optimized Resource Utilization: Instruction Pipelining maximizes the use of

computational resources, keeping the processor occupied as instructions progress through
pipeline stages simultaneously. This approach enhances the efficiency of hardware
resources.

 Increased Performance: The simultaneous execution of instructions in parallel results in

heightened performance, allowing the processor to manage a greater quantity of
instructions per unit of time and improving overall computational speed.

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 Nevertheless, Instruction Pipelining poses certain challenges. Careful management of
dependencies between instructions, such as data or control dependencies, is essential to ensure
accurate execution and maintain instruction order. Additionally, pipeline hazards, including data
or control hazards, may emerge, necessitating special techniques such as forwarding or branch
prediction for resolution.

Arithmetic Pipelining
Pipeline arithmetic units are generally discovered in very large-speed computers. It can execute
floating-point operations, multiplication of fixed-point numbers, and the same computations
encountered in mathematical problems.

The inputs to the floating-point adder pipeline are two normalized floating-point
binary numbers represented as

X = A x 2a

Y = B x 2b

Where A and B are two fractions that define the mantissa and a and b are the
exponents. The floating-point addition and subtraction can be implemented in four segments, as a
displayed figure. The registers labeled R is located between the segments to save intermediate
outcomes. The sub operations that are implemented in the four segments are –

 It can compare the exponents.

 It can align the mantissa.
 It can add or subtract the mantissa.
 It can normalize the result.

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The following block diagram describes the sub operations implemented in each segment of the
pipeline.

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 Figure 2.3: Illustration of the arithmetic pipeline (ginni, 2021)

Comparing exponents through subtraction involves determining the difference

between them. The larger exponent is chosen to be the exponent of the result. The disparity in
exponents dictates how many times the mantissa associated with the smaller exponent should be
shifted to the right.

Align the mantissa

The mantissa related to the smaller exponent is transferred as per the difference of exponents
regulate in segment one.

X = 0.9504 * 103

Y = 0.08200 * 103

Add mantissa
The two mantissas are added in segment three.

Z = X + Y = 1.0324 * 103

Normalize the result

After normalization, the result is written as

Z = 0.1324 * 104

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2.4 Advantages of Pipelining
Advantages of Pipelining include

 increased instruction throughput

 simultaneous execution of a higher number of instructions with more pipeline stages
 the potential for designing faster Arithmetic Logic Units (ALUs)
 the ability of pipelined CPUs to operate at higher clock frequencies compared to RAM,
ultimately enhancing overall CPU performance.

However, there are disadvantages to pipelining, including the complexity of

designing pipelined processors, increased instruction latency, difficulty in predicting the
throughput of a pipelined processor, and the exacerbation of hazard problems for branch
instructions as the pipeline lengthens.

2.5 Historical Context

Pipelining roots trace back to the 1980s, a pivotal era in computer architecture marked by the rise
of Reduced Instruction Set Computing (RISC) architectures. Traditional processors faced
challenges in improving performance due to the sequential nature of instruction execution.
Recognizing this limitation, early computer architects sought inspiration from assembly line
processes, where tasks are divided into sequential stages to optimize efficiency.

The concept of pipelining was born from this analogy. Architects proposed dividing the
instruction execution process into distinct stages, allowing different stages to operate
concurrently, much like different stations on an assembly line. This breakthrough in CPU design
enabled processors to execute multiple instructions simultaneously, thus significantly improving
performance.

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 The advent of RISC architectures, characterized by simplified instruction sets and
optimized instruction pipelines, further propelled the adoption of pipelining. By breaking down
instruction execution into sequential stages such as instruction fetch, decode, execute, and write
back, processors could achieve higher throughput and efficiency.

In essence, pipelining revolutionized CPU design by introducing parallelism into

instruction execution. It marked a paradigm shift in processor architecture, laying the foundation
for subsequent advancements in performance optimization techniques. Through its historical
evolution, pipelining has become a cornerstone of modern computing systems, driving continual
innovation in CPU design and paving the way for increasingly powerful and efficient processors.

2.6 Summary
Pipelining, drawing inspiration from assembly line processes, is a fundamental concept in
computer architecture aimed at enhancing processor performance by concurrently executing
multiple instructions.

This technique, rooted in early RISC architectures, revolutionized CPU design by

introducing the concept of overlapping instruction actions. By breaking down instruction
execution into sequential stages and allowing instructions to progress through these stages
simultaneously, pipelining significantly boosts processor efficiency and throughput.

Initially developed to mitigate the performance limitations of complex instruction

set computing (CISC) architectures, pipelining has become an integral aspect of modern CPU
design across various computing platforms. Through the parallel execution of instruction tasks,
pipelining optimizes resource utilization and reduces instruction latency, leading to substantial
improvements in computational speed and overall system performance.

Furthermore, pipelining serves as a cornerstone for other advanced processor

optimization techniques, such as superscalar and out-of-order execution. These techniques build

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upon the principles of pipelining to further exploit instruction-level parallelism and enhance
processor efficiency.

In summary, pipelining stands as a testament to the continuous evolution of

computer architecture, embodying the pursuit of performance optimization and efficiency
enhancement in processor design. Its pervasive influence underscores its significance as a
cornerstone of modern computing systems.

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 Chapter 3

Pipelined Data Path and Control

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3.1 Introduction
In computer architecture, pipelining is a technique that breaks down instruction execution into
stages to enable parallel processing of multiple instructions and enhance processor speed.
Although it enhances efficiency by simplifying the execution process, it also presents challenges
such as hazards that must be managed for smooth operation. (Architecturemaker, n.d.)

Stages of the Pipeline:

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 Figure 3.1: Flow chart of Pipelining stages

3.2 Components of Pipelined Data path

 The Arithmetic Logic Unit (ALU) serves as the mathematical and logical center of a
computer. It carries out operations such as addition, subtraction, and more. Think of it
like the brain for computing math problems.

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  Registers can be likened to compact and lightning-fast memo pads found within the
computer system. They serve a temporary function by holding tiny amounts of data that
are actively being processed by the machine at present.

 Buses inside a computer can be likened to highways for data, transporting information
between various parts of the system. Diverse buses exist for conveying specific types of
signals such as addresses, data, and control.

 Multiplexers are like train switches for data, diverting a computer's attention to different
inputs to process them. Just as railway tracks rely on trains switching paths seamlessly,
using multiplexers allows computers to quickly change focus between various sources of
information.

 The Control Unit acts as a conductor for the computer, ensuring that all components
work harmoniously and at appropriate instances. Though not directly involved in data
processing, its role is indispensable.

 Internal connections refer to the wires and pathways present inside a computer,
responsible for linking various components seamlessly, enabling effortless data transfer.
(point, n.d.)

3.3 Architectures with Superscalar and VLIW

designs
Here's a comprehension of the Architectures with Superscalar and VLIW designs

 The Superscalar Architecture: employs a single processor that utilizes instruction-

level parallelism, enabling it to execute numerous instructions at once during a clock

28
 cycle by dispatching them to various execution units within the CPU. This contrasts with
scalar processors which can only process one instruction per clock cycle, resulting in
lower throughput when compared.

 The VLIW Architecture: simplifies CPU design through a unique approach to

parallelism. Rather than relying on hardware for scheduling instructions, this architecture
utilizes the compiler to identify and bundle multiple operations into one lengthy
instruction word that can be executed simultaneously. By delegating the responsibility of
organizing instructions with the potential for synchronization to the compiler, complexity
is reduced in designing CPUs. (Encyclopedia, 2024)

3.3.1 Trade-offs and Challenges

The design of pipelines in computer architecture poses multiple hurdles, such as intricacy and
energy consumption.

 Complexity: As pipelines are augmented to improve performance, their depth and

complexity increase, posing greater challenges for managing dependencies and ensuring
accurate instruction execution.

 Power Consumption: Modern computing systems, especially mobile devices and data
centers are faced with a crucial concern of higher power consumption attributed to deeper
pipelines and faster clock speeds.

To optimize pipeline design, different factors such as performance, power consumption, and cost
must be balanced. One example is to increase the pipeline depth for improved performance
however this could also result in higher power consumption and increased complexity.
(Linkedin, n.d.)

29
3.4 Data Flow in Pipelined Systems
Stages in Pipelined Data Path are

 Prefetch: Retrieve the position of the upcoming directive in advance.

 Fetch: Obtain the following directive.

 Interpret: Determine the appropriate method of accessing memory required for

processing the instruction's data.

 Access: Locate the address of the data operands through access.

 Observe: Retrieve the factual data operands.

 Execute: Carry out the task of placing the information onto the bus for additional
analysis.

The implementation of pipelining in processors divides instruction execution into smaller stages,
which enables concurrent processing of various instructions at different phases.

This enhances parallelism and resource utilization thereby considerably

enhancing performance compared to non-pipelined architectures. Despite the complexities
introduced such as hazard handling and pipeline stalls, overall pipelining increases the
processor's efficiency by rapidly executing instructions.

30
Pathway for data:

Figure 3.4: A Pipeline Data path

The data path is composed of different components, such as ALUs, multipliers, registers, and
buses that execute data processing functions. It joins with the control unit to construct the CPU.
31
Multiplexers can merge several data paths to form a more comprehensive one. (WIKIPEDIA,
n.d.)

3.5 Control Signal (OpenGenus, n.d.)

Effective monitoring of instruction flow and coordination across various stages is vital for
efficient CPU pipelining. The control signals from the processor's control unit guide each
pipeline stage on what actions to execute and when to ensure accurate processing of instructions.
These signals facilitate the simultaneous execution of multiple instructions in distinct phases,
boosting overall efficiency levels.

Control signals have multiple functions, one of them being the supervision and
resolution of pipeline hazards that could interrupt sequential execution. Moreover, they are
responsible for guaranteeing data integrity during various instructions and operations like
memory access or branch instructions as well as arithmetic calculations.

Dangers and situations causing cessation of progress (Witscad, n.d.)

The occurrence of pipeline hazards in a CPU results from the incapacity of executing the next
instruction within its scheduled clock cycle, consequently producing ineffective performance.
The types associated with such risks are classified into three categories:

 Structural hazards occur when multiple instructions in the pipeline need to access a
shared resource, such as memory or ALU, at the same time, overwhelming hardware
capabilities and creating a bottleneck.
 Data hazards arise when instructions in the pipeline rely on the outcomes of preceding
instructions. This can happen if a particular instruction requires data that has not been
recorded by an earlier instruction, resulting in such a hazardous situation.

32
  Control hazards, which are also referred to as branch hazards, arise when the pipeline
relies on branch prediction to make decisions. If this forecast is incorrect, any instructions
brought into the pipeline based on it must be disregarded resulting in delays.

Multiple methods are employed to manage these dangers

 Forwarding: refers to sending outcomes directly to the necessary units, thus eliminating
the requirement of first recording and subsequently accessing data.

 Pipelining: is the process of dividing instruction execution into smaller stages, which
enables different instructions to be executed concurrently in distinct phases.

 Stalling: refers to the insertion of 'bubbles' or no-operation instructions (NOPs) within

the pipeline to temporarily halt certain instruction executions and resolve hazards. It is
employed mainly when forwarding and other approaches prove ineffective in addressing
such issues.

Managing interdependencies and resource requirements of instructions in the pipeline is

facilitated by these mechanisms, which aid in ensuring the accurate execution of instructions.

3.6 Summary
In conclusion, pipelining is a critical and sophisticated technique in computer architecture that
significantly enhances processor performance by allowing parallel processing of instructions.

While it offers substantial benefits in terms of efficiency and speed, it also introduces
complexities, such as various types of hazards and increased power consumption. The successful
implementation of pipelining involves carefully balancing these trade-offs and effectively
managing hazards through techniques like forwarding, stalling, and strategic pipeline design.

33
 Additionally, the evolution of processor architectures like Superscalar and VLIW
reflects ongoing efforts to exploit instruction-level parallelism more effectively. Despite its
challenges, pipelining remains a cornerstone in modern processor design, contributing to the
continual advancement of computing power and efficiency.

34
 Chapter 4

Pipeline Hazards

4.1 Introduction
Pipeline hazards are critical impediments in pipelined CPU architectures, significantly impacting
processor efficiency and performance. These hazards occur when the execution of an instruction
in the pipeline cannot proceed in the next cycle, leading to delays and performance bottlenecks
(Shanthi, n.d.).

35
4.2 Types of Pipeline Hazards

(Shrutika, 2023)

4.3 Structural Hazards

These arise when the hardware resources are insufficient for the demands of simultaneous
instructions. For example, when two instructions simultaneously require the same ALU or
memory resource, a structural hazard occurs, leading to delays and reduced throughput (Shanthi,
n.d.).

36
4.4 Data Hazards
Data hazards occur due to dependencies between instructions, such as when an instruction
requires data that is yet to be produced by a previous instruction. This category includes hazards
like Read After Write (RAW), Write After Write (WAW), and Write After Read (WAR), each
with its unique implications on the pipeline flow (StudySmarter, n.d.).

4.5 Control Hazards

Also known as branch hazards, these arise from the branching of instructions, where the
direction of the branch is not immediately known. This uncertainty can cause significant delays,
as the pipeline might need to be flushed and reloaded once the branch direction is determined
(StudySmarter, n.d.).

4.6 Mitigation Strategies

Pipeline Stalling: Implemented by inserting No Operation Instructions (NOPs) into the pipeline
to allow time for resolving the hazard. While effective, this method can lead to underutilization
of CPU resources (Shanthi, n.d.).

Data Forwarding: Involves forwarding the data from a later stage in the pipeline to
an earlier stage where it’s needed, thus resolving data dependencies more efficiently (Shanthi,
n.d.).

Branch Prediction: Predicts the direction of branch instructions to mitigate control hazards.
While effective, incorrect predictions can lead to pipeline flushing, which can be costly in terms
of performance (StudySmarter, n.d.).
37
 Hardware Enhancements: Adding more resources, like extra ALUs, can help in
mitigating structural hazards, though this increases the cost and complexity of the CPU design
(Shanthi, n.d.).

Real-World Implications and Examples

Modern CPUs implement these strategies in various combinations to optimize performance. For
example, Intel’s Core processors utilize advanced branch prediction algorithms and data
forwarding techniques to minimize pipeline stalls and improve overall throughput.

4.7 Conclusion
Understanding and effectively addressing pipeline hazards is crucial in CPU design. While there
are multiple strategies to mitigate these hazards, each comes with its own set of trade-offs that
must be carefully considered in the context of overall system design and performance goals.

Summary
 In this report, we have discussed the concept of pipelining in computer architecture,
including its definition, purpose, structure, pipeline stages, control signals, and different

38
 types of pipeline hazards. We also discussed techniques for mitigating pipeline hazards,
such as forwarding, stalling, and branch prediction.

 Pipelining has played a crucial role in the evolution of computer architecture, enabling
faster and more efficient processing of instructions. Pipelining has allowed processors to
execute multiple instructions simultaneously, leading to significant improvements in
performance. Pipelining has also paved the way for other innovations in computer
architecture, such as superscalar and out-of-order execution.

 Future research in the field of pipelining could focus on improving the efficiency of
existing techniques for mitigating pipeline hazards, exploring new techniques for
reducing power consumption, and investigating the impact of pipelining on security and
reliability in computing systems. Additionally, research could focus on the integration of
pipelining with emerging technologies such as quantum computing and neuromorphic
computing.

39
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