Laporan Hasil Praktikum

Elektronika Digital

Dosen Pengampu: Yuri Pamungkas, S.Tr.T, M.T.

Disusun oleh:
Muhammad Aisar 5049231116

Program Studi Teknologi Kedokteran

Fakultas Kedokteran dan Kesehatan
Institut Teknologi Sepuluh Nopember
2024
 BAB III
GERBANG LOGIKA

1. AND

A B X Gambar

0 0 0

0 1 0

1 0 0

1 1 1

2. OR
A B X Gambar

0 0 0

0 1 1

1 0 1

1 1 1

3. NAND
A B X Gambar

0 0 1

0 1 1

1 0 1

1 1 1

4. NOR
A B X Gambar

0 0 1

0 1 0

1 0 0

1 1 0

5. EX-OR
A B X Gambar

0 0 0

0 1 1

1 0 1

1 1 0

6. EX-NOR
A B X Gambar

0 0 1

0 1 0

1 0 0

1 1 1

7. NOT
A X Gambar

0 1

1 0

BAB IV
RANGKAIAN LOGIKA KOMBINASI
 Percobaan 1

A B X Gambar

0 0 1

0 1 0

1 0 0

1 1 0

Percobaan 2

A B X Gambar
 0 0 1

0 1 1

1 0 1

1 1 0

Percobaan 3

A B X Gambar
0 0 1

0 1 1

1 0 1

1 1 0

Percobaan 4

A B X Gambar
 0 0 1

0 1 0

1 0 0

1 1 0

Percobaan 5

A B X Gambar
0 0 1

0 1 0

1 0 0

1 1 0

Percobaan 6

A B X
0 0 0

0 1 0

1 0 1

1 1 1

Percobaan 7

A B C X Gambar
0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1
1 0 1 0

1 1 0 1

1 1 1 1
 BAB V
RANGKAIAN FLIP FLOP

1. Nilai Kebenaran Flip-Flop RS dengan Gerbang NAND

R S 𝑅̅ 𝑆̅ Q 𝑄̅ Gambar

0 0 1 1 NT NT

0 1 1 0 0 1

1 0 0 1 1 0

1 1 0 0 - -

2. Nilai Kebenaran Flip-Flop RS dengan Gerbang NOR

R S 𝑅̅ 𝑆̅ Q 𝑄̅ Gambar

0 0 1 1 0 0

0 1 1 0 1 0

1 0 0 1 0 1

1 1 0 0 NT NT

3. Nilai Kebenaran Flip Flop D non Clock

D Q' Q Gambar

0 1 0

1 0 1

4. Nilai Kebenaran Flip-Flop D dengan Clock

 Input Output
Gambar
Clock D Q 𝑄̅

0 0 0 1

1 0 0 1

0 1 1 0

1 1 1 0

0 0 0 1
1 0 0 1

0 1 1 0

1 1 1 0

5. Nilai Kebenaran Flip-Flop D menggunakan IC 7474 dengan Fitur Set dan Reset

Input Output
Set Reset Gambar
Clock D Q 𝑄̅
0 0 0 0 0 1

0 0 1 0 1 1

1 0 0 1 0 1
1 0 1 1 0 1

0 1 0 0 1 1

0 1 1 0 0 1
1 1 0 1 0 1

1 1 1 1 0 1

6. Nilai Kebenaran Flip-Flop JK dengan Gerbang NOR

 Input Output
Gambar
Clock J K Q 𝑄̅

0 0 0 - -

1 0 0 - -

0 0 1 - -

1 0 1 - -

0 1 0 - -

1 1 0 - -

0 1 1 - -

1 1 1 - -

7. Nilai Kebenaran Flip-Flop JK menggunakan IC 7473

Input Output
Gambar
Clock J K Q 𝑄̅

0 0 1 0 1

0 0 0 0 1
0 1 0 0 1

0 1 1 0 1

0 0 1 0 1
 0 0 1 0 1

1 0 0 0 1

1 1 0 0 1

8. Nilai Kebenaran Master/Slave JK dengan IC 7473

Clock J K 𝑄1 𝑄̅ 1 𝑄2 𝑄̅ 2 Gambar
0 0 0 0 1 0 1

1 0 0 0 1 0 1

0 0 1 0 1 0 1

1 0 1 0 1 0 1
0 1 0 0 1 0 1

1 1 0 0 1 0 1

0 1 1 0 1 0 1

1 1 1 0 1 0 1
 BAB VI
RANGKAIAN REGISTER DAN COUNTER

Tabel 6. 10 Hasil Percobaan Rangkaian Pencacah Biner

Output
Input Clock
D C B A

1 0 0 0 0
2 0 0 0 1
3 0 0 0 1
4 0 0 1 0
5 0 0 1 0
6 0 1 0 1
7 0 1 0 1
8 0 1 1 0
9 0 1 1 0
 10 1 0 0 1
11 1 0 0 1
12 1 0 1 0
13 1 0 1 0
14 1 1 0 1
15 1 1 0 1
16 1 1 1 0
17 1 1 1 0
18 0 0 0 1
19 0 0 0 1
20 0 0 1 0

Tabel 6. 11 Hasil Percobaan Rangkaian Pencacah Desimal

Input Clock Output 7 Segment
1 1
2 1
3 2
4 2
5 3
6 3
7 4
8 4
9 5
10 5
11 6
12 6
13 7
14 7
15 8
Tabel 6. 12 Tabel Percobaan Rangkaian Shift Register SIPO 1
Serial In pada Clock ke- Output
No
1 2 3 4 A B C D

1 1 1 1 1 0 1 0 0
2 1 1 1 0 0 1 0 0
3 1 1 0 1 0 0 0 0
4 1 1 0 0 0 0 0 0
5 1 0 1 1 0 1 0 0
6 1 0 1 0 0 1 0 0
7 1 0 0 1 0 0 0 0
8 1 0 0 0 0 0 0 0

Tabel 6. 13 Tabel Percobaan Rangkaian Shift Register SIPO 2

Serial In pada Clock ke- Output pada Clock ke
No
1 2 3 4 5 6 7 1 2 3 4 5 6 7

1 1 1 1 1 0 0 0 0 0 0 1 1 1 1
2 1 1 1 0 0 0 0 0 0 0 0 1 1 1
3 1 1 0 1 0 0 0 0 0 0 1 0 1 1
4 1 1 0 0 0 0 0 0 0 0 0 0 1 1
5 1 0 1 1 0 0 0 0 0 0 1 1 0 1
6 1 0 1 0 0 0 0 0 0 0 0 1 0 1
 7 1 0 0 1 0 0 0 0 0 0 1 0 0 1
8 1 0 0 0 0 0 0 0 0 0 0 0 0 1

Tabel 6. 14 Hasil Percobaan Rangkaian 8-bit Serial to Parallel Converter

Clock
ke- Serial In Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
1 1 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0
4 1 0 0 0 0 0 0 0 0
5 1 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 0 0 0
7 1 0 0 0 0 0 0 0 0
8 1 0 0 0 0 0 0 0 0

BAB VII
RANGKAIAN ADDER DAN SUBTRACTOR

Tabel 7. 1 Hasil Percobaan Rangkaian Half Adder

 Input Output
A B Carry Sum
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Tabel 7. 2 Hasil Percobaan Rangkaian Full Adder

Input Output
A B Carry In Carry Out Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 1
1 0 0 0 0
1 0 1 1 0
1 1 0 1 1
1 1 1 1 1
Tabel 7. 3 Hasil Percobaan Rangkaian Half Subtractor
Input Output
A B Borrow Sum
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

Tabel 7. 4 Hasil Percobaan Rangkaian Full Subtractor

Input Output
A B Borrow In Borrow Out Sum
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

BAB VIII
RANGKAIAN ENCODER DAN DECODER
Tabel 8. 3 Hasil Percobaan Rangkaian Encoder
Input Output
A0 A1 A2 A3 A4 A5 A6 A7 A8 A B C D
1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 0 1 1 1
x 0 1 1 1 1 1 1 1 1 0 1 1
x x 0 1 1 1 1 1 1 0 0 1 1
x x x 0 1 1 1 1 1 1 1 0 1
x x x x 0 1 1 1 1 0 1 0 1
x x x x x 0 1 1 1 1 0 0 1
x x x x x x 0 1 1 0 0 0 1
x x x x x x x 0 1 1 1 1 0
x x x x x x x x 0 0 1 1 0
 Tabel 8. 4 Hasil Percobaan Rangkaian Decoder
Logic Switch Data Output
S1 S2 S3 S4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
0 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

BAB IX
RANGKAIAN RANGKAIAN ADC DAN DAC

Tabel Rangkaian DAC

 Nilai Logic Monitor
Desim Vout Step Size Gambar
al D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0 0 0,00 0

1 0 0 0 0 0 0 0 1 0,01 100

2 0 0 0 0 0 0 1 0 0,03 66,67
3 0 0 0 0 0 0 1 0 0,03 100

4 0 0 0 0 0 1 0 0 0,07 57,14

5 0 0 0 0 0 1 0 1 0,09 55,56
6 0 0 0 0 1 0 0 0 0,16 37,5

7 0 0 0 1 0 0 0 0 0,31 22,58

8 0 0 1 0 0 0 0 0 0,62 12,91
9 0 0 1 1 0 0 0 0 0,94 9,57

10 0 1 0 0 0 0 0 0 1,25 8

11 1 0 0 0 0 0 0 0 2,5 4,4
12 1 0 0 1 0 0 0 0 2,81 4,27

13 1 0 1 0 0 0 0 0 3,12 4,167

14 1 0 1 1 0 0 0 0 3,44 4,07
15 1 1 1 1 1 1 1 1 4,97 3,018