Name: GERAND T.

SALAZAR Rating: ________________

Schedule: S/7:30am -10:30am Instructor: ENGR. EDWIN PURISIMA

Experiment No. 2
UP-DOWN COUNTERS

I. OBJECTIVES:

1. To demonstrate the proper connections for a binary up counter.

2. To demonstrate the proper connections for a binary down
counter.
3. To connect and operate an MSI up-down counter.

II. MATERIALS:

3 - 7476 JK master/slave flip-flops

4 - 7411 2-input AND gates
2 - 7432 2-input OR gates
1 - 74193 Binary up-down counter
LEDs power
supply
pulse generator or debounced switch

III. PROCEDURE:

1. Construct the up counter shown in Figure 2-1a and apply the

clock; record the results and observe.

Clock (1 A B C
cycle)
0 0 0 0
1 1 0 0
2 0 1 0
3 1 1 0
4 0 0 1
5 1 0 1
6 0 1 1
7 1 1 1
2. Construct the down counter shown in Figure 2-1b. Apply 8
clock pulses; record the results and observe.

Clock (1 A B C
cycle)
0 1 1 1
1 0 1 1
2 1 0 1
3 0 0 1
4 1 1 0
5 0 1 0
6 1 0 0
7 0 0 0

3. Construct the up-down counter shown in Figure 2-2.

 Ground the count-down line, and apply + Vcc to the count-
up line. Apply 8 clock pulses, and carefully record the
outputs with respect to the clock.
Clock (1 A B C
cycle)
0 0 0 0
1 1 0 0
2 0 1 0
3 1 1 0
4 0 0 1
5 1 0 1
6 0 1 1
7 1 1 1
8 0 0 0

 Ground the count-up line, and apply + Vcc to the count-up

line. Apply 8 clock pulses, and carefully record the outputs.
Clock (1 A B C
cycle)
0 1 1 1
1 0 1 1
2 1 0 1
3 0 0 1
4 1 1 0
5 0 1 0
6 1 0 0
7 0 0 0
 The J and K inputs to the flip-flops in Figure 2-1a & 1b and Figure
2-2 have no connections. The flip-flops are being used as simple
toggles; should there be any connection to the J and K inputs?

Yes, in order to attain these outputs, there should be a

connection in J and K inputs because it needs high states or 1 in order
to bypass when a clock pulse signal is received to the flip-flops and to
produce a complementing output.

4. Examine the data sheet for the 74193 up-down counter to

determine proper pin locations. Record the maximum supply
current required for Vcc = + 5V dc. Connect the following preset
data inputs (A,B,C,D) to 1. CO = BO = 1, LOAD = 1 and CLR = 0.

Connect the DOWN pin to +Vcc and apply clock to UP pin and apply
8 clock pulses. Record the results.

Clock (1 A B C D
cycle)
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1
 Connect the UP pin to +Vcc and apply clock to DOWN and apply 8
clock pulses. Record the results.

Clock (1 A B C D
cycle)
0 1 1 1 1
1 0 1 1 1
2 1 0 1 1
3 0 0 1 1
4 1 1 0 1
5 0 1 0 1
6 1 0 0 1
7 0 0 0 1
8 1 1 1 0
9 0 1 1 0
10 1 0 1 0
11 0 0 1 0
12 1 1 0 0
13 0 1 0 0
14 1 0 0 0
15 0 0 0 0

5. Apply the clock to both DOWN and UP pin simultaneously, and note
the result.

- The operation of 74913 IC become a down counter if we apply the

clock to both down and up pin. The count is decreasing.

6. Explain how the Figure 2-3 will guarantee that UP = DOWN so that
the counter will always be either the count-up or count-down
mode.
The figure 2-3 will guarantee that UP=DOWN so that the counter
will always be either the count-up or count-down mode by connecting
the SR flip-flop to the figure 2-2. It will configure the circuit to count-
up or count-down mode. By connecting the count-up terminal to the Q
of SR and connecting the count-down to the Q’ of SR flip-flop
IV. OBSERVATION:
As I have observed, goal of this experiment is to demonstrate how the
up counter and down counter works using flip-flops, specifically JK flip-flops.
The cascading of JK flip-flops is seen in the first circuit. When the clock pulse
is activated, the up counter starts at 111 and finishes at 000, while the down
counter is the opposite. The counter circuits are operated with an external
clock to toggle in order to generate incrementing counts (000-111) to the first
JK flipflop, according to the circuits. Because the Q in the first flip-flop is
connected to the CLK of the second flip-flop, the first flip-flop will act as a clock
to the second flip-flop, and the second flip-flop will work as a clock to the third
flip-flop to change the state of the outputs. In other words, outputs A, B, and
C will generate a count that will increase over time. The Q' of the first flip-flop
is connected to the CLK of the second flip-flop in the second circuit, and the Q'
of the second flip-flop is connected to the CLK of the third flip-flop in the third
circuit. The circuit will generate a decrementing count in this arrangement. An
up-down counter is represented by circuit 2-2. When the clock is triggered, it
will produce an increment counting from 000 to 111 if the up-counter line is
connected directly to the VCC and the down-counter line is grounded. When
the clock is triggered, the down-counter line is connected directly to the VCC
and the up-counter line is grounded, resulting in a decrement counting from
111 to 000. Circuit 2-3 serves as a switch for circuit 2-2, with an SR flip-flop
used to monitor the switch's logic and determine whether the circuit is in
counter-up or counter-down mode. To configure the circuit, toggling the
switches for SR and the clock has a high input, the 2-3 switch must have an
output of 10 for counter-up and 01 for counter-down. The counter-up line is
connected to the Q line of the switch, while the counter-down line is connected
to the Q' line of the switch. By setting the clock to 2-2, you can choose between
increment and decrement counting. If both SR are 00, the SR flip-flop will only
trigger an increment counting since set is higher than reset in the priority
order. The 74193 is used to show how to count up and down. The pins load
and down are connected to the VCC, while the up pin is connected to the clock
in the Q terminal to provide increment counting in the up-counter setup. To
create a decrement counter, the pins load and up are linked to the VCC, while
the down pin is connected to the clock in the Q terminal. If the clock's up and
down pins are both connected, the clock will only count in increments.
V. CONCLUSION:
A counter is a circuit that operates in a consecutive manner. The term
"counter" refers to a digital circuit that counts pulses. The most common use
of flip-flops is on the counter. A clock signal is applied to a collection of flipflops.
The circuits that were used in this experiment are examples of asynchronous
counter circuits. It used flip-flops to explain how the up, down, and up-counter
functions. To function, the counter circuits must be coupled in a series of JK
flip-flops that are timed by an external clock in order to determine whether the
output provides incrementing or decrementing counts. The output changes
based on the clock's toggling or triggering, with the output changing only when
the clock receives a signal pulse. Furthermore, asynchronous counter circuits
have a ripple effect in which the remaining flipflops receive their signal from
the previous flip-flops, resulting in misleading output counts between some
steps of the count sequence
VI. DIAGRAM: