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WIDE BANDGAP
SEMICONDUCTOR ELECTRONICS
AND DEVICES
SELECTED TOPICS IN ELECTRONICS AND SYSTEMS
Published*
WIDE BANDGAP
SEMICONDUCTOR ELECTRONICS
AND DEVICES
Editors
Uttam Singisetti
University of Buffalo, USA
Towhidur Razzak
The Ohio State University, USA
Yuewei Zhang
University of California Santa Barbara, USA
Published by
World Scientific Publishing Co. Pte. Ltd.
5 Toh Tuck Link, Singapore 596224
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ISBN 978-981-121-647-3
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Printed in Singapore
Preface
Editors
Uttam Singisetti (University at Buffalo)
Towhidur Razzak (The Ohio State University, Columbus)
Yuewei Zhang (University of California, Santa Barbara)
November, 2019
Contents
Preface
Hareesh Chandrasekar
Department of Electrical and Computer Engineering, The Ohio State University, 2015 Neil
Avenue, 205 Dreese Labs, Columbus OH 43210, USA
[email protected]
1. Introduction
Gallium Nitride high electron mobility transistors (HEMTs) are
currently the mainstream RF technology of choice for discrete and
MMIC-based high-power, high-frequency power amplifiers in a range
of applications ranging from radars, CATVs, and satellite
communications, to wireless broadband in the 4G and the up-and-
coming 5G spectrums [1–3]. Despite the stellar performance of GaN
devices on silicon carbide (SiC) substrates [1], the inherently high
cost of this technology due to the limited areas and high starting
substrate costs, have spurred the development of GaN devices on
alternate, more inexpensive substrates in order to achieve cost-
competitiveness with existing Si LDMOS technology for sub-3.6 GHz
power amplifiers and for future applications at higher frequency
bands. Silicon (111) has been widely used as a substrate for GaN
growth despite the multifarious challenges involved in obtaining
good quality III-nitride films such as the very large lattice (17%) and
thermal mismatch which in turn leads to higher dislocation densities
and film cracking [4–6]. These challenges have been successfully
addressed by a variety of stress management schemes and present
day epitaxy on Si is of comparable quality and repeatability to that
on SiC substrates albeit with a higher complexity of the epitaxial
process [6–9]. Nevertheless, the large size of Si wafers (up to 12"
diameter currently), their ultra-low cost, and possibility of co-
processing in existing CMOS foundries promises to make GaN-on-Si
devices the cost-effective gallium nitride solution for power
amplification and power electronic applications. Indeed the bulk of
R&D efforts in GaN power electronics has focused on material grown
on Si substrates in view of the above advantages [10, 11].
Although the development of GaN-on-Si HEMTs for RF
applications far predates that for power electronics [12–15], this
technology is becoming more mainstream thanks to its adoption
currently in wireless broadband applications, and device & circuit
level metrics of reliable GaN-on-Si devices comparable to GaN-on-SiC
have been reported in literature [12, 16–21]. The continued
development of GaN-on-Si devices goes hand in hand with advances
in hetero-epitaxy in terms of defect reduction and stress
management schemes, maturity of CMOS-compatible process flows
for device fabrication, and informed device design and modeling
based on accurate device characterization data – both electrical and
thermal – as well as reliability implications. Such an interplay
between device design-growth-processing-characterization is key to
realizing the full potential of this technology.
In this context, it is important to thoroughly understand the role
of the Si substrate itself on the intrinsic performance of GaN-on-Si
RF electronics from a device standpoint. Here we review recent work
on three issues stemming from the use of semiconducting Si as the
substrate of choice for GaN RF devices. Firstly, the formation of a
parasitic/parallel conduction channel at the Si-epitaxy interface is
discussed in terms of the physical mechanisms involved and its
effect on RF losses, with solutions to address the same. Secondly,
we discuss the increased susceptibility of GaN-on-HR-Si HEMTs to
dispersion/trapping effects in the GaN buffer due to the presence of
such a parallel channel and small amounts of leakage through the
substrate backplane. We will then briefly present and evaluate
approaches to minimize such buffer-induced current collapse for
GaN-on-Si devices. Lastly, thermal generation of carriers in the
semiconducting Si substrates, either due to heat flow from the active
device or elevated ambient operating temperatures is considered.
This causes a drop in the resistivity of the highly-resistive Si
substrates (HR-Si) used for GaN devices, leading to RF substrate
losses which are quantified, and we conclude with presenting
approaches to minimize this effect.
Fig. 1. A summary of potential factors affecting formation of the parasitic channel at or near
the epitaxy – Si substrate interface.
Figure 2 shows the 1-D equilibrium band diagram for the case of a
Ga-profile with a peak concentration of 1018 cm–3 at the interface
and a roll-off of 3 μm into highly resistive n-type Si (10 kΩ.cm),
without accounting for any interfacial polarization charge.
Fig. 2. (a) Ga-diffusion profile in the Si substrate with peak concentration of 1018 cm–3 at
the interface and roll-off of 3 μm after Hanson et al. [23] (b) Band diagram of near-
interface HR-Si region at the AlN/Si heterointerface showing the accumulation of holes close
to the interface, generated using the Silvaco ATLAS device simulator.
It is important to note that the III-nitride films grown on Si are
not only highly defective but also have large film stresses (in the GPa
range) even at the growth temperatures [6]. The initial layers such
as the AlN nucleation layer and some part of the subsequent AlGaN
transition layers are typically grown under tensile strain and have
dislocation densities ranging from 1013 cm–2 in the AlN layer to 1011
cm–2 in the AlGaN layers. The GaN buffers are typically engineered
to have a compressive strain in order to obtain crack-free films on
cool-down and typically have dislocation densities of 109-1010 cm–2
at the active device regions [31, 32]. These large dislocation
densities could act as local diffusion pathways for Ga- and Al-species
towards the substrate with the large film stresses further aiding such
diffusion. It is also noteworthy that only Al and Ga in substitutional
Si sites act as dopants. While such substitutional doping would be
aided by the high growth temperatures typically used, the total
density of these species as reported by SIMS measurement would
also include interstitial Al/Ga. Furthermore, the parasitic channel is
expected to be composed of holes (p-type) in this case.
Another commonly proposed explanation for the parasitic channel
is the formation of an inversion layer of electrons at the Si/AlN
interface [25–27]. AlN is a polar material with a high spontaneous
(Psp) and piezoelectric polarization (Ppz) while Si is a non-polar
material. This gives rise to a “polarization step” at this polar/non-
polar hetero-interface. Since AlN on Si is almost always Al-polar, a
positive polarization charge would be manifest at this interface.
Given the large spontaneous polarization of the AlN (0.081μC/cm2),
this should correspond to a sheet charge of ~5x1013 cm–2 at the
interface. Furthermore, the AlN films are typically strained in tension
(>1 GPa) and hence the piezoelectric polarization should add to the
spontaneous polarization and increase the interfacial sheet charge
and expected electron density at this interface. Figure 3 shows the
equilibrium band diagram for this scenario assuming a relaxed 100
nm AlN layer (Ppz = 0) on a highly resistive p-type Si (10 kΩ.cm).
The parasitic channel in this case is composed of an inversion layer
of electrons (n-type), the origin of which would most likely be
thermal generation in the silicon substrate or surface donors in case
of only AlN layers on Si [27].
Fig. 3. (a) Band diagram at the AlN/Si interface assuming spontaneous polarization only in
relaxed AlN films on Si showing formation of an inversion layer of electrons at the interface.
(b) Plot of electron concentration expected due to the polarization step at an ideal AlN/Si
interface, generated using the Silvaco ATLAS device simulator.
Fig. 4. (a) Conductance spectra of 50 nm MOCVD AlN films on p-Si substrates showing the
evolution of slow and fast traps. (b) Interface trap densities (Dit in cm–2) and trap time
constants (τit in s) with gate voltage swept from depletion to weak inversion. (Reprinted
with permission from Thickness-dependent Parasitic Channel Formation at AlN/Si Interface,
by H. Chandrasekar et al., in Scientific Reports, Volume 7, Article number: 15749, 2017).
Fig. 5. (a) GaN-on-Si HEMT stack with 1-D lumped element equivalent circuit for charge
storage during substrate ramp measurements. (b) Representative curves for normalized
2DEG conductivity for negative substrate ramps for a GaN HEMT with buffer-induced
current collapse due to charge re-distribution and for the case where substrate depletion
effects are observed. Also shown is the capacitance line for the entire epitaxy behaving as
an ideal capacitor.
Fig. 6. (a) Measured substrate ramp traces for the C:doped GaN-on-HR Si HEMT stack
shown in Fig. 5 for ramp rates of 0.4, 4 and 25 V/s with Vd of 1V and Vg of 0V. (b)
Simulated substrate ramp traces for an identical stack using Silvaco ATLAS. (c) Band
diagram at -50V (point A in (b)). The applied voltage drops entirely in the epitaxy and not
in the HR-Si at all. (d) Charge re-distribution in the C:doped region when the applied
substrate bias is removed (point B in (b)) (© IEEE 2018, Reprinted with permission from
Buffer-induced Current Collapse in GaN HEMTs on Highly Resistive Si Substrates by H.
Chandrasekar et al., in IEEE Electron Device Letters 39(10), pg. 1556-1559, 2018) [83].
where Gth is the thermal generation rate given by ni /τn and CIII-N is
the areal capacitance (F/cm2) of the total III-nitride epitaxial stack.
Substrate ramps above this rate should widen the depletion region
and hence increase the voltage dropped across the Si. However, it
has been shown that the measured 2DEG conductivity traces fall
below the ideal capacitive limit even for very high sweep rates of 25
V/s for a proto-typical Carbon-doped GaN stack on HR-Si, as seen in
Fig. 6(a) [83]. This shows that deep-depletion in silicon is not
achieved even for such high sweep rates hence pointing to the
inadequacy of thermal generation as the only carrier contributing
mechanism to the inversion channel at the interface. Interestingly,
the experimental findings could be reproduced by device simulations
once carrier injection from the bottom substrate contact was
considered (see Fig. 6(b)). Thus, small amounts of vertical current
flow through the highly-resistive Si substrate, due to its
semiconducting nature, coupled with the conductive layer at the
epitaxy-substrate interface serves to back-bias the GaN layers and
leads to current collapse. This current collapse in turn is due to
charge-redistribution within the carbon doped buffer layer with
ionized acceptors and donors at the GaN buffer/strain-relief layers
(AlGaN) interface. Since the negative stored acceptor charge is
closer to the 2DEG, this causes the 2DEG conductivity to drop
leading to collapse. This can also be seen in band diagrams of
Fig. 6(c) and (d) which shows the negative charge close to the 2DEG
due to the ionized acceptors at the top of the C:doped layers leading
to current collapse, with positive compensating donor charge at the
top of the strain relief layer. We see that this phenomenon is
identical to that for GaN-on-doped Si substrates for power electronic
applications [78]. In comparison these effects would not arise in
case of the insulating SiC substrates used for standard GaN-on-SiC
RF devices and hence GaN-on-Si RF devices are inherently more
susceptible to buffer-induced current collapse in comparison to those
on SiC.
Fig. 7. Device simulations showing the effect of a blocking substrate contact in inducing
substrate depletion for GaN-on-HR Si stack. The normalized drain current trace falls above
the ideal capacitive line as expected when compared to a regular back-bias configuration.
with
and K(k) & K(k’) are the complete elliptic integrals of the first kind
whose ratios are computed using Hilberg’s approximation as [108],
for 1≤K/(k)/K(k’)≤∞ and 1/√2≤k≤1, and
Fig. 9. Comparison of experimental and simulated line loss at 20 GHz on SiNx-on-Si CPW
structures for substrate resistivity of 10 kΩ.cm and 25 Ω.cm from 25-200°C. (© IEEE 2019,
Reprinted with permission from Quantifying Temperature-dependent Substrate Loss in GaN-
on-Si RF Technology, by H. Chandrasekar et al., in IEEE Transactions on Electron Devices
66(4), pg. 1681-1687, 2019) [106].