LIST OF EXPERIMENTS

1. Verification of Boolean Theorems using basic gates.

Design and implementation of combinational circuits using basic gates for arbitrary
2.
functions, code converters.

3. Design and implement Half/Full Adder and Subtractor.

4. Design and implement combinational circuits using MSI devices:

4 – bit binary adder / subtractor
Parity generator / checker
Magnitude Comparator
Application using multiplexers

5. Design and implement shift-registers.

6. Design and implement synchronous counters.

7. Design and implement asynchronous counters.

8. Coding combinational circuits using HDL.

9. Coding sequential circuits using HDL.

10. Design and implementation of a simple digital system (Mini Project).

 STUDY OF LOGIC GATES

THEORY:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one
or more input and only oneoutput.
OR, AND and NOT are basic gates. NAND and NOR are known as universal gates. Basic gates
form these gates.
AND GATE

The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs islow.

OR GATE

The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT GATE

The NOT gate is called an inverter. The output is high when the input is low. The output is
low when the input is high.
X- ORGATE

The output is high when any one of the inputs is high. The output is low when both the inputs
are low and both the inputs are high.
NAND GATE

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs arehigh.
NOR GATE

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
AND GATE:

SYMBOL: PINDIAGRAM:

OR GATE:
 NOT GATE :
SYMBOL: PINDIAGRAM:

X-OR GATE :
SYMBOL : PIN DIAGRAM:
2- INPUT NANDGATE

SYMBOL PINDIAGRAM

3- INPUT NANDGATE
NOR GATE
 Ex. No:
VERIFICATION OF BOOLEAN THEOREMS USING BASIC GATES
Date:

Aim:
To verify the truth table of basic Boolean algebric laws by using logic gates.
Components Required:
S.NO COMPONENTS RANGE QUANTITY

1 Digital IC trainer kit - 1

2 IC 7400 1
7402 1
7404 1
7408 1
7432 1
7486 1

3 Bread board - 1
4 Connecting wires - As required

Theory:
Demorgan’s Theorems
First Theorem:
It states that the complement of a product is equal to the sum of the complements.
(AB)′ =A′ +B′
Second Theorem:
It states that the complement of a sum is equal to the product of the complements.
(A+B)′ =A′.B′
Boolean Laws:
Boolean algebra is a mathematical system consisting of a set of two or more distinct elements, two binary
operators denoted by the symbols (+) and (.) and one unary operator denoted by the symbol either bar (-) or prime
(„). They satisfy the commutative, associative, distributive and absorption properties of the Boolean algebra.
Commutative Property:
Boolean addition is commutative, given by A+B=B+A
Boolean algebra is also commutative over multiplication, given by A.B=B.A
De-Morgan’s Theorem: 1

De-Morgan’s Theorem: 2
Associative Property:

The associative property of addition is given by A+ (B+C) =

(A+B) +C
The associative law of multiplication is given by A. (B.C) =
(A.B).C
Distributive Property:
The Boolean addition is distributive over Boolean multiplication, given by A+BC = (A+B)
(A+C)
Boolean multiplication is also distributive over Boolean addition given by A. (B+C) =
A.B+A.C
Realization of circuits for Boolean expression after simplification:
A binary variable can take the value of „0‟ or „1‟. A Boolean function is an expression formed with
binary operator OR, AND and a unary operator NOT, parenthesis function can be 0 or 1.
For example, consider the function

The prime implicants are found by using the elimination of complementary function. The circuit diagram for the
function is drawn using AND.OR and NOT gates. The output for the corresponding input of A1, A0, B1, BO is
calculated and the truth table is drawn.
Procedure:
1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.

Commutative Law:
Truth Table:
Input Output

A B A+B B+A

0 0 0 0

0 1 1 1

1 0 1 1

1 1 1 1

Associative Law:

Truth Table:

Input Output

A B C A+B (A+B)+C B+C A+(B+C)

0 0 0 0 0 0 0

0 0 1 0 1 1 1

0 1 0 1 1 1 1

0 1 1 1 1 1 1

1 0 0 1 1 0 1

1 0 1 1 1 1 1

1 1 0 1 1 1 1

1 1 1 1 1 1 1
Distributive Law:

Truth Table:

Input Output
A.B+A.
A B C B+C A.(B+C) A.B A.C C
0 0 0 0 0 0 0 0

0 0 1 1 0 0 0 0

0 1 0 1 0 0 0 0

0 1 1 1 0 0 0 0

1 0 0 0 0 0 0 0

1 0 1 1 1 0 1 1

1 1 0 1 1 1 0 1

1 1 1 1 1 1 1 1

Result:
Thus the verification of Boolean laws and theorems using digital logic gates were performed.
Ex. No: Design and implementation of combinational circuits using
Date:
basic gates for arbitrary functions, code converters.

Aim:
To design and implement 4-bit
(i) Binary to gray codeconverter
(ii) Gray to binary codeconverter
(iii) BCD to excess-3 codeconverter
(iv) Excess-3 to BCD codeconverter
APPARATUS REQUIRED:

Sl.No. Component Specification Qty.

1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35
THEORY:

The availability of large variety of codes for the same discrete elements of information
results in the use of different codes by different systems. A conversion circuit must be inserted
between the two systems if each uses different codes for same information. Thus, code converter
is a circuit that makes the two systems compatible even though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code uses four bits
to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted
code.

The input variable are designated as B3, B2, B1, B0 and the output variables are designated
as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The Boolean functions
are obtained from K-Map for each output variable.

A code converter is a circuit that makes the two systems compatible even though each uses
a different binary code. To convert from binary code to Excess-3 code, the input lines must supply
the bit combination of elements as specified by code and the output lines generate the
corresponding bit combination of code. Each one of the four maps represents one of the four
outputs of the circuit as a function of the four input variables.
 A two-level logic diagram may be obtained directly from the Boolean expressions derived
by the maps. These are various other possibilities for a logic diagram that implements this circuit.
Now the OR gate whose output is C+D has been used to implement partially each of threeoutputs.
Logic Diagram:
BINARY TO GRAY CODE CONVERTOR

K-Mapfor G3: K-Map forG2:

G3 = B3
K-Mapfor G1: K-Map forG0:

Truth Table:

| Binaryinput | Graycodeoutput |

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1
 1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

Logic Diagram:
GRAY CODE TO BINARY CONVERTOR

K-MapforB3: K-Map forB2:

B3 = G3
K-MapforB1: K-Map forB0:

Truth Table:

| GrayCode | BinaryCode |

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1
 1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1

Logic Diagram:

BCD TO EXCESS-3 CONVERTOR

 K-MapforE3: K-Map forE2:

E3 = B3 + B2 (B0 + B1)

K-MapforE1: K-Map forE0:

Truth Table:

| BCDinput | Excess – 3output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x x x x

1 0 1 1 x x x x

1 1 0 0 x x x x

1 1 0 1 x x x x

1 1 1 0 x x x x

1 1 1 1 x x x x
Logic Diagram:
EXCESS-3 TO BCD CONVERTOR

K-Mapfor A: K-Map forB:

A = X1 X2 + X3X4X1
K-M apfor C: K-Map forD:

Truth Table:

| Excess –3Input | BCDOutput |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0
 1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1

PROCEDURE:
(i) Connections were given as per circuitdiagram.
(ii) Logical inputs were given as per truthtable
(iii) Observe the logical output and verify with the truthtables.

Result:

Thus, binary to gray code converter, Gray to binary code converter, BCD to excess-3
code converter, Excess-3 to BCD code converter was implemented.
 Ex. No: DESIGN AND IMPLEMENT HALF/FULL ADDER AND
SUBTRACTOR.
Date:

AIM
To design and implement 4-bit adder / subtractor and BCD adder using IC

Apparatus Required:

Sl.No. Component Specification Qty.

1. IC IC 7483 1

2. EX-OR Gate IC 7486 1

3. NOT Gate IC 7404 1

3. IC Trainer Kit - 1

4. Patch Cords - 40

Theory:

4 Bit Binary Adder:

A binary adder is a digital circuit that produces the arithmetic sum of two
binary numbers. It can be constructed with full adders connected in cascade, with
the output carry from each full adder connected to the input carry of next full adder
in chain. The augends bits of ‘A’ and the addend bits of ‘B’ are designated by
subscript numbers from right to left, with subscript 0 denoting the least significant
bits. The carries are connected in chain through the full adder. The input carry to the
adder is C0 and it ripples through the full adder to the output carry C 4.
4 Bit Binary Adder/Subtractor:

The addition and subtraction operation can be combined into one circuit with
one common binary adder. The mode input M controls the operation. When M=0,
the circuit is adder circuit. When M=1, it becomes subtractor.

4 Bit BCD Adder:

Consider the arithmetic addition of two decimal digits in BCD, together with
an input carry from a previous stage. Since each input digit does not exceed 9, the
output sum cannot be greater than 19, the 1 in the sum being an input carry. The
output of two decimal digits must be represented in BCD and should appear in the
form listed in the columns.

ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2
decimal digits, together with the input carry, are first added in the top 4 bit adder to
produce the binary sum.

PROCEDURE:
(i) Connections were given as per circuitdiagram.
(ii) Logical inputs were given as per truthtable
(iii) Observe the logical output and verify with the truthtables.
Pin Diagram for IC 7483:

Logic Diagram:
4-Bit Binary Adder
4-Bit Binary Subtractor

5- Bit BinaryAdder/Subtractor
Truth Table:
Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
BCD ADDER

K- MAP

Y = S4 (S3 + S2)
Truth Table:

BCD SUM CARRY

S4 S3 S2 S1 C

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

Result:

Thus, the 4-bit adder / subtractor and BCD adder using IC 7483 was
designed and implement.
Ex. No: Design and implement combinational circuits using MSI devices:
Date:
Application using multiplexers

Aim:
To design and implement multiplexer and De-multiplexer using logic gates and study of
IC 74150 and IC 74154.

Apparatus Required:

Sl.No. Component Specification Qty.

1. 3 I/P AND GATE IC 7411 2

2. OR GATE IC 7432 1

3. NOT GATE IC 7404 1

2. IC TRAINER KIT - 1

3. PATCH CORDS - 32

Theory:
MULTIPLEXER:

Multiplexer means transmitting a large number of information units over a smaller number
of channels or lines. A digital multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it to a single output line. The selection of a particular input
line is controlled by a set of selection lines. Normally there are 2n input line and n selection lines
whose bit combination determine which input isselected.

DEMULTIPLEXER:

The function of Demultiplexer is in contrast to multiplexer function. It takes information

from one line and distributes it to a given number of output lines. For this reason, the demultiplexer
is also known as a data distributor. Decoder can also be used as demultiplexer.
 In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data
select lines enable only one gate at a time and the data on the data input line will pass through the
selected gate to the associated data output line.

Block Diagram for 4:1 Multiplexer:

Function Table:

S1 S0 INPUTS Y

0 0 D0 → D0 S1’ S0’

0 1 D1 → D1 S1’ S0

1 0 D2 → D2 S1 S0’

1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

Circuit Diagram For Multiplexer:

Truth Table:

S1 S0 Y = OUTPUT

0 0 D0

0 1 D1

1 0 D2

1 1 D3
Block Diagram for 1:4 Demultiplexer:

Function Table

S1 S0 INPUT

0 0 X → D0 = X S1’ S0’

0 1 X → D1 = X S1’ S0

1 0 X → D2 = X S1 S0’

1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

Logic Diagram for Demultiplexer:

Truth Table:

INPUT OUTPUT

S1 S0 I/P D0 D1 D2 D3

0 0 0 0 0 0 0
 0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1

Pin Diagram for IC 74150:

 Pin Diagram for IC 74154:

(i) C
o
n
n
e
c
t
i
o
n
s
a
r
e
g
i
v
e
n
PROCEDURE:
a
s (i) Connections were given as per circuitdiagram.
p (ii) Logical inputs were given as per truthtable
e (iii) Observe the logical output and verify with the truthtables.
r
c
i
r
c
u
i
t
d
Result:
i
a Thus, the multiplexer and De-multiplexer was designed using logic gates
g and implement.
r
a
m
.
Ex.No: DESIGN AND IMPLEMENTATION OF MAGNITUDE
COMPARATOR
Date:

AIM: To design and implement

i. 2 – Bit magnitude comparator using basicgates.
ii. 8 – Bit magnitude comparator using IC7485.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE IC 7485 2
COMPARATOR
6. IC TRAINER KIT - 1
7. PATCH CORDS - 30

THEORY:
The comparison of two numbers is an operator that determine one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares
two numbers A and B and determine their relative magnitude. The outcome of the comparator is
specified by three binary variables that indicate whether A>B, A=B (or)A<B.
A = A3 A2 A1A0 B = B3 B2 B1B0
The equality of the two numbers and B is displayed in a combinational circuit designated by
the symbol (A=B).
This indicates A greater than B, then inspect the relative magnitude of pairs of significant
digits starting from most significant position. A is 0 and that of B is 0.
We have A<B, the sequential comparison can be expanded as
 DIGITAL ELECTRONICS LAB

A>B = A3B31 + X3A2B 21 + X3X2A1B 11 + X3X2X1A0B01

A<B = A31B 3+ X A 1
3 2B +
2 X X2A
3
1
B1 +X
1 XX3 A
1
2 B1 0 0

The same circuit can be used to compare the relative magnitude of two BCD

digits.
Where, A = B is expanded as,
A = B = (A3 + B3) (A2 + B2) (A1+B1) (A0 +B0)
   
x3 x2 x1 x0

LOGIC DIAGRAM:
4 BIT MAGNITUDE COMPARATOR
 DIGITAL ELECTRONICS LAB

K MAP

TRUTH TABLE

A1 A0 B1 B0 A>B A=B A<B

0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
 DIGITAL ELECTRONICS LAB

LOGIC DIAGRAM:
2 BIT MAGNITUDE COMPARATOR

PIN DIAGRAM FOR IC 7485:

 DIGITAL ELECTRONICS LAB

LOGIC DIAGRAM:
8 BIT MAGNITUDE COMPARATOR

TRUTH TABLE:

TRUTH TABLE
A B A>B A=B A<B
0000 0000 0000 0000 0 1 0
0001 0001 0000 0000 1 0 0
0000 0000 0001 0001 0 0 1

PROCEDURE:

(i) Connections are given as per circuitdiagram.

(ii) Logical inputs are given as per circuitdiagram.

(iii) Observe the output and verify the truthtable.

RESULT:

Thus the 2-bit and 8-bit magnitude comparator circuits are implemented using logic gates and
IC 7485.
Ex. No:
DESIGN AND IMPLEMENTATION OF PARITY
Date: CHECKER/GENERATOR

AIM:
To design and implement 16 bit odd/even parity checker and generator using
IC 74180.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. NOT GATE IC 7404 1
1. PARITY IC IC 74180 2
2. IC TRAINER KIT - 1
3. PATCH CORDS - 30

THEORY:

A parity bit is used for detecting errors during transmission of binary information. A parity
bit is an extra bit included with a binary message to make the number is either even or odd. The
message including the parity bit is transmitted and then checked at the receiver ends for errors. An
error is detected if the checked parity bit doesn’t correspond to the one transmitted. The circuit that
generates the parity bit in the transmitter is called a ‘parity generator’ and the circuit that checks the
parity in the receiver is called a ‘parity checker’.
In even parity, the added parity bit will make the total number is even amount. In odd parity,
the added parity bit will make the total number is odd amount. The parity checker circuit checks for
possible errors in the transmission. If theinformation is passed in even parity, then the bits required
must have an even number of 1’s. An error occur during transmission, if the received bits have an
odd number of 1’s indicating that one bit has changed in value duringtransmission.
PIN DIAGRAM FOR IC 74180:

FUNCTION TABLE:
INPUTS OUTPUTS
Number of High Data PE PO ∑E ∑O
Inputs (I0 – I7)
EVEN 1 0 1 0
ODD 1 0 0 1
EVEN 0 1 0 1
ODD 0 1 1 0
X 1 1 0 0
X 0 0 1 1

LOGIC DIAGRAM:

16 BIT ODD/EVEN PARITY CHECKER

:
TRUTH TABLE
I7 I6 I5 I4 I3 I2 I1 I0 I7’I6’I5’I4’I3’I2’11’ I0’ Active ∑E ∑O
0 0 0 0 0 0 0 1 0 0 0 0 0 0 00 1 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 10 0 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 10 1 0 1

LOGIC DIAGRAM:

4 BIT ODD/EVEN PARITY CHECKER

TRUTH TABLE
ODD/EVEN PARITY CHECKER
INPUT OUTPUT
A B C D ODD EVEN
0 0 0 0 1 0
0 0 0 1 0 1
0 0 1 0 0 1
0 0 1 1 1 0
0 1 0 0 0 1
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 0 1
1 0 0 0 0 1
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 0 1
1 1 0 0 1 0
1 1 0 1 0 1
1 1 1 0 0 1
1 1 1 1 1 0
LOGIC DIAGRAM:
16 BIT ODD/EVEN PARITY GENERATOR

TRUTH TABLE:

I7 I6 I5 I4 I3 I2 I1 I0 I7 I6 I5 I4 I3 I2 I1 I0 Active ∑E ∑O
1 1 0 0 0 0 0 0 1 1 0 0 0 0 00 1 1 0
1 1 0 0 0 0 0 0 1 1 0 0 0 0 00 0 0 1
1 1 0 0 0 0 0 0 0 1 0 0 0 0 00 0 1 0

LOGIC DIAGRAM:
4BIT ODD/EVEN PARITY GENERATOR

TRUTH TABLE:
INPUT OUTPUT
A B C ODD EVEN
0 0 0 1 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 0 1
PROCEDURE:

(i) Connections are given as per circuitdiagram.

(ii) Logical inputs are given as per circuitdiagram.

(iii) Observe the output and verify the truthtable.

RESULT:

Thus the 16 bit odd/even parity checker and generator circuit designed and implemented
using IC 74180.
Ex. No: DESIGN AND IMPLEMENTATIOIN OF 4 BIT
Date:
RIPPLECOUNTER AND MOD 10/MOD 12
RIPPLECOUNTER

Aim:
To design and verify 4 bit ripple counter mod 10/ mod 12 ripple counter.

Apparatus Required:

Sl.No. Component Specification Qty.

1. JK FLIP FLOP IC 7476 2

2. NAND GATE IC 7400 1

3. IC TRAINER KIT - 1

4. PATCH CORDS - 30

Theory:

A counter is a register capable of counting number of clock pulse arriving at

its clock input. Counter represents the number of clock pulses arrived. A specified
sequence of states appears as counter output. This is the main difference between a
register and a counter. There are two types of counter, synchronous and
asynchronous. In synchronous common clock is given to all flip flop and in
asynchronous first flip flop is clocked by external pulse and then each successive
flip flop is clocked by Q or Q output of previous stage. A soon the clock of second
stage is triggered by output of first stage. Because of inherent propagation delay time
all flip flops are not activated at same time which results in asynchronous operation.
PIN Diagram for IC 7476:

Logic Diagram for 4 Bit Ripple Counter:

Truth Table:

CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1

13 1 0 1 1

14 0 1 1 1

15 1 1 1 1
Logic Diagram for Mod - 10 Ripple Counter:

Truth Table:

CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0
 6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 0 0 0

Logic Diagram for Mod - 12 Ripple Counter:

Truth Table:

CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 0 0
PROCEDURE:

(ii) Connections are given as per circuitdiagram.

(iii) Logical inputs are given as per circuitdiagram.
(iv) Observe the output and verify the truthtable.

Result:
Thus, the 4 bit ripple counter mod 10/ mod 12 ripple counters was designed and verified.
Ex. No: DESIGN AND IMPLEMENTATION OF 3
Date:
BITSYNCHRONOUS UP/DOWN COUNTER

Aim:

To design and implement 3 bit synchronous up/down counter .

Apparatus Required:

Sl.No. Component Specification Qty.

1. JK FLIP FLOP IC 7476 2

2. 3 I/P AND GATE IC 7411 1

3. OR GATE IC 7432 1

4. XOR GATE IC 7486 1

5. NOT GATE IC 7404 1

6. IC TRAINER KIT - 1

7. PATCH CORDS - 35

Theory:

A counter is a register capable of counting number of clock pulse arriving at

its clock input. Counter represents the number of clock pulses arrived. An up/down
counter is one that is capable of progressing in increasing order or decreasing order
through a certain sequence. An up/down counter is also called bidirectional counter.
Usually up/down operation of the counter is controlled by up/down signal. When
this signal is high counter goes through up sequence and when up/down signal is low
counter follows reversesequence.
K- MAP

State Diagram:
Characteristics Table:

Q Qt+1 J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

Logic Diagram:
Truth Table:

Input Present State Next State A B C

Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC

0 0 0 0 1 1 1 1 X 1 X 1 X

0 1 1 1 1 1 0 X 0 X 0 X 1

0 1 1 0 1 0 1 X 0 X 1 1 X

0 1 0 1 1 0 0 X 0 0 X X 1

0 1 0 0 0 1 1 X 1 1 X 1 X

0 0 1 1 0 1 0 0 X X 0 X 1

0 0 1 0 0 0 1 0 X X 1 1 X

0 0 0 1 0 0 0 0 X 0 X X 1

1 0 0 0 0 0 1 0 X 0 X 1 X

1 0 0 1 0 1 0 0 X 1 X X 1

1 0 1 0 0 1 1 0 X X 0 1 X

1 0 1 1 1 0 0 1 X X 1 X 1

1 1 0 0 1 0 1 X 0 0 X 1 X

1 1 0 1 1 1 0 X 0 1 X X 1

1 1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 1 0 0 0 X 1 X 1 X 1
Procedure:

(v) Connections are given as per circuitdiagram.

(vi) Logical inputs are given as per circuitdiagram.
(vii) Observe the output and verify the truthtable.

Result:

Thus, 3 bit synchronous up/down counter was designed and implemented.

 Ex. No:
DESIGN AND IMPLEMENT SHIFT-REGISTERS.
Date:

AIM
To design and implement

(i) Serial in serialout

(ii) Serial in parallelout
(iii) Parallel in serialout
(iv) Parallel in parallelout

Apparatus Required:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2

2. OR GATE IC 7432 1

3. IC TRAINER KIT - 1

4. PATCH CORDS - 35

Theory:

A register is capable of shifting its binary information in one or both directions

is known as shift register. The logical configuration of shift register consist of a D-
Flip flop cascaded with output of one flip flop connected to input of next flip flop.
All flip flops receive common clock pulses which causes the shift in the output of
the flip flop.The simplest possible shift register is one that uses only flip flop. The
output of a given flip flop is connected to the input of next flip flop of the register.
Each clock pulse shifts the content of register one bit position to right.
Pin Diagram:

Logic Diagram:

SERIAL IN SERIAL OUT:

Truth Table:

CLK Serial in Serial out

1 1 0

2 0 0

3 0 0

4 1 1

5 X 0

6 X 0

7 X 1

Logic Diagram:

SERIAL IN PARALLEL OUT:

Truth Table:

OUTPUT

CLK DATA QA QB QC QD

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1

4 1 1 0 0 1

Logic Diagram:

PARALLEL IN SERIAL OUT:

Truth Table:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

Logic Diagram:

PARALLEL IN PARALLEL OUT:

Truth Table:

DATA INPUT OUTPUT

CLK DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0

Procedure:

(i) Connections are given as per circuitdiagram.

(ii) Logical inputs are given as per circuitdiagram.
(iii) Observe the output and verify the truthtable.

Result:

Thus, the Serial in serial out, Serial in parallel out, Parallel in serial out,
Parallel in parallel out was designed and implemented using flip flops.
Ex. No: DESIGN AND IMPLEMENTATION OF ENCODER AND
DECODER
Date:

AIM
To design and implement encoder and decoder using logic gates and study of IC 7445
and IC 74147.

Apparatus Required:

Sl.No. Component Specification Qty.

1. 3 I/P NAND Gate IC 7410 2

2. OR Gate IC 7432 3

3. NOT Gate IC 7404 1

2. IC Trainer Kit - 1

3. Patch Cords - 27

Theory:

Encoder:

An encoder is a digital circuit that perform inverse operation of a decoder. An

encoder has 2n input lines and n output lines. In encoder the output lines generates
the binary code corresponding to the input value. In octal to binary encoder it has
eight inputs, one for each octal digit and three output that generate the corresponding
binary code. In encoder it is assumed that only one input has a value of one at any
given time otherwise the circuit is meaningless. It has an ambiguila that when all
inputs are zero the outputs are zero. The zero outputs can also be generated when
D0 = 1.
Decoder:

A decoder is a multiple input multiple output logic circuit which converts

coded input into coded output where input and output codes are different. The input
code generally has fewer bits than the output code. Each input code word produces
a different output code word i.e there is one to one mapping can be expressed in truth
table. In the block diagram of decoder circuit the encoded information is present as
n input producing 2npossible outputs. 2n output valuesare from 0 through out 2n –1.

PIN Diagram forIC 7445: PIN Diagram for IC74147:

BCD to DecimalDecoder:
Logic Diagram for Encoder:

Truth Table:

INPUT OUTPUT

Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C

1 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 0
 0 0 1 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 1 1 1 1

Logic Diagram for Decoder:

Truth Table:

INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

Procedure:

(i) Connections are given as per circuitdiagram.

(ii) Logical inputs are given as per circuitdiagram.
(iii) Observe the output and verify the truthtable.

Result:

Thus, the encoder and decoder were designed using logic gates and implement .