Introduction: A Brief History, MOS Transistors, MOS Transistor Theory, Ideal I-V

Characteristics, Non-ideal I-V Effects, DC Transfer Characteristics (1.1, 1.3, 2.1, 2.2, 2.4,
2.5 of TEXT2).
Fabrication: nMOS Fabrication, CMOS Fabrication [P-well process, N-well process, Twin tub
process], BiCMOS Technology (1.7, 1.8,1.10 of TEXT1).

A Brief History:
• We have called it the Transistor, T-R-A-N-S-I-S-T-O-R, because it is a resistor or semiconductor
device which can amplify electrical signals as they are transferred through it from input to output
terminals.
• In 1947, John Bardeen and Walter Brattain built the first functioning point contact transistor at Bell
Laboratories.
• Ten years later, Jack Kilby at Texas Instruments realized the potential for miniaturization if multiple
transistors could be built on one piece of silicon.
• Ten years later, Jack Kilby at Texas Instruments realized the potential for miniaturization if multiple
transistors could be built on one piece of silicon.
• In 1963, Frank Wanlass at Fairchild described the first logic gates using MOSFETs.
• Fairchild’s gates used both nMOS and pMOS transistors, earning the name Complementary Metal
Oxide Semiconductor, or CMOS. The circuits used discrete transistors but consumed only nanowatts
of power, six orders of magnitude less than their bipolar counterparts.
• With the development of the silicon planar process, MOS integrated circuits became attractive for their
low cost because each transistor occupied less area and the fabrication process was simpler.
•

Moore’s Law:-
“The number of transistors embedded on the chip doubles after every one and a half Year.” The number of
transistors is taken on the y-axis and the years in taken on the x-axis.
The diagram also shows the speed in MHz. the graph given in figure also shows the variation of speed of the
chip in MHz.
The graph in figure2 compares the various technologies available in ICs.
• From the graph we can conclude that GaAs technology is better but still it is not used because of
growing difficulties of GaAs crystal.
• CMOS looks to be a better option compared to nMOS since it consumes a lesser power.
• BiCMOS technology is also used in places where high driving capability is required and from the
graph it confirms that, BiCMOS consumes more power compared to CMOS.

Integrated circuits era:

Integrated Circuit
• Integrated Circuit is the circuit in which all the Passive and Active components are fabricated onto a single
chip. Initially the Integrated Chip could accommodate only a few components.
• As the days passed, the devices became more complex and required more number of circuits which made
the devices look bulky.
• Instead of accommodating more circuits in the system, an Integration technology was developed to
increase the number of components that are to be placed on a single chip.
• This Technology not only helped to reduce the size of the devices but also improved their speed.
Depending upon the number of components (Transistors) to be integrated, they were categorized as SSI,
MSI, LSI, VLSI, ULSI & GSI.

Small Scale Integration (SSI): In this Technology, 1-100 Transistors were fabricated on a single chip.
Eg Gates , Flipflops.

Medium Scale Integration (MSI): Using this Technology, 100-1000 number of Transistors could be integrated
on a single chip.
Eg 4 bit Microprocessors.

Large Scale Integration: In this Technology, 1000-10000 Transistors could be integrated on a single chip.
Eg 8 bit Microprocessors, RAM, ROM

Very Large Scale Integration(VLSI): In this Technology, 10000-1 Million Transistors could be accommodated.
Eg 16-32 bit Microprocessors.
Ultra Large Scale Integration(ULSI): In this Technology, 1 Million-10 Million Transistors could be
accommodated.
Eg Special Purpose Registers.

Giant Scale Integration (GSI): In this Technology more than 10 Million Transistors could be accommodated.
Eg Embedded Systems.

Basic MOS Transistors:

• Silicon (Si), a semiconductor, forms the basic starting material for most integrated circuits. Pure
silicon consists of a three-dimensional lattice of atoms. Silicon is a Group IV element, so it forms
covalent bonds with four adjacent atoms, as shown in Figure.4a

Why the name MOS?

We call Metal Oxide Semiconductor transistor, because the structure consists of a layer of Metal (gate), a
layer of oxide (Sio2) and a layer of semiconductor. Figure 3 below clearly tell why the name MOS.

Figure 3. cross section of a MOS structure

We have two types of FETs. They are Enhancement mode and depletion mode transistor. Also we have PMOS
and NMOS transistors.
• In Enhancement mode transistor channel is going to form after giving a proper positive gate voltage.
We have NMOS and PMOS enhancement transistors.
• In Depletion mode transistor channel will be present by the implant or adding of dopants at the time
of fabrication. It can be removed by giving a proper negative gate voltage. We have NMOS and PMOS
depletion mode transistors.

N-MOS depletion mode transistor: -

This transistor is normally ON, even with Vgs=0 because the channel will be implanted while fabricating,
hence it is normally ON.
To remove or break the channel between source and drain, a – ve voltage must be applied between gate and
source.
NOTE: Mobility of electrons is 2.5 to 3 times faster than holes. Hence P-MOS devices will have more
resistance compared to NMOS.

Depletion mode Transistor action:-

We can explain the working of depletion mode transistor in the same manner, as that of the enhancement mode
transistor only difference is, channel is established due to the implant even when Vgs = 0 and the channel can
be cut off by applying a –ve voltage between the gate and source. Threshold voltage of depletion mode
transistor is around 0.8*Vdd.
Working of Enhancement mode Transistor:-
Formation of channel in nMOS
When there is no gate source voltage (Vgs=0) all the majority carrier (holes) accumulate below the gate region
this is known as accumulation region.
When the gate source voltage is less than the threshold voltage (Vgs <<Vt) the majority carriers in the p
substrate gets rippled by the positive voltage at the gate causing depletion region.
When the gate source voltage is greater or equal to threshold voltage (Vgs > Vt) the minority
carriers(electrons) in the p substrate gets attracted by the positive voltage at the gate and gets accumulate
below the gate region forming a channel this region is called inversion region.
Note: even though the channel is formed no current flows until drain source voltage is applied.
To establish the channel between the source and the drain a minimum voltage (Vt) must be applied between
gate and source. This minimum voltage is called as “Threshold Voltage”.

a) Vgs > Vt and Vds = 0

Since Vgs > Vt and Vds = 0 the channel is formed but no current flows between drain and source.

b) Vgs > Vt and Vds < Vgs – Vt

This region is called the non-saturation Region or linear region where the drain current increases linearly with
Vds. When Vds is increased the drain side becomes more reverse biased (hence more depletion region towards
the drain end) and the channel starts reduce and move towards source.
c) Vgs > Vt and Vds > Vgs – Vt

This region is called Saturation Region where the drain current remains almost constant. As the drain voltage
is increased further beyond (Vgs-Vt) channel starts to move from the drain end to the source end and pinch
off occurs. Even if the Vds is increased more and more, a constant current will flow between source and drain.
The typical threshold voltage for an enhancement mode transistor is given by Vt = 0.2 *Vdd

Ideal IV Characteristics:
Second Order Effects or NON-IDEAL IV Characteristics:
Following are the list of second order effects of MOSFET.
• Mobility Degradation
• Threshold voltage – Body effect
• Sub threshold region
• Channel length modulation
• Mobility variation
• Fowler_Nordheim Tunneling
• Drain Punch through
• Impact Ionization – Hot Electrons
• Temperature Dependence

Mobility degradation:
• The saturation current increases less than quadratically with increasing Vgs . This is caused by two
effects: velocity saturation and mobility degradation.
• At high lateral field strengths (Vds /L), carrier velocity ceases to increase linearly with field strength.
This is called velocity saturation and results in lower Ids than expected at high Vds .
• At high vertical field strengths (Vgs /tox ), the carriers scatter off the oxide interface more often,
slowing their process this is called mobility degradation.

Threshold voltage – Body effect:

The change in the threshold voltage of a MOSFET, because of the voltage difference between source and the
substrate is called body effect. The expression for the threshold voltage is given by the following expression.

Where
Vt is the threshold voltage,
Vt(0) is the threshold voltage without body effect
γ is the constant

q is charge on electron,
єsi is dielectric constant of silicon substrate ,
єox is dielectric constant of silicon dioxide.
Subthreshold region:
For Vgs<Vt we think MOSFET is in cutoff region no channel is formed hence no current flows but there exist
a weak channel between source and drain hence a small value of Drain current flows this is called as
Subthreshold current and the region is called as Subthreshold region.
Channel length modulation:
As the technology gets scaled the length of the channel gets reduced, during saturation region there should be
a constant current flow but there will be a small variation in the current this variation is called channel length
modulation. As the channel length increases this effect reduces.

where λ represents Channel length modulation

Mobility:
Mobility is the ratio of average carrier drift velocity and electric field. Mobility is represented by the symbol
μ.
𝑎𝑣𝑒𝑟𝑎𝑔𝑒 𝑐𝑎𝑟𝑟𝑖𝑒𝑟 𝑑𝑟𝑖𝑓𝑡 𝑣𝑒𝑙𝑜𝑐𝑖𝑡𝑦 (𝑣)
µ=
𝐸𝑙𝑒𝑐𝑡𝑟𝑖𝑐 𝐹𝑖𝑒𝑙𝑑(𝐸)

Mobility may varies in number of ways

• Electrons have higher mobility than holes, resulting in N-device having higher current producing
capability than the corresponding P-device.
• Mobility decreases with increase in doping concentration and increase in temperature.

Fowler Nordhiem tunneling:

When the gate oxide is very thin, a current can flow between gate to source or drain by electron tunneling
through the gate oxide. This current is proportional to the area of the gate of the transistor.

• This effect limits the thickness of the gate oxide as processes are scaled.

Drain punchthough:
When the drain is a high voltage, the depletion region around the drain may extend to the source, causing the
current to flow even if gate voltage is zero. This is known as Punchthrough condition.
• This effect is used in I/O protection circuits.
Impact Ionization-hot electrons:
When the length of the transistor is reduced, the electric field at the drain increases. The field can become so
high that electrons gain enough energy we can term them as hot. These hot electrons impact the drain,
dislodging holes that are then swept toward the negatively charged substrate and appear as a substrate current.
This effect is known as Impact Ionization.
The electron can penetrate the gate oxide causing gate current, this can lead to degradation of the MOSFET
device, which in turn causes failure of the circuits
Temperature Dependence:
• Transistor characteristics are influenced by temperature
• Carrier mobility decreases with temperature.

•
• where T is the absolute temperature, Tr is room temperature, and kµ is a fitting parameter with a
typical value of about 1.5. vsat also decreases with temperature, dropping by about 20% from 300 to
400 K.
• The magnitude of the threshold voltage decreases nearly linearly with temperature and may be
approximated by

CMOS INVETER CHARACTERISTICS:

• CMOS inverters (Complementary MOSFET Inverters) are most widely used inverters used in chip
design.
• They operate with less power consumption and at relatively high speed. Furthermore, the CMOS
inverter has large noise margins in both low and high state.
• A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate terminals,
a supply voltage VDD at the PMOS source terminal, and a ground connected at the NMOS source
terminal, were VIN is connected to the gate terminals and VOUT is connected to the drain terminals.
(given in diagram).
Graphical Derivation of Inverter DC Characteristics:
• The actual characteristics are drawn by plotting the values of output voltage for different values of the
input voltage. We can also draw the characteristics, starting with the VI characteristics of PMOS and
NMOS characteristics.
Influence of βn/βp on the Transfer characteristics:
To find the variation of transfer characteristic as a function of βn/βp, the transfer curve for
several values of βn/βp are plotted as shown below

• The characteristics shifts left if the ratio of βn/βp is greater than 1(say 10). The curve shifts right if
the ratio of βn/βp is lesser than 1(say 0.1).
• For βn=βp the inverter threshold voltage Vinv is VDD/2. This may be desirable because it maximizes noise
margins.
• Inverters with different beta ratios r = βn=βp are called skewed inverters. If r > 1, the inverter is HI-
skewed. If r < 1, the inverter is LO-skewed. If r = 1, the inverter has normal skew or is unskewed.
• A HI-skew inverter has a stronger pMOS transistor. Therefore, if the input is VDD /2, we would expect
the output will be greater than VDD /2. In other words, the input threshold must be higher than for an
unskewed inverter. Similarly, a LO-skew inverter has a weaker pMOS transistor and thus a lower
switching threshold.
• As temperature of an MOSFET device is increased, the mobility decreases, this results in decrease in
β.
• decrease in β, with temperature is given by β α T-1.5

Noise Margin:
• Noise margin is a parameter related to input output characteristics.
• It determines the allowable noise voltage on the input so that the output is not affected.

We will specify it in terms of two things:

LOW noise margin
HIGH noise margin

LOW noise margin: is defined as the difference in magnitude between the maximum Low output voltage
of the driving gate and the maximum input Low voltage recognized by the driven gate.
NML=|VILmax – VOLmax|

HIGH noise margin: is defined difference in magnitude between minimum High outputs Voltage of the
driving gate and minimum input High voltage recognized by the receiving gate.
NMH=|Vohmin – VIHmin|
 • Inputs between VIL and VIH are said to be in the indeterminate region or forbidden zone and do not
represent any digital logic levels.
• Therefore, it is generally desirable to have VIH as close as possible to VIL and for this value to be
midway in the “logic swing,” VOL to VOH.
• the transfer characteristic of the inverter and the definition of voltage levels VIL, VOL, VIH, and VOH
are shown in Figure 2.30.
• Logic levels are defined at the unity gain point where the slope is –1.
• the output is slightly degraded when the input is degraded; this is called noise feedthrough or
propagated noise.
• An unskewed (βn=βp) gate has equal noise margins, which maximizes immunity to arbitrary noise
sources.
• If a gate sees more noise in the high or low input state, the gate can be skewed to improve that noise
margin
Pass transistors:
We have N and P pass transistors.
NMOS Pass Transistors:
• Consider the nMOS pass transistor, Initially the load capacitor C load is discharged (i.e Vout = Vss),
S=0, Vout = Vss irrespective of input Vin.
• when S=1, and Vin= 1, the nMOS transistor begin to conduct and current starts to flow from higher
potential (Vin) to lower potential (Vout) and charges the load capacitor towards Vdd, as the voltage
approaches Vout –Vtn the nMOS turns “OFF” thus degrading passing of logic 1.
• when S=1, and Vin= 0, the nMOS transistor begin to conduct and current starts to flow from higher
potential (Vout) to lower potential (Vin) and discharges the load capacitor towards Vss, thus passing
logic 0 without degrading.

PMOS Pass Transistors:

• Consider the pMOS pass transistor,Initially the load capacitor Cload is discharged (i.eVout = Vss), S=1,
Vout = Vss irrespective of input Vin.
• when S=0, and Vin= 1, the pMOS transistor begin to conduct and current starts to flow from higher
potential (Vin) to lower potential (Vout) and charges the load capacitor towards Vdd, thus passing
logic 1 without degrading.
• when S=0, and Vin= 0, the pMOS transistor begin to conduct and current starts to flow from higher
potential (Vout) to lower potential (Vin) and discharges the load capacitor towards Vss, but as the
voltage approaches Vtp the pMOS turns “OFF” thus degrading passing of logic 0.
Nmos Fabrication:
N-WELL Cmos process:
P-well Cmos Process:
The fabrication of p-well cmos process is similar to n-well process except that p-wells acts as substrate for the n-
devices within the parent n substrate.
Twin Tub Process:

Bi-CMOS technology: - (Bipolar CMOS)

• The driving capability of MOS transistors is less because of limited current sourcing and sinking
capabilities of the transistors hence to drive large capacitive loads we can think of Bi-Cmos technology.
• This technology combines Bipolar and CMOS transistors in a single integrated circuit, by retaining
benefits of bipolar and CMOS.
 • BiCMOS is able to achieve VLSI circuits with speed-power-density performance previously
unattainable with either technology individually.

Characteristics of CMOS Technology:

• Lower static power dissipation
• Higher noise margins
• Higher packing density – lower manufacturing cost per device
• High yield with large integrated complex functions
• High input impedance (low drive current)
• Scalable threshold voltage.
• High delay sensitivity to load (fan-out limitations)
• Low output drive current (issue when driving large capacitive loads)
• Low transconductance, where transconductance, gm a Vin
• Bi-directional capability (drain & source are interchangeable)
• A near ideal switching device

Characteristics of Bipolar Technology:

• Higher switching speed
• Higher current drive per unit area, higher gain
• Generally better noise performance and better high frequency characteristics
• Better analogue capability
• Improved I/O speed (particularly significant with the growing importance of package limitations in high
speed systems).
• High power dissipation
• Lower input impedance (high drive current)
• Low voltage swing logic
• Low packing density
• Low delay sensitivity to load
• High gm (gm a Vin)
• High unity gain band width (ft) at low currents
• Essentially unidirectional

The diagram given below shows the cross section of the BiCMOS process which uses an npn transistor.

Figure 14 Cross section of BiCMOS process

The figure below shows the layout view of the BiCMOS process.
• The fabrication process of bicmos is similar to that of cmos process except two additional layers that
is n+ sub-collector and p+ base layers.
• The npn is formed in an n-well and additional p+ base region is located in the well to form the p-base
region of the transistor.
• The second layer the buried n+ subcollector is added to reduce the collector resistance and thus improve the
quality of bipolar transistor.