LECTURE PLAN

MICROPROCESSOR AND COMPUTER ARCHITECTURE (ECECC12/EIECC13)

Course Course Name Course Structure

Code
ECECC12/ Microprocessors and L-T-P 3-0-2
EIECC13 Computer
Architecture
COURSE OUTCOME (CO):
CO1: To comprehend the instruction set architecture of 8085 microprocessor, instruction cycle and concept of interfacing
CO2: To understand instruction set architecture of 8086 microprocessor.
CO3: To familiarize students with processor architecture, instruction set architecture and assembly language programming in
general
CO4: To develop understanding and operation of memory system and different memory types.
UNIT Course Content: Lecture Practical
No.
Unit-I: 8086 PROCESSOR: Von-Neumann & Harvard CPU 01-02
(10) architecture and CISC & RISC CPU architecture. 8086 CPU 1. Write a program to arrange the 10
Architecture. numbers in SRAM memory in
Addressing modes 03 ascending order. Repeat you
Physical memory Organization, General Bus operation cycle, 04 experiment to arrange the data in
I/O addressing capability, Special processor activities, descending order.
Minimum mode 8086 system and Timing diagrams, 05 2. Develop a subroutine for Multiply
and divide operations.
Maximum Mode 8086 system and Timing diagrams. 06
INSTRUCTION SET OF 8086: Data transfer and arithmetic 07
instructions. Control/Branch Instructions,
Logical Instructions, String manipulation instructions, Flag 08
manipulation and Processor control instructions,
Illustration of these instructions with example programs. 9-10
Assembler Directives and Operators, Assembly Language
Programming and example programs
Class Test- 1
Unit-II: Introduction to stack, Stack structure of 8086, Programming for 11 3. Write routines to convert Binary
(08) Stack, to ASCII, ASCII to binary,
binary to BCD, BCD to binary.
 Interrupts and Interrupt Service routines, Interrupt cycle of 8086, 12-13 4. Move a block of data from a
NMI, INTR, Interrupt programming, Passing parameters to source address location to target
procedures address location using assembly
language programming in 8086
Macros, Timing and Delays. 14
5. Study the operation of 8255
Basic Peripherals and their Interfacing with 8086: Static RAM 15-16 Interface Card. As outlined in
Interfacing with 8086 (5.1.1), Interfacing I/O ports, the 8255 Study Card Manual.
PIO 8255, Modes of operation – Mode-0 and BSR Mode, 17-18
Interfacing ADC-0808/0809, DAC-0800, 8259.
UNIT-III CPU structure and functions, processor organization 19 6. Study of 8259 Interface Card.
(07) ALU, data paths, internal registers, 20 As outlined in the 8259 Study
MID Sem Examination Card Manual. MATLAB
Status flags; System bus structure: Data, address and control 21 7. Design, model and test using
buses HDL (hardware description
Processor control, micro-operations, instruction fetch, hardwired 22-24 language), a Sign magnitude
vs. microprogrammed control adder, BCD incrementor, Gray
Microinstruction sequencing and execution 25 Counter and LFSR based
random number generator.
UNIT-IV Instruction set principles, machine instructions, types of 26-27 8. Study of 8259 Interface Card.
(08) operations and operands, encoding an instruction set As outlined in the 8259 Study
assembly language programming, addressing modes and formats 28-30 Card Manual. MATLAB
Class Test-2 9. Design, model and test using
Pipelining: basic concepts of pipelining, throughput and speed, 31-32 HDL (hardware description
pipeline hazards language), a Sign magnitude
Comparison between CISC and RISC architecture, Introduction 33 adder, BCD incrementor, Gray
to RISC-V and domain specific architectures Counter and LFSR based
random number generator.
UNIT-V Memory system, internal and external memory 34-35 10. HDL behavioral model for a 32-
(07) Memory hierarchy, cache, memory and its working 36 bit MIPS ALU
Virtual memory concept, I/O organization; I/O techniques 37 11. Write a program to test the
Interrupts, polling, 38 RAM on the Kit.
DMA; Synchronous vs. asynchronous I/O 39-40
Textb o o k s :
[T1] Hall, D.V., “Microprocessors and Interfacing”, 2nd Ed., Tata McGraw Hill. 2006
[T2] Brey, B.B., “The Intel Microprocessors”, 6th Ed., Pearson Education. 2003
[T3] Mano, M.M., “Computer System Architecture” 3rd Ed., Prentice-Hall of India. 2004
[T4] Mano M. M., Celletti M. D., “Digital Design”5th Edition, Pearson 2013
[T5] Rajaraman, V. and Radhakrishnan, T., “Computer Organization and Architecture”, Prentice-Hall of India. 2007
[T6] Govindarajulu, B., “Computer Architecture and Organization”, Tata McGraw-Hill. 2004
[T7] Stallings, W., “Computer Organization and Architecture”, 5th Ed., Pearson Education. 2001
[T8] D.A. Patterson, J.L. Hennessy, “Computer Architecture: A Quantitative Approach”, Sixth Edition, Morgan Kaufmann,
2017.

EVALUATION SCHEME FOR CONTINUOUS ASSESSMENT:

Sr. No. Component Continuous Assessment Marks
1. TCA (15) 2 class tests 5
2. Three Assignments 5
3. Attendance/Response in Class 5
4. PCA (15) 1 Lab Test/Viva 5
5. Lab Files, Attendance/Performance in Lab 1 mark per turn (max 10)
Total 30 marks

For any difficulties related to the course, students may contact the following:
S. No. CCC Name Contact E Mail
1 Chairperson 1. Dr. Sukhbir Singh 1. [email protected]
2 Co-Chairperson --
3 Course Instructor 1. Dr. Sukhbir Singh (EIECC13) 1. [email protected]
2. Mr. Manish Rai (ECECC12, Sec-1) 2. [email protected]
3. Mr. Prakash Chandra (ECECC12, Sec-2) 3. [email protected]
4. Ms. Shalini (ECECC12, Sec-3) 4. [email protected]

Dr. Sukhbir Singh

CCC, Chairperson