IMAGINATION

UNiVERSITY
PROGRAMME
Let us empower you to use our technologies in your teaching labs and student projects!
We have 29 years’ experience of helping teachers around the world…

The four vital components in our The majors & courses we focus on:
teaching packages: • Computer Science/Engineering (“CS”/“CE”)
Tools: free to download software development • Games Design/Engineering/Programming
tools. Full versions with no code size or time limits!
• Electrical & Electronic Engineering (“EE”)
Hardware: low-cost, robust, and effective hardware
• Automotive Engineering
from our partners
• Computer Architecture
Materials: not in-house/commercial training.
• System-on-Chip (“SoC”) Design
Genuine teaching materials written by academics
who are respected experts in their field. With • Graphics
licensing that allows sharing with students, editing, • GPU Acceleration & Compute
translation and unrestricted • AI: Artificial Intelligence
academic/not-for-profit use • Autonomous Vehicles and In-Vehicle Systems
Effective support: through our forums, online
video tutorials, and online/on-campus workshops
Introduction to Mobile Graphics
Scope: Hardware: Languages:
The first course on Mobile Acer Chromebook, Android phones English, Chinese (simplified &
Graphics, / tablets, BeagleBone Black/AI 64 traditional),
with Lectures and Labs. A full OR: Software Emulator on a PC Japanese, Korean
semester course.
Online Video Tutorials Support:
Author: One Day Workshop: materials & IUP Forum: university.imgtec.com/
Darren McKie, University of Hull, UK package and videos from April’22 forums
London Workshop
Partners: Request & Download:
BeagleBoard.org Online self-study course in Chinese university.imgtec.com/teaching-
on XuetangX download
Audience:
3rd year BSc/MSc Gaming, EE and Tool-Chain: PowerVR SDK
CS Students

Week Lecture Topic Details

1 Introduction to mobile graphics Introduction to the different graphics APIs available and how
technologies they compare.

1-2 Basics of the PowerVR How the simple triangle graphics program has been written
Framework, and simple Object using the PowerVR SDK. How to separate the triangle code
Orientated Design out of the main drawing function and into its own class.

2-3 Introduction to mobile graphics Comparison of mobile’s dominant graphics hardware, an

architectures introduction to the concerns relating to power consumption
and performance, and to understand the cross-platform/
cross-compilation benefits of OpenGL ES. The PowerVR
Graphics architecture case study will be outlined.

3-4 Introduction to graphics SDKs and Learn about the main technologies used in mobile graphics
forums SDKs up to OpenGL ES 3.2 and to learn how to use some of
the SDK utilities and how to use forums for help.

4-5 Texturing How texturing works, including the coordinate system and
performance concerns.

5 Transformations IHow transformations and lighting can be applied to vertices,

including translations, rotations, and how to apply lighting.

6-7 OpenGL ES basics Learn the basics of the OpenGL ES commands and Shader
Language.

7-8 OpenGL ES lighting Learn how to use different lighting models to illuminate
objects in a scene.

9 Reflection and Refraction Learn how cubemaps can be created and how they are used
for calculating reflections and refractions.

9-10 Introduction to Vulkan Introduction to Vulkan and a comparison with OpenGL ES.
Overview of RVfpga Courses
The RVfpga: Understanding Computer Architecture course targets a soft-core
RISC-V CPU – the SweRV EH1 - to an FPGA. It guides users in setting up the
tools and ensuring the system is working. Through twenty well-documented
and thorough labs, it enables students to understand the workings of the CPU,
its interfaces to the outside world, and its core, pipeline, and memory system.

The follow-on course, RVfpga-SoC: An Introduction to SoC Design, enables users to gain hands-on
experience building a System-on-Chip (SoC). RVfpga-SoC guides users through the interconnect options,
adding peripherals, and then running an RTOS (real-time operating system) on the SoC. This course includes
five labs including one that shows how to run Tensorflow Lite on the SoC.

Both courses use the RVfpga system, which is based on Chips Alliance’s SweRVolf SoC that uses Western
Digital’s RISC-V SweRV EH1 core. SweRV EH1 is a fully-verified production-level processor core. SweRV EH1
is open-source and is already in silicon, including in Western Digital’s SSD data storage and in Imagination
Technologies’ latest GPUs.

We are passionate about sharing real-world in-silicon solutions with students and other RISC-V users. Why
use a “simplified education core” when you can use industrially proven designs? SweRV cores are at the
centre of a vibrant expanding ecosystem with many useful open-source and commercial tools available,
including simulators, models, integrated development environments (IDEs), virtual hardware, and pre-
configured FPGA-ready SoC implementations.

Scope Software
The teaching materials fully illustrate the fundamentals – Xilinx Vivado 2019.2 WebPACK
of computer architecture, the inner workings of a RISC – Microsoft’s Visual Studio Code
processor, and the process to get from a CPU to a –P latformIO with Chips Alliance platform, which
System-on-Chip Design. includes: RISC-V Tool-chain, OpenOCD, Verilator
HDL Simulator, Western Digital’s Whisper ISS
Authors
(instruction set simulator)
Dr. Sarah Harris, University of Nevada, Las Vegas (U.S.),
Dr. Daniel Chaver-Martínez, Universidad Complutense Hardware
de Madrid (Spain), Zubair Kakakhel (AKZY Ltd; UK) –D
 igilent Nexys A7 (100T) or Nexys 4 DDR
FPGA Board
Audience
Hardware is recommended but not required:
BSc Digital Design & Microarchitectures, Computer
- All labs can be completed in simulation, or using
Organisation & Architecture, BSc/MSc Advanced
“ViDBo” the Virtual Development Board.
Computer Architecture, MSc SoC design, MSc Design
Verification, BSc/MSc Embedded Systems projects Open source RISC-V Core & SoC
and MSc/PhD Processor Architecture – Core: Western Digital’s SweRV EH1
– SoC: Chips Alliance’s SweRVolf
Languages
English, Chinese (simplified & traditional), Japanese,
Korean, Russian, Spanish, Portuguese and Turkish
Understanding Computer Architecture
and Introduction to SoC Design
RVfpga (RISC-V FPGA) provides the foundation knowledge and hands-on experience that the next
generation of programmers and engineers need to harness the potential of RISC-V. The course is
suitable for undergraduate and master’s classes, self-study, and industry training. It includes many
resources for instructors who would like to teach Rvfpga, including: how to set up the course, how
to install hardware and software tools, lecture slides, lab instructions, examples and exercises with
solutions, and supplementary materials. Instructors could use a subset of the materials in a single-
semester course or run a two- to three-semester course using all of the materials.

Additional features & support:

• A Getting Started Guide and twenty labs with detailed instructions, examples, short questions and
practical exercises with solutions, giving teachers flexibility to choose between a practical and an
exam-based structure for the course.
• Provided in both PDF and .pptx/.docx formats enabling customisation by teachers to suit their own
needs.
• Available in nine languages: English, Simplified Chinese, Traditional Chinese, Japanese, Korean,
Spanish, Turkish, Russian, and Portuguese.
• Direct support and up-to-date news on Imagination University Programme Forum:
university.imgtec.com/forums

RVfpga: Sponsors & Supporters

Academic Adviser: Reviewer: Authors:
Prof. David Patterson Prof. Roy Kravitz Prof. Sarah Harris
University of California, Portland State University, U.S University of Nevada, Las
Berkeley Vegas

Contributors:
Olof Kindgren Assoc. Prof. Daniel Prof. Peng Liu Zubair Kakakhel
Qamcom Research & Chaver Martinez Zhejiang University, China AZKY Tech Ltd, Birmingham,
Technology Complutense University of UK
Gothenburg, Sweden Madrid

Supporters:
Semesters 1&2: RVfpga: Understanding
Computer Architecture
Lecture Topic
Details

Lab 0 RVfpga Labs Overview

Lab 1 C Programming

Lab 2 RISC-V Assembly Language

Lab 3 Function Calls

Lab 4 Image Processing: Projects with C & Assembly

Lab 5 Creating a Vivado Project

Lab 6 Introduction to I/O

Lab 7 7-Segment Displays

Lab 8 Timers

Lab 9 Interrupt-Driven I/O

Lab 10 Serial Buses

Lab 11 SweRV EH1 Configuration and Organization. Performance Monitoring

Lab 12 Arithmetic/Logical Instructions: the add instruction

Lab 13 Memory Instructions: the lw and sw instructions

Lab 14 Structural Hazards

Lab 15 Data Hazards

Lab 16 Control Hazards. Branch Instructions: the beq Instruction. The Branch Predictor.

Lab 17 Superscalar Execution

Lab 18 Adding New Features (Instructions, Hardware Counters) to the Core

Lab 19 Memory Hierarchy. The Instruction Cache.

Lab 20 ICCM and DCCM

Semester 3: RVfpga-SoC: Introduction to SoC Design

Lecture
Details
Topic
Lab 1 Introduction to RVfpga-SoC

Lab 2 Running Software on the RVfpga SoC

Lab 3 Introduction to SweRVolf and FuseSoC

Lab 4 Building and Running Zephyr on the SweRVolf

Lab 5 Running Tensorflow Lite on SweRVolf

Guide to RISC-V
RISC-V is big news in the semiconductor industry. What’s behind the buzz? We’ve teamed up with
Digi-Key to create a technology guide focused on RISC-V. Short, easy to understand, and hands-on.
Written by Richard J. Sikora, it draws on his 35 years’ experience in embedded systems development!

Contents (2) MCU microcontroller using the SiFive SoC on the

- RISC-V: its history and unique features SparkFun RED-V “Red Board”.
- Licencing (3) And a “soft core” – implementing Western Digital’s
- Where the technology is going… “SweRV” EH1 core on an FPGA from Xilinx – the
platform for our “Rvfpga” Teaching Materials.
- Early examples of implementations
- Hands-on with three implementations: Direct Download
university.imgtec.com/resources/download/
Real-World Examples
guidetoriscv
(1) M
 PU microprocessor running Linux using the
Kendryte CPU on the Seeed Technologies Maix
BiT board.

Fun with Beagle –

Exploring the GPU & Running OpenCL
The BeagleBone® Black is a favourite development platform for millions of users: Students, Hobbyists, and
Developers. It has become a preferred Single Board Linux Computer for industrial developers. The TI “Sitara™
system-on-chip at the heart of Beagle contains an Imagination SGX530 GPU. Until now, this was just a block on
the system diagram and a “black box” to most Beagle users. In recognition of Beagle’s popularity, we are lifting
the lid on its GPU…

Dr. Iain Hunter was at TI when the Sitara SoCs first appeared, and since then he has become a leading
independent developer on this platform. Few people know Beagle so well!

Graphics Online Video Tutorials

Materials from “Introduction to Mobile Graphics, 2020 • Preparation
Edition” run on Beagle, and this guide reprises some • Boot BeagleBone Black
basic examples.
• Configure SDK
• Compile SDK
Running Open CL
Dr. Hunter takes you through this interesting and quite • Build BeagleBone Black OpenCL Examples
complex part of the BeagleBone Black system. He • Run BeagleBone Black OpenCL
shows you how to implement Open CL on the GPU and • Build OpenCL audio
run an application. • Run ALSA OpenCL
• The package includes the Open CL driver along with a
practical explanation about getting it running and how
to use it
• The example demonstrates Audio Sample Rate
Conversion, running on the GPU – a first for the
Beagle Board!
Edge AI – Principles and Practices
Scope Associates
The full course is based on the development of 4 Paul Buxton, Robert Owen, Guanyang He
module, 9 units and 11 labs (L0-L10), which will cover
Platform
the fundamental algorithms and typical applications
BeagleBone AI 64 board running Imagination’s Neural
in Edge AI, following a case-study format and fitting a
Compute Software Development Kit (NC-SDK-AC)
typical semester course.
Audience
Authors
3rd year BSc EE and CS Students
Prof. Luis Pinuel Moreno, Prof. Francisco D. Igual -
Universidad Complutense de Madrid (Spain), Prof. Languages
Sandra Catalán, Rafael Rodriguez English, Chinese (simplified) to follow

Contributors
Prof. Xiaohui Duan - Peking University (China),
Chris Thomas

Week Lecture Topic Details

1. Introduction and Getting Introduction to Edge AI and the experimental platform

Started
Lab 0: Getting started with the Pumpkin board

2. Data acquisition and pro- Image processing fundamentals

Module 1.
cessing on the Edge Lab 1: Image acquisition and processing with OpenCV
Introduction
to Edge AI Introduction to Machine Learning, the IMG Neural Compute
SDK and the IMGDNN library
3. Introduction to Machine
Learning on the Edge Lab 2: First steps with the NCSDK
Lab 3: My first Neural Network on the Pumpkin board
Lab 4: My first Neural Network with imgDNN

4.Image classification Image classification on edge device

Lab 5: Image classifier example on the Pumpkin board
Module 2. Image segmentation on Edge devices
5. Image segmentation
Image vision
Lab 6: Semantic image segmentation on the Pumpkin board

6. Object detection Object detection on Eedge devices

Lab 7: SSD person detection on the Pumpkin board

Module 3. 7. Automatic Speech Recogni- Automatic Speech Recognition for Edge Devices
Speech tion (ASR)
Lab 8: Voice control of the Pumpkin board
and natural
language 8. Natural Language Process- NLP Fundamentals
processing ing (NLP)
Lab 9: Automatic question answering on the Pumpkin board

Module 4. Advanced NCSDK and OpenCL usage.

9: Advanced NCSDK and
Advanced
OpenCL usage. Lab 10: OpenCL-based pre- and post-processing
topics
IUP Website
The focal point to access our services is the IUP website: teaching materials, video tutorials, forums, suggested
hardware, recommended textbooks, pictures, news, and workshop + event listings.

Joining the IUP Requesting teaching materials

Visit Imagination University Programme website: Request the materials you want
university.imgtec.com Tell us what you plan to do
Click Register on the menu bar We will assess and respond to your request
Fill in the registration form. Please make sure you fill in within 3 working days
the items with green star Once approved, you will receive an email with
After submission, you will receive an email to set up the download link. Be quick - this link is only valid
your password for 3 days

Useful Textbooks

Computer Graphics: Principles and Digital Design & Computer Deep Learning (Adaptive
Practice (3rd Edition) Architecture (RISC-V Edition) Computation and Machine
John F. Hughes & Andries van Dam Sarah Harris & David Harris - Learning series)
Available in Chinese and English Sept’21 Ian Goodfellow, Yoshua Bengio,
Available in Chinese and English Aaron Courville
Available in Chinese and English

Hardware Tools

Digilent Nexys A7-100T Pumpkin i300 EVK BeagleBone® Black

Based on Xilinx Artix®-7 FPGA. Based on the Mediatek i300B The BeagleBone Black from
The -100T can ahold the Western SoC, ARM Quad-Core A35 1.3GHz beagleboard.org is based on the
Digital SweRV softcore. 7-segment processor, PowerVR 8XE GPU TI AM335x Arm Cortex-A8
digital displays & rich I/O make it a which supports openGL, openGL processor 512MB DDR3 RAM,
great fit for computer architecture ES and OpenCL. Together with the PowerVR SGX530 GPU with 3D
labs. The older Nexys 4 DDR is Nerual Compute SDK Academic graphics accelerator, microSD
also suitable. version, it could become an ideal card,HDMI, Ethernet, USB 2.0,
platform for you to run Edge 2x PRU 32-bit microcontrollers
AI applications.