PAAVAI ENGINEERING COLLEGE

ACADEMIC YEAR – 2024-2025

PRESENTER’S MANUAL

Department of ECE
Course Name: System Design with FPGA
Course Code: EC20552

1
What is Paavai Teaching Methodology?

At Paavai Educational Institutions, inclusive, flexible and insightful learning aims to provide engaging

educational experiences and meet the needs of learners from all the backgrounds. Teachers should align their

teaching with everyday life which will make learning meaningful.

This semester is based on the teaching methodology following three cardinal components:

1. Concept Class

2. Directed Learning Class

Concept class: This is a theory class that will focus on the concepts. Whenever required this session will also

demonstrate how these concepts get translated into Mechanical Engineering topics.

Directed Learning Class: Learning and application may be challenging for some students. One of the oldest

and most comprehensive ways of delivery information, self-directed class allows the student to apply

themselves in a manner that makes understanding content more accessible. In this process, learners take

initiative in their own learning by planning, implementing and evaluating their learning.

The entire purpose of this methodology is to make the students more:

 Concept focused

 Adapted to real life work environment

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EC20552 SYSTEM DIESIGN WITH FPGA 3 0 0 3

COURSE OBJECTIVES

To enable the students to

 Know the fundamentals of programmable logic devices

 Study the field programmable gate array
 Acquire the SRAM Programmable FPGAS
 Learn the necessity of Anti-Fuse Programmed FPGAS
 Gain the knowledge of design applications of FPGA

UNIT I Basics of Programmable Logic Devices 09

Introduction: Programmable Logic Array: Programmable Logic Devices, Generic Array Logic- Architecture
of Xilinx cool runner XCR3064XL CPLD: CPLD implementation of Parallel adder.

UNIT II Field Programmable Gate Arrays 09

Organization of FPGAs, FPGA programming Technologies, Programmable logic block Architectures,

Programmable Interconnects, Programmable I/O blocks in FPGA, Application of FPGAs.

UNIT III SRAM Programmable FPGAs 09

Introduction: Programming Technology, Device Architecture, Xilinx XC3000, XC4000 Architectures.

UNIT IV Anti-Fuse Programmed FPGAs 09

Introduction: Programming Technology, Device Architecture, Actel ACT2, ACT3 Architectures.

UNIT V Design Applications 09

Counter Examples: Fast Video Controller, Position Tracker for a Robot Manipulator, Design Counters with
ACT devices, Designing Adders and Accumulators with the ACT architecture

TOTAL PERIODS 45

3
Course Outcomes

At the end of the course, the students will be able to

 Examine the challenges in programmable logic devices.

 Analyze the different concept field programmable gate array.
 Design the SRAM programmable FGPAS
 Evaluate the necessity of Anti-Fuse programmed FPGAS
 Apply the concept of design applications on FPGA

TEXT BOOKS

1. Charles H.Roth Jr.Lizy Kuriyan John and Byeong Kil Lee. “ Digital System Design using Verilog”
Cengage I Earning 2016.

2. Stephen M. and Trim Berger “Field Programmable Gate Array Technology” Springer International Edition
1994.

REFERENCE

1. John V. Oldfield and Richard C Dorf “Field Programmable Gate Arrays” Wiley India 1995.

2. Pak K Chan Samiha Mourad “Digital Design using FPGA” Pearson Low Price Edition.2009.

3. Ian Grout “Digital System Design using FPGA and CPLDs” Elsevier. Newnes 2008.

4. Wayne Wolf “FPGA based System Design” Prentice Hall Modern Semiconductor Design Series.2004.

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Introduction to the Course
This Presenter’s Manual is to be used for the Seventh semester of Electronics and Communication
Engineering for the course of Design and Implementation. The syllabus of this course enhances the students’
knowledge and skill in designing of system with FGPA as well as implementation of the system.
Course Code- Theory: EC20552
Unit -1 Basics of Programmable Logic Devices
Unit -2 Field Programmable Gate Arrays
Unit -3 SRAM Programmable FPGAS
Unit -4 Anti-Fused Programmed FPGAS
Unit -5 Design Applications
Student Learning Outcomes:
Clearly written student learning outcomes are the foundation upon which effective courses are designed.
Outcomes inform both the ways students are evaluated in a course and the way a course will be organized.
Effective learning outcomes are student-centered, measurable, concise, meaningful, achievable and outcome-
based (rather than task-based). The course contents are designed for those who are keen on getting themselves
a career in the field of Electronics and Communication engineering, specifically for those who want to be
involved in the design of FGPA. At the end of the course, the students will be able to:

 Understand FPGA Architecture: Explain the architecture and fundamental components of

Field-Programmable Gate Arrays (FPGAs).
 Develop HDL Code: Write and debug hardware description language (HDL) code, such as
VHDL or Verilog, for designing digital circuits.
 Implement Digital Designs: Implement digital systems and designs on FPGA hardware,
including combinational and sequential circuits.
 Design State Machines: Create and optimize finite state machines (FSMs) for control logic in
digital systems.
 Interface with Peripheral Devices: Interface FPGAs with various peripheral devices such as
sensors, memory modules, and communication interfaces.
 Optimize Designs Apply optimization techniques to improve the performance, area, and power
consumption of FPGA-based designs.

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Pre-requisites for taking this course

 Problem Solving Skills

 Communication Skills
 Logical Thinking Skills
 Team Work
 Basic understanding System Design
 Understanding various sensors and transducers used in Design system
 Skill sets to understand various design and implementation measurement techniques.

This semester is based on the teaching methodology following three cardinal components:

 Concept Class Session

 Directed Learning Class

Student Learning Outcomes:

Clearly written student learning outcomes are the foundation upon which effective courses are designed.
Outcomes inform both the ways students are evaluated in a course and the way a course will be organized.
Effective learning outcomes are student-centered, measurable, concise, meaningful, achievable and outcome-
based (rather than task-based). The course contents are designed for those who are keen on getting themselves
a career in the field of Mechanical engineering, specifically for those who want to be involved in the design
and implementation of automation in manufacturing industries.
At the end of the course, the students will be able to:
 Understand FPGA Architecture: Explain the architecture and fundamental components of Field-
Programmable Gate Arrays (FPGAs).
 Develop HDL Code: Write and debug hardware description language (HDL) code, such as VHDL or
Verilog, for designing digital circuits.
 Implement Digital Designs: Implement digital systems and designs on FPGA hardware, including
combinational and sequential circuits.
 Design State Machines: Create and optimize finite state machines (FSMs) for control logic in digital
systems.
 Interface with Peripheral Devices: Interface FPGAs with various peripheral devices such as sensors,
memory modules, and communication interfaces.

Optimize Designs Apply optimization techniques to improve the performance, area, and power
consumption of FPGA-based designs

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CO/PO MAPPING:

Mapping of Courses Outcomes with Programme Outcomes:

(1/2/3 indicates strength of correlation) 3-Strong, 2-Medium, 1-Week

Programme Outcomes (POs)

COs
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2

CO1 3 3 3 2 - - - - 2 - - 3 3 3

CO2 3 3 3 2 - - - - 2 - - - 3 3

CO3 3 3 3 - - - - - - - - - 3 3

CO4 3 3 3 2 - - - - - - - 3 3 3

CO5 3 3 3 2 - - - - 2 - - 3 3 3

* For Entire Course, PO & PSO Mapping

POs & PSO REFERENCE:

PO Engineering Knowledge PO7 Environment & Sustainability PSO1 Professional Skills
1
PO Problem Analysis PO8 Ethics PSO2 Problem-Solving Skills
2
PO Design & Development PO9 Individual & Team Work PSO3 Successful Career and
3 Entrepreneurship
PO Investigations PO10 Communication Skills
4
PO Modern Tools PO11 Project Mgt. & Finance
5
PO Engineer & Society PO12 Life Long Learning
6

UNIT WISE HOURS ALLOCATION

Course Concept Class Dir. Learning Class Total
Hrs. Hrs. Hrs.
Unit - 1 7 2 9
Unit - 2 7 2 9
Unit - 3 7 2 9
Unit - 4 7 2 9
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 Unit - 5 7 2 9
Total 35 10 45

I. CONCEPT CLASS

LESSON PLAN

UNIT V Design Applications 09

Counter Examples: Fast Video Controller, Position Tracker for a Robot Manipulator, Design
Counters with ACT devices, Designing Adders and Accumulators with the ACT architecture.

Objective: Gain the knowledge of design applications of FPGA

Lecture
Sl. Topics to be Method Proposed notes- Teaching
Time Ref
No. covered date Page Method
Number

Counter
Examples:
Fast Video 10/09/24 10-13
1,2,3 Controller 3 2 L/PPT
CC 11/09/24
Position Tracker
for a Robot
Manipulator

Design Counters 11/09/24

4,5,6 CC 3 13-18 2 L/PPT
with ACT devices 12/09/24

Designing Adders 14/09/24

and Accumulators
5,6,7 CC 3 18/09/24 19-23 2 L/PPT
with the ACT
architecture 19/09/24

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 UNIT-V
1. TECHNICAL TERMS

S.NO Technical Terms Literal Meaning Technical Meaning

1. Programming File It contain the instructions and The file that contains the information
data required for a computer needed to program the FPGA, often in
program to run a specific format compatible with the
FPGA manufacturer's programming
tools.

2. I/O Blocks It is used for communication Its provides a programmable,

between the problem program unidirectional or
and the system. bidirectional interface between a
package pin and the FPGA’s internal
logic, supporting a wide variety of
standard interface
3. Programming set of programming tools
A set of software tools provided
Toolchain that are used to perform a
by the FPGA manufacturer to
complex software generate the programming
development task or to bitstream and facilitate the
create a software product. programming process.

4. Decommissioning The final phase in the life The process of permanently disabling
cycle of an energy installation or erasing the programmed
covering all activities from configuration of an anti-fuse FPGA, if
shutdown and removal of necessary.
equipment and material to
environmental restoration of
the site.

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S.No Time Structure
1. 2mins Attendance Fast
Video
2. 2mins Pranayama
Design application with FPGA
3.
3mins What is VRAM control?
Define multiplexer.
4. 5mins What is meant by robot manipulator?
How the DMA controller represents?
5. 35mins Fast Video Controller
Position Tracker for a Robot Manipulator
6. 3mins

How the throughput is achieved?

7. 2mins What is the resolution of the system?

8. 3mins Summarizing
Introduction to Designing Adders and Accumulators
Controller
Position Tracker for a Robot Manipulator

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 Fast Video Controller

Seventy Megahertz Video Controller.

Figure shows a block diagram of a video controller for a full-page high- resolution display. The FPGA is required to
control access to the video RAM, format the video data and generate control signals for the video monitor. Due to the
high resolution, the system is required to run at a 70 MHz rate. The high throughput is achieved by heavy pipelining,
which is supported by the XC3000 CLB structure in which every logic block is followed by a flip-flop. To achieve the
high performance, the logic was partitioned manually then placed and routed automatically. The placement and routing
were done incrementally, with the f critical paths were placed and routed.This application was designed and debugged
as successive prototypes in an XC3030 device, then put into production in an XC3020 device. The additional space in
the XC3030 prototype device contained on-chip debugging logic, electronic "scaffolding."

A Position Tracker For a Robot Manipulator

Robot manipulator positions are tracked by counting the number of times an indicator has passed in front of a sensor. A
manipulator with many degrees of freedom requires many sensors

Robot Manipulator Position Tracker

and position counters. The counters need not run fast, but they must loadable; they must be able to count both up and
down; and the system must be able to set and read the counts, the position of the manipulator, without interrupting the
count degrees of freedom. The range of motion of the arm and the position resolution require a 32-bit position register

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and counter for each degree of freedom. The design was implemented in two XC3090 FPGAs, each one implementing
eight 32-bit loadable up/down counters. The position registers are in the XC3090's flip- flops, and the counters are
implemented in lookup tables. Horizontal three-state lines give access to the position count registers. The position
registers can be independently addressed to be read and written by the robot controller at a 30 MHz data rate. Each
counter has its own up/down count signals and can count at. 8 MHz. Each of the XC3090s contains over eight thousand
gates of logic.

A Fast DMA Controller

Figure 5.3 shows a block diagram of a 16-channel DMA controller. The controller supports round-robin or priority channel
selection with pipelined channel arbitration.

It works with byte, word or long word transfers with separate 32-bit transfer count and address registers for each channel.
The controller interfaces to 16-bit or 32- bit data busses and supports 20 million transfers per second, up to 80 MB/sec.

Figure 5.4 shows the block diagram of the DMA controller in an XC4008 FPGA.
Registers and internal buffers use the CLB RAM configuration. Data and address sequencers use the high-speed
arithmetic. Wide data busses run horizontally across the chip on three-state lines. The control logic for sequencing and
DRAM interface is implemented as random logic on the same IC. The DMA controller represents approximately 7000
gates of logic and is implemented in about 200 CLBs, the synthesized netlist.

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 Figure 5.3. High-Speed DMA Controller Block Diagram.

Figure 5.4. High-Speed DMA Controller Layout

The symbol IOs correspond to those defined in the PALASM file. It is marked with a property indicating
that the netlist was synthesized and is to be found in a separate directory. When the top-level design is
compiled, the schematic and the synthesized netlists will be integrated into a single file.

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The ACTMAP tool also generates a netlist in the format of the users CA tools which may be used to
simulate and verify the synthesized logic either alone or interacting with other logic in the design.
Schematic generators may be used to view the synthesis results.

Design Counters with ACT devices

S.No Time Structure
1. 2mins Attendance
2. 2mins Pranayama
Design application with FPGA
3. Fast Video Controller
3mins
Position Tracker for a Robot Manipulator

4. 5mins What is meant by ACT devices?

How the counter works?
5. 35mins Design Counters with ACT devices

6. 3mins

How the throughput is achieved?

7. 2mins What is the resolution of the system?

8. 3mins Summarizing
Introduction to Designing Adders and Accumulators

Design Counters with ACT devices

Perhaps the most common digital logic function used is the synchronous binary counter. Regardless of
the technology employed to implement counters, they are found in every type of application. The
following describes some of the techniques for designing counters, or modifying a counters in the Act and
Act soft macro libraries.The functional requirements of the counter determine the approach to be taken
in its design. Most applications minimally require synchronous counters with an asynchronous reset.A
simple binary counter with reset is shown in Figure 5.5. The least significant bit uses an inverting flip-
flop so it toggles without additional logic. Whenever counter output polarity is flexible, or parallel
flip-flops are warranted by fan-out macro bubbled Is to reduce module count and levels of logic.In the
simple counter, as in most types of counters, the biggest design concern is propagating flip-flop
outputs to higher bits. For Act1-based designs like the simple counter example, bits higher than eight
require another level of combinatorial logic. Combinatorial levels required for the simple counter are:
two for up to nine bits, three for ten to 33 bits.A loadable counter appears in Figure 3.6.10. The
multiplexor flip-flip is used where one input provides the loaded data and the other the count data.
The multiplexor select line is controlled by the counter load line. The Act modules offer more logic
integration than Act modules. In the sample design of Figure 3.6.11 you can see how to construct a
six-bit loadable counter with only one level of combinatorial logic between flip-flops. (In the counter
design described below a ten-bit counter with one level of combinatorial logic may be built using a
14
multiplexed flip-flop with a gated select input.) The design has a 4:1 multiplexor driving the data
input of each flip-flop. The multiplexor macro and the flip-flop are combinable into a single S-module
by the ALS software providing good integration and performance.

Figure 5.5. Act Five Bit Binary Counter

The select lines on the multiplexor are operated by the load control (S1) and by the count enable and
carry from the lower order bits (SO). The multiplexor data inputs are used for data to be loaded, held,
or incremented. The fourth multiplexor data input can be used as a second data input, or a
synchronous set counter design considerations should be evaluated from the perspective of the device-
level design and how the counter is used in it. For example, if some counter outputs may be active low
or if additional modules are used for redundant larger counters may be designed without additional
logic levels using five-input gates. Such decisions should consider the implications for module count
and fan- out as detailed below. enable will serve to illustrate some of the considerations designers
should be aware of when designing large counters in Act FPGA designs. The functional description
for the counter appears in Table 8

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Figure 5.6. Act l Loadable Counter

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 Table 8 : Counter Function

Figure 5.7. Act Six-Bit Loadable Counter Example

The counter design makes extensive use (bits O through 5) of a 4:1 multiplexor driving a flip-flop as
depicted in Figure 5.6C-modules are used as AND-EXORs bring the count enable (CE) to the
multiplexor via the select line in bits Q3 and above.
For the bits Q6 through Q15, an S-module macro with both a 4:1 multiplexor and an OR gate driving
one select line is used to allow for more parallel propagation of the lower bits. Figure 5.7 shows the
implementation of the most significant bit of the counter

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.

18
The S-module OR gate is used as a two-input NAND with active-low inputs which are, in turn, driven
by NAND gates to propagate the lower bits and the count enable.

The active-low output of the built-in two-input gate (OR used as a NAND) is adiusted for by shifting
the position of the multiplexor data inputs.

Most four-input gates are implemented with a single C-module, but a four-input NAND with no
bubbled inputs requires two modules. The limitation is avoided by using a NAND with a bubbled
input. The count enable is active low, so it may be used to drive a bubbled input on a gate. Active-low
counter bits are used to drive other bubbled gate inputs.

The Q0 inversion toggles the flip-flop. A toggle flip-flop could have been used instead of a D flip-
flop, but it could not have been combined with the multiplexor into a single S-module. Moreover, the
inverter output is available as a resource to share the fan-out load with the flip-flop and to allow the
use of bubbled inputs on gates whenever it is desirable.

It could be argued that the use of the inverted output to drive gates causes the lower level bits to use
two levels of combinatorial logic when it is not necessary. For a design of ten bits or less the point
would be valid because no path requires more than one combinatorial level. In the example design,
however, two levels are already required by the upper bits and the improvement in fan-out from the
use of the inverter output at no additional cost in module count makes the practice worthwhile.

Designing Adders and Accumulators with the ACT architecture

S.No Time Structure
1. 2mins Attendance
2. 2mins Pranayama
Fast Video Controller
3.
3mins Robot Manipulator

4. 5mins Introduction to Adders and Accumulators

Designing Adders
5. 35mins
Designing Accumulators with the ACT architecture
6. 3mins

7. 2mins How many module are required to perform an addition?

State the applications of counter in ACT architecture
8. 3mins Summarizing

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 Designing Adders and Accumulators with the ACT Architecture

Many designers implement adders using carry-propagation techniques. The multiplexed-based Act
and Act combinatorial module (C-module) allows for the more efficient carry-select design. This
method partitions the add function into blocks that perform two additions simultaneously on a number
of bits of the two operands.

The two additions are performed simultaneously except that one assumes a carry- in and one has no
carry-in. The two sums are input to a 2:1 multiplexors, one for each bit pair. The carry line, from the
low bits to the high bits, is used to select the appropriate sum for each block.
The ACT architecture lends itself well to implementing adders of various sizes using the carry-select
technique. A sample design for a 16-bit adder, as shown in Figure 5.9will be used to illustrate adder
design.

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 Figure 5.9. 18-Bit Counter, Fanout Reduced Design

The way to balance the levels of logic modules for the sum blocks with the carry is to partition
the sum blocks. This partition is based on the logic levels required for the sums and the levels for the
carry between sums. The size of the partitions varies with width of the data. The Act library contains
some powerful hard macros that are used to shorten the levels of logic required for generating sums and
carries. The description of the sample design will illustrate the use of the macros.

21
 Figure 5.10. Act Carry-Select Adder Example

For the 16-bit adder, the optimal organization is to perform two two-bit additions on the least four significant bits
with the remaining higher order bits broken into four sections of three bits each. In the top-level schematic the
addition logic o levels of the design hierarchy described in the next section.

The Act library includes two two-level carry hard macros. One macro generates a carry for the two bit
pairs assuming the carry-in is true and the other assumes it is false. The latter macro may be seen at
the bottom of Figure 3.6.18 making the carry for the least two bits.

22
The carry macro output drives the select line for the 2: 1 multiplexors for sum bits two and three. It
also drives the select line on the cascade multiplexor. The cascade multiplexor is a special Act hard
macro that can propagate two levels of carry. The macro is depicted in Figure 5.11 and has five
inputs. The top multiplexor inputs select the most significant sum or carry. The lower three inputs
drive logic that implements a simplified form of a 2:1 multiplexor.

Figure 5.11. Cascade Multiplexor Macro

A fully implemented 2:1 cascade multiplexor does not map into the Act module efficiently, but the
full functionality is not required in a carry select adder. A simplified version of the cascade
multiplexor that maps into a C-module or that can be combined with a flip-flop in an S-module is
available. consisting of only a two-input OR driving one input of a two-input AND. The two OR gate
inputs are driven by the carry output from the next lower sum block assuming no carry-in and the
carry in from the rest of the lower bits of the adder. The remaining AND input is the carry from the
sum block which assumes a carry- in.The logic is correct for a carry select adder because if the
assume-no-carry-in input is true (meaning that a carry was generated within that sum block), then
the assume-carry-in is always true (since it equals the false plus one) which completes the AND
function.If the carry from the lower bits is true (meaning a carry is propagated to the sum block),
then we complete the AND if the assume-carry is true.

23
The schematic for the three-bit adder block appears in Figure 5.12 The adder

Figure 5.12. Three Bit Adder Block

requires thirteen logic modules to generate the three sum and carry pairs. All the output paths are
two levels of logic or less. The two carries for the three bits come from two-level carry hard macros
driving a three-bit majority macro. All the sums are generated from exclusive OR or NOR gates.

The optimal design for a carry select adder depends on the number bits to be added.

As mentioned previously, the number of bits in a block is a function of the overall adder size. For Act
adders of two and three bits, the design shown in Figure 3.6.20 is attractive because the two-level
carry macro allows for delays to be two levels or less.

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 Figure 5.13. Another Adder Example

The above design uses ACT library single bit two-module hard macros. The Actel library
contains several such two-module adder macros with both a sum and a carry output.

The carry output goes through one module delay and the sum output two module delays.
The carry propagates through the chain in four levels in the example so that all the sum
bits are stable when the carry ripple is complete.

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23