D01. Lexical Resourses

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30 DAYS CHALLENGE

VERILOG CODING : DAY 1


➢ Verilog is a hardware description language used for electronic design.
➢ some key points regarding its lexical conventions

1. Case Sensitivity:
• Verilog is case sensitive.
• Keywords, system tasks, and system functions are in lowercase, while user-defined identifiers are case sensitive.

module caseExample;
input A;
output B;
assign B = a; // Error, 'a' is different from 'A'
due to case sensitivity.
endmodule

2. Whitespace:
• Verilog ignores spaces, tabs, and line breaks, except to separate tokens.
• Whitespace is used to make the code more readable.

module whitespaceExample;

input A;

output B;

assign B = A + 1; // Whitespace is used for


readability.

endmodule

3. Comments:
• Comments are denoted by double slashes `//` for single-line comments.
• `/ * */` for multi-line comments.
• They are used for documentation and explanations within the code.

module commentsExample;

// This is a single-line comment

/* This is

a multi-line comment */

input A;

output B;

assign B = A + 1;

endmodule
4. Identifiers:
• Identifiers in Verilog are used for naming modules, variables, and other elements.
• They must start with a letter or an underscore and can contain letters, digits, and underscores.

module identifierExample;

input data_in;

output data_out;

wire clk;

reg [7:0] counter;

assign data_out = data_in & counter;

endmodule

5. Keywords:
• Verilog has a set of reserved keywords like module, input, output, and always, which have special meanings in the language.

module keywordExample;

input A, B;

output Y;

assign Y = A & B; // 'input', 'output', and


'assign' are keywords.

endmodule

6. Literals:

• Verilog supports different literal types, including binary, octal, decimal, and hexadecimal.
• For example, 8'hFF represents an 8-bit hexadecimal value.

module literalExample;

reg [3:0] binary = 4'b1101;

reg [3:0] octal = 4'o75;

reg [3:0] decimal = 4'd13;

reg [3:0] hexadecimal = 4'hD;

endmodule
7. Operators:
• Verilog uses various operators like +, -, *, /, ==, !=, &&, ||, etc., for arithmetic and logical operations.

module operatorExample;

reg A = 1;

reg B = 0;

wire C;

assign C = A | B; // '|' is a bitwise OR


operator.

endmodule

8. Strings:

• Strings are enclosed in double quotes, e.g., "Hello, World".

module stringExample;

initial

$display("Hello, World");

initial

$display("Verilog %s", "visionaries!"); // Strings are


enclosed in double quotes.

endmodule

9. Numbers:
• Verilog supports both integer and real numbers.
• Real numbers include decimal points or an exponent notation.

module numberExample;

reg [7:0] integer = 8;

reg realNum = 3.14159;

endmodule

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