MCP4802

MCP4802/4812/4822
8/10/12-Bit Dual Voltage Output Digital-to-Analog Converter

with Internal VREF and SPI Interface
Features Description
• MCP4802: Dual 8-Bit Voltage Output DAC The MCP4802/4812/4822 devices are dual 8-bit, 10-bit
• MCP4812: Dual 10-Bit Voltage Output DAC and 12-bit buffered voltage output Digital-to-Analog
• MCP4822: Dual 12-Bit Voltage Output DAC Converters (DACs), respectively. The devices operate
from a single 2.7V to 5.5V supply with SPI compatible
• Rail-to-Rail Output
Serial Peripheral Interface.
• SPI Interface with 20 MHz Clock Support
The devices have a high precision internal voltage
• Simultaneous Latching of the Dual DACs reference (VREF = 2.048V). The user can configure the
with LDAC pin full-scale range of the device to be 2.048V or 4.096V by
• Fast Settling Time of 4.5 µs setting the Gain Selection Option bit (gain of 1 of 2).
• Selectable Unity or 2x Gain Output Each DAC channel can be operated in Active or
• 2.048V Internal Voltage Reference Shutdown mode individually by setting the Configuration
• 50 ppm/°C VREF Temperature Coefficient register bits. In Shutdown mode, most of the internal
circuits in the shutdown channel are turned off for power
• 2.7V to 5.5V Single-Supply Operation
savings and the output amplifier is configured to present
• Extended Temperature Range: -40°C to +125°C a known high resistance output load (500 k typical.
The devices include double-buffered registers,
Applications allowing synchronous updates of two DAC outputs
• Set Point or Offset Trimming using the LDAC pin. These devices also incorporate a
Power-on Reset (POR) circuit to ensure reliable power-
• Sensor Calibration
up.
• Precision Selectable Voltage Reference
The devices utilize a resistive string architecture, with
• Portable Instrumentation (Battery-Powered) its inherent advantages of low DNL error, low ratio
• Calibration of Optical Communication Devices metric temperature coefficient and fast settling time.
These devices are specified over the extended
Related Products(1) temperature range (+125°C).
The devices provide high accuracy and low noise
Voltage performance for consumer and industrial applications
DAC No. of
P/N Reference where calibration or compensation of signals (such as
Resolution Channels
(VREF) temperature, pressure and humidity) are required.
MCP4801 8 1 The MCP4802/4812/4822 devices are available in the
MCP4811 10 1 PDIP, SOIC and MSOP packages.
MCP4821 12 1 Internal
(2.048V)
Package Types
MCP4802 8 2
8-Pin PDIP, SOIC, MSOP
MCP4812 10 2
MCP4822 12 2 VDD 1 8 VOUTA
MCP48X2
MCP4901 8 1 CS 2 7 VSS
MCP4911 10 1 SCK 3 6 VOUTB
MCP4921 12 1 SDI 4 5 LDAC
External
MCP4902 8 2
MCP4802: 8-bit dual DAC
MCP4912 10 2 MCP4812: 10-bit dual DAC
MCP4922 12 2 MCP4822: 12-bit dual DAC
Note 1: The products listed here have similar
AC/DC performances.
 2010 Microchip Technology Inc. DS22249A-page 1

MCP4802/4812/4822
Block Diagram
CS SDI SCK LDAC
VDD
Interface Logic Power-on
Reset
VSS
Input Input
Register A Register B
2.048V
VREF
DACA DACB
Register Register
String String
DACA DACB
Gain Gain
Logic Output Logic
Op Amps
Output
Logic
VOUTA VOUTB
DS22249A-page 2  2010 Microchip Technology Inc.

MCP4802/4812/4822
1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
CHARACTERISTICS This is a stress rating only and functional operation of
the device at those or any other conditions above those
Absolute Maximum Ratings † indicated in the operational listings of this specification
VDD....................................................................... 6.5V is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
All inputs and outputs .......... VSS – 0.3V to VDD + 0.3V
Current at Input Pins ......................................... ±2 mA
Current at Supply Pins .................................... ±50 mA
Current at Output Pins .................................... ±25 mA
Storage temperature .......................... -65°C to +150°C
Ambient temp. with power applied ..... -55°C to +125°C
ESD protection on all pins 4 kV (HBM), 400V (MM)
Maximum Junction Temperature (TJ)................+150°C
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V,
Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85°C. Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Power Requirements
Input Voltage VDD 2.7 — 5.5 V
Input Current IDD — 415 750 µA All digital inputs are grounded,
all analog outputs (VOUT) are
unloaded. Code = 0x000h
Software Shutdown Current ISHDN_SW — 3.3 6 µA
Power-on Reset Threshold VPOR — 2.0 — V
DC Accuracy
MCP4802
Resolution n 8 — — Bits
INL Error INL -1 ±0.125 1 LSb
DNL DNL -0.5 ±0.1 +0.5 LSb Note 1
MCP4812
INL Error INL -3.5 ±0.5 3.5 LSb
DNL DNL -0.5 ±0.1 +0.5 LSb Note 1
MCP4822
INL Error INL -12 ±2 12 LSb
DNL DNL -0.75 ±0.2 +0.75 LSb Note 1
Offset Error VOS -1 ±0.02 1 % of FSR Code = 0x000h
Offset Error Temperature VOS/°C — 0.16 — ppm/°C -45°C to +25°C
Coefficient — -0.44 — ppm/°C +25°C to +85°C
Gain Error gE -2 -0.10 2 % of FSR Code = 0xFFFh,
not including offset error
Gain Error Temperature G/°C — -3 — ppm/°C
Coefficient
Note 1: Guaranteed monotonic by design over all codes.
2: This parameter is ensured by design, and not 100% tested.

MCP4802/4812/4822
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V,
Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85°C. Typical values are at +25°C.
Internal Voltage Reference (VREF)
Internal Reference Voltage VREF 2.008 2.048 2.088 V VOUTA when G = 1x and
Code = 0xFFFh
Temperature Coefficient VREF/°C — 125 325 ppm/°C -40°C to 0°C
(Note 2) — 0.25 0.65 LSb/°C -40°C to 0°C
— 45 160 ppm/°C 0°C to +85°C
— 0.09 0.32 LSb/°C 0°C to +85°C
Output Noise (VREF Noise) ENREF — 290 — µVp-p Code = 0xFFFh, G = 1x
(0.1-
10 Hz)
Output Noise Density eNREF — 1.2 — µV/Hz Code = 0xFFFh, G = 1x
(1 kHz)
eNREF — 1.0 — µV/Hz Code = 0xFFFh, G = 1x
(10 kHz)
1/f Corner Frequency fCORNER — 400 — Hz
Output Amplifier
Output Swing VOUT — 0.01 to — V Accuracy is better than 1 LSb for
VDD – 0.04 VOUT = 10 mV to (VDD–40 mV)
Phase Margin PM — 66 — Degree CL= 400 pF, RL = 
(°)
Slew Rate SR — 0.55 — V/µs
Short Circuit Current ISC — 15 24 mA
Settling Time tSETTLING — 4.5 — µs Within 1/2 LSb of final value from
1/4 to 3/4 full-scale range
Dynamic Performance (Note 2)
DAC-to-DAC Crosstalk — <10 — nV-s
Major Code Transition Glitch — 45 — nV-s 1 LSb change around major carry
(0111...1111 to
1000...0000)
Digital Feedthrough — <10 — nV-s
Analog Crosstalk — <10 — nV-s

MCP4802/4812/4822
ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE

Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x,
RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Power Requirements
Input Voltage VDD 2.7 — 5.5 V
Input Current IDD — 440 — µA All digital inputs are grounded,
Input Curren all analog outputs (VOUT) are
unloaded. Code = 0x000h.
Software Shutdown Current ISHDN_SW — 5 — µA
Power-On Reset threshold VPOR — 1.85 — V
DC Accuracy
MCP4802
INL Error INL — ±0.25 — LSb
DNL DNL — ±0.2 — LSb Note 1
MCP4812
INL Error INL — ±1 — LSb
MCP4822
INL Error INL — ±4 — LSb
Offset Error VOS — ±0.02 — % of FSR Code = 0x000h
Offset Error Temperature VOS/°C — -5 — ppm/°C +25°C to +125°C
Coefficient
Gain Error gE — -0.10 — % of FSR Code = 0xFFFh,
not including offset error
Gain Error Temperature G/°C — -3 — ppm/°C
Coefficient
Internal Voltage Reference (VREF)
Internal Reference Voltage VREF — 2.048 — V VOUTA when G = 1x and
Code = 0xFFFh
Temperature Coefficient VREF/°C — 125 — ppm/°C -40°C to 0°C
(Note 2) — 0.25 — LSb/°C -40°C to 0°C
— 45 — ppm/°C 0°C to +85°C
— 0.09 — LSb/°C 0°C to +85°C
Output Noise (VREF Noise) ENREF — 290 — µVp-p Code = 0xFFFh, G = 1x
(0.1 – 10 Hz)
Output Noise Density eNREF — 1.2 — µV/Hz Code = 0xFFFh, G = 1x
(1 kHz)
eNREF — 1.0 — µV/Hz Code = 0xFFFh, G = 1x
(10 kHz)
1/f Corner Frequency fCORNER — 400 — Hz

MCP4802/4812/4822
ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x,
RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Output Amplifier
Output Swing VOUT — 0.01 to — V Accuracy is better than 1 LSb
VDD – 0.04 for
VOUT = 10 mV to (VDD –
40 mV)
Phase Margin PM — 66 — Degree (°) CL= 400 pF, RL = 
Slew Rate SR — 0.55 — V/µs
Short Circuit Current ISC — 17 — mA
Settling Time tSETTLING — 4.5 — µs Within 1/2 LSb of final value
from 1/4 to 3/4 full-scale range
Dynamic Performance (Note 2)
DAC-to-DAC Crosstalk — <10 — nV-s
Major Code Transition — 45 — nV-s 1 LSb change around major
Glitch carry (0111...1111 to
1000...0000)
Digital Feedthrough — <10 — nV-s
Analog Crosstalk — <10 — nV-s
AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)

Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 to +125°C.
Typical values are at +25°C.
Schmitt Trigger High-Level VIH 0.7 VDD — — V
Input Voltage
(All digital input pins)
Schmitt Trigger Low-Level VIL — — 0.2 VDD V
Input Voltage
(All digital input pins)
Hysteresis of Schmitt Trigger VHYS — 0.05 VDD — V
Inputs
Input Leakage Current ILEAKAGE -1 — 1 A LDAC = CS = SDI = SCK =
VDD or VSS
Digital Pin Capacitance CIN, — 10 — pF VDD = 5.0V, TA = +25°C,
(All inputs/outputs) COUT fCLK = 1 MHz (Note 1)
Clock Frequency FCLK — — 20 MHz TA = +25°C (Note 1)
Clock High Time tHI 15 — — ns Note 1
Clock Low Time tLO 15 — — ns Note 1
CS Fall to First Rising CLK tCSSR 40 — — ns Applies only when CS falls with
Edge CLK high. (Note 1)
Data Input Setup Time tSU 15 — — ns Note 1
Data Input Hold Time tHD 10 — — ns Note 1
SCK Rise to CS Rise Hold tCHS 15 — — ns Note 1
Time
Note 1: This parameter is ensured by design and not 100% tested.

MCP4802/4812/4822
AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)
Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 to +125°C.
Typical values are at +25°C.
CS High Time tCSH 15 — — ns Note 1
LDAC Pulse Width tLD 100 — — ns Note 1
LDAC Setup Time tLS 40 — — ns Note 1
SCK Idle Time before CS Fall tIDLE 40 — — ns Note 1
Note 1: This parameter is ensured by design and not 100% tested.
tCSH
CS
tIDLE
tCSSR tHI tLO tCHS
Mode 1,1
SCK Mode 0,0
tSU tHD
SDI
MSb in LSb in
LDAC
tLS tLD
FIGURE 1-1: SPI Input Timing Data.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Temperature Ranges
Specified Temperature Range TA -40 — +125 °C
Operating Temperature Range TA -40 — +125 °C Note 1
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-MSOP JA — 211 — °C/W
Thermal Resistance, 8L-PDIP JA — 90 — °C/W
Thermal Resistance, 8L-SOIC JA — 150 — °C/W
Note 1: The MCP4802/4812/4822 devices operate over this extended temperature range, but with reduced
performance. Operation in this range must not cause TJ to exceed the maximum junction temperature
of +150°C.

MCP4802/4812/4822
NOTES:

MCP4802/4812/4822
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
0.3 5
Ambient Temperature
4
0.2 125C 85 25
3
0.1 2
DNL (LSB)
INL (LSB)
1
0 0
-1
-0.1
-2
-0.2 -3
-4
-0.3 -5
0 1024 2048 3072 4096 0 1024 2048 3072 4096
Code (Decimal) Code (Decimal)
FIGURE 2-1: DNL vs. Code (MCP4822). FIGURE 2-4: INL vs. Code and
Temperature (MCP4822).
0.2 2.5
2
Absolute INL (LSB)
0.1
DNL (LSB)
1.5
0
1
-0.1 0.5
-0.2 0
0 1024 2048 3072 4096 -40 -20 0 20 40 60 80 100 120
Code (Decimal) 125C 85C 25C Ambient Temperature (ºC)
FIGURE 2-2: DNL vs. Code and FIGURE 2-5: Absolute INL vs.
Temperature (MCP4822). Temperature (MCP4822).
0.0766 2
0.0764
Absolute DNL (LSB)
0.0762 0
0.076
INL (LSB)
0.0758 -2
0.0756
0.0754 -4
0.0752
0.075 -6
-40 -20 0 20 40 60 80 100 120 0 1024 2048 3072 4096
Ambient Temperature (ºC) Code (Decimal)
FIGURE 2-3: Absolute DNL vs. FIGURE 2-6: INL vs. Code (MCP4822).
Note: Single device graph for illustration of 64
code effect.

MCP4802/4812/4822
0.3 0.6
o
- 40 C - 40oC
0.5
0.2
0.4 o
85 C
0.1 0.3
INL (LSB)
DNL (LSB)
0.2
0 0.1
0
-0.1
-0.1 125oC
25oC
-0.2 -0.2
+25oC to +125oC
-0.3
-0.3 0 32 64 96 128 160 192 224 256
0 128 256 384 512 640 768 896 1024
Code Code
FIGURE 2-7: DNL vs. Code and FIGURE 2-10: INL vs. Code and
Temperature (MCP4812). Temperature (MCP4802).
2.050
1.5 2.049
2.048
Full Scale VOUT (V)

1
2.047
0.5
85oC 2.046
0 2.045 VDD: 4V
INL (LSB)
VDD: 3V
-0.5 2.044 VDD: 2.7V
-1 2.043
-1.5 2.042
-2 25oC 2.041
o
- 40 C 2.040
-2.5 o
125 C -40 -20 0 20 40 60 80 100 120
-3
Ambient Temperature (°C)
0 128 256 384 512 640 768 896 1024
Code
FIGURE 2-11: Full-Scale VOUTA vs.
FIGURE 2-8: INL vs. Code and Ambient Temperature and VDD. Gain = 1x.
0.15 4.100
o o
Temperature: - 40 C to +125 C
0.1 4.096
Full Scale VOUT (V)
0.05 4.092
DNL (LSB)
0 VDD: 5.5V
4.088
34
VDD: 5V
-0.05 4.084
-0.1 4.080
-0.15 4.076
0 32 64 96 128 160 192 224 256 -40 -20 0 20 40 60 80 100 120
Code Ambient Temperature (°C)
FIGURE 2-9: DNL vs. Code and FIGURE 2-12: Full-Scale VOUTA vs.
Temperature (MCP4802). Ambient Temperature and VDD. Gain = 2x.

MCP4802/4812/4822
100
1.E-04 25
Output Noise Voltage Density
20
Occurrence
1.E-05
10
15
(µV/Hz)
10
1
1.E-06
5
0
0.1
1.E-07
380
385
390
395
400
405
410
415
420
425
430
435
440
0.1
1E-1 1
1E+0 10
1E+1 100
1E+2 1k
1E+3 10k
1E+4 100k
1E+5
Frequency (Hz) IDD (µA)
FIGURE 2-13: Output Noise Voltage FIGURE 2-16: IDD Histogram (VDD = 2.7V).
Density (VREF Noise Density) vs. Frequency.
Gain = 1x.
1.E-02
10.0 22
20
Output Noise Voltage (mV)
18
16
Occurrence
1.E-03
1.00 Eni (in VP-P) 14
12
10
8
0.10
1.E-04 6
Eni (in VRMS) 4
2
Maximum Measurement Time = 10s 0
0.01
1.E-05
385
390
395
400
405
410
415
420
425
430
435
100
1E+2 1k
1E+3 10k
1E+4 100k
1E+5 1M
1E+6 IDD (µA)
Bandwidth (Hz)
FIGURE 2-14: Output Noise Voltage FIGURE 2-17: IDD Histogram (VDD = 5.0V).
(VREF Noise Voltage) vs. Bandwidth. Gain = 1x.
340
5.5V
320 5.0V
4.0V
300 3.0V
2.7V
280 VDD
IDD (µA)
260
240
220
200
180
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (°C)
FIGURE 2-15: IDD vs. Temperature and VDD.

MCP4802/4812/4822
4 4 VDD
5.5V
3.5 5.0V 5.5V

3.5
VIN Hi Threshold (V)

5.0V
3 3
ISHDN_SW (µA)
4.0V
2.5 2.5 4.0V

3.0V
2 2.7V 2
V DD 3.0V
1.5 1.5 2.7V
1 1
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC) Ambient Temperature (ºC)
FIGURE 2-18: Software Shutdown Current FIGURE 2-21: VIN High Threshold vs.
vs. Temperature and VDD. Temperature and VDD.
1.6
0.11 VDD
1.5
VIN Low Threshold (V)

0.09 5.5V
1.4
Offset Error (%)
0.07 5.0V
1.3
0.05
5.5V 1.2
0.03 4.0V
VDD 1.1
0.01 1
5.0V 3.0V
-0.01 0.9
4.0V 2.7V
3.0V
-0.03 2.7V 0.8
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
FIGURE 2-19: Offset Error vs. Temperature FIGURE 2-22: VIN Low Threshold vs.
and VDD. Temperature and VDD.
-0.05
-0.1
VDD
-0.15
5.5V
Gain Error (%)
5.0V
-0.2 4.0V
3.0V
-0.25 2.7V
-0.3
-0.35
-0.4
-0.45
-0.5
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
FIGURE 2-20: Gain Error vs. Temperature

and VDD.

MCP4802/4812/4822
2.5 16
VDD 5.5V
2.25 5.0V
5.5V 15 4.0V
VIN_SPI Hysteresis (V)
IOUT_HI_SHORTED (mA)
3.0V
5.0V 2.7V
1.75 14
1.5 VDD
4.0V 13
1.25
1
3.0V 12
0.75 2.7V
0.5 11
0.25
0 10
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
FIGURE 2-23: Input Hysteresis vs. FIGURE 2-26: IOUT High Short vs.
Temperature and VDD. Temperature and VDD.
0.035 6.0
4.0V
0.033
5.0
VOUT_HI Limit (VDD-Y)(V)
0.031
VREF = 4.096V
0.029
4.0
Output Shorted to VDD
VOUT (V)
0.027
0.025 3.0V 3.0
0.023 2.7V
2.0
0.021 VDD
0.019 1.0
Output Shorted to VSS
0.017
0.015 0.0
-40 -20 0 20 40 60 80 100 120 0 2 4 6 8 10 12 14 16
Ambient Temperature (ºC) IOUT (mA)
FIGURE 2-24: VOUT High Limit FIGURE 2-27: IOUT vs. VOUT. Gain = 2x.
vs.Temperature and VDD.
0.0028 VDD
0.0026
VOUT_LOW Limit (Y-AVSS)(V)
0.0024 5.5V
0.0022 5.0V
0.0020
0.0018 4.0V
3.0V
0.0016 2.7V
0.0014
0.0012
0.0010
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
FIGURE 2-25: VOUT Low Limit vs.

Temperature and VDD.

MCP4802/4812/4822
VOUT
VOUT
SCK
LDAC LDAC
Time (1 µs/div) Time (1 µs/div)

FIGURE 2-28: VOUT Rise Time. FIGURE 2-31: VOUT Rise Time.
VOUT
VOUT
SCK
SCK
LDAC LDAC
Time (1 µs/div) Time (1 µs/div)

FIGURE 2-29: VOUT Fall Time. FIGURE 2-32: VOUT Rise Time Exit
Shutdown.
Ripple Rejection (dB)
VOUT
SCK
LDAC
Time (1 µs/div) Frequency (Hz)

FIGURE 2-30: VOUT Rise Time. FIGURE 2-33: PSRR vs. Frequency.

MCP4802/4812/4822
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE FOR MCP4802/4812/4822

MCP4802/4812/4822
Symbol Description
MSOP, PDIP, SOIC
1 VDD Supply Voltage Input (2.7V to 5.5V)
2 CS Chip Select Input
3 SCK Serial Clock Input
4 SDI Serial Data Input
5 LDAC Synchronization Input. This pin is used to transfer DAC settings
(Input Registers) to the output registers (VOUT)
6 VOUTB DACB Output
7 VSS Ground reference point for all circuitry on the device
8 VOUTA DACA Output
3.1 Supply Voltage Pins (VDD, VSS) 3.4 Serial Data Input (SDI)
VDD is the positive supply voltage input pin. The input SDI is the SPI compatible serial data input pin.
supply voltage is relative to VSS and can range from
2.7V to 5.5V. The power supply at the VDD pin should 3.5 Latch DAC Input (LDAC)
be as clean as possible for a good DAC performance.
It is recommended to use an appropriate bypass LDAC (latch DAC synchronization input) pin is used to
capacitor of about 0.1 µF (ceramic) to ground. An transfer the input latch registers to their corresponding
additional 10 µF capacitor (tantalum) in parallel is also DAC registers (output latches, VOUT). When this pin is
recommended to further attenuate high-frequency low, both VOUTA and VOUTB are updated at the same
noise present in application boards. time with their input register contents. This pin can be
tied to low (VSS) if the VOUT update is desired at the
VSS is the analog ground pin and the current return path
rising edge of the CS pin. This pin can be driven by an
of the device. The user must connect the VSS pin to a
external control device such as an MCU I/O pin.
ground plane through a low-impedance connection. If
an analog ground path is available in the application
Printed Circuit Board (PCB), it is highly recommended 3.6 Analog Outputs (VOUTA, VOUTB)
that the VSS pin be tied to the analog ground path or VOUTA is the DAC A output pin, and VOUTB is the DAC
isolated within an analog ground plane of the circuit B output pin. Each output has its own output amplifier.
board. The full-scale range of the DAC output is from
VSS to G* VREF, where G is the gain selection option
3.2 Chip Select (CS) (1x or 2x). The DAC analog output cannot go higher
than the supply voltage (VDD).
CS is the Chip Select input pin, which requires an
active-low to enable serial clock and data functions.
3.3 Serial Clock Input (SCK)

SCK is the SPI compatible serial clock input pin.

MCP4802/4812/4822
NOTES:

MCP4802/4812/4822
4.0 GENERAL OVERVIEW 1 LSb is the ideal voltage difference between two
successive codes. Table 4-1 illustrates the LSb
The MCP4802, MCP4812 and MCP4822 are dual calculation of each device.
voltage output 8-bit, 10-bit and 12-bit DAC devices,
respectively. These devices include rail-to-rail output TABLE 4-1: LSb OF EACH DEVICE
amplifiers, internal voltage reference, shutdown and Gain
reset-management circuitry. The devices use an SPI Device LSb Size
Selection
serial communication interface and operate with a sin-
gle supply voltage from 2.7V to 5.5V. MCP4802 1x 2.048V/256 = 8 mV
(n = 8) 2x 4.096V/256 = 16 mV
The DAC input coding of these devices is straight
binary. Equation 4-1 shows the DAC analog output MCP4812 1x 2.048V/1024 = 2 mV
voltage calculation. (n = 10) 2x 4.096V/1024 = 4 mV
MCP4822 1x 2.048V/4096 = 0.5 mV
EQUATION 4-1: ANALOG OUTPUT (n = 12) 2x 4.096V/4096 = 1 mV
VOLTAGE (VOUT)
4.0.1 INL ACCURACY
 2.048V  Dn 
V OUT -G
= ---------------------------------- Integral Non-Linearity (INL) error for these devices is
n
2 the maximum deviation between an actual code transi-
Where: tion point and its corresponding ideal transition point
once offset and gain errors have been removed. The
2.048V = Internal voltage reference two end points method (from 0x000 to 0xFFF) is used
Dn = DAC input code for the calculation. Figure 4-1 shows the details.
G = Gain selection A positive INL error represents transition(s) later than
= 2 for <GA> bit = 0 ideal. A negative INL error represents transition(s)
earlier than ideal.
= 1 for <GA> bit = 1
n = DAC Resolution
= 8 for MCP4802 INL < 0
= 10 for MCP4812 111
Actual
= 12 for MCP4822
110 Transfer
Function
101
The ideal output range of each device is:
• MCP4802 (n = 8) Digital 100
Input
(a) 0.0V to 255/256 * 2.048V when gain setting = 1x. Code 011 Ideal Transfer
(b) 0.0V to 255/256 * 4.096V when gain setting = 2x.
Function
• MCP4812 (n = 10) 010
(a) 0.0V to 1023/1024 * 2.048V when gain setting = 1x. 001

(b) 0.0V to 1023/1024 * 4.096V when gain setting = 2x.
000
• MCP4822 (n = 12) INL < 0
(a) 0.0V to 4095/4096 * 2.048V when gain setting = 1x.
(b) 0.0V to 4095/4096 * 4.096V when gain setting = 2x. DAC Output
FIGURE 4-1: Example for INL Error.

Note: See the output swing voltage specification in
Section 1.0 “Electrical Characteristics”.

MCP4802/4812/4822
4.0.2 DNL ACCURACY 4.1 Circuit Descriptions
A Differential Non-Linearity (DNL) error is the measure
of variations in code widths from the ideal code width. 4.1.1 OUTPUT AMPLIFIERS
A DNL error of zero indicates that every code is exactly The DAC’s outputs are buffered with a low-power,
1 LSb wide. precision CMOS amplifier. This amplifier provides low
offset voltage and low noise. The output stage enables
the device to operate with output voltages close to the
power supply rails. Refer to Section 1.0 “Electrical
111 Actual Characteristics” for the analog output voltage range
Transfer and load conditions.
110 Function
In addition to resistive load-driving capability, the
amplifier will also drive high capacitive loads without
101
oscillation. The amplifier’s strong outputs allow VOUT to
Digital 100 be used as a programmable voltage reference in a
Input Ideal Transfer system.
Code Function
011
4.1.1.1 Programmable Gain Block
010
The rail-to-rail output amplifier has two configurable
001 Wide Code, >1 LSb gain options: a gain of 1x (<GA> = 1) or a gain of 2x
(<GA> = 0). The default value for this bit is a gain
000 of 2 (<GA> = 0). This results in an ideal full-scale
Narrow Code, <1 LSb
output of 0.000V to 4.096V due to the internal
reference (VREF = 2.048V).
DAC Output
4.1.2 VOLTAGE REFERENCE
FIGURE 4-2: Example for DNL Error.
The MCP4802/4812/4822 devices utilize internal
4.0.3 OFFSET ERROR 2.048V voltage reference. The voltage reference has a
low temperature coefficient and low noise
An offset error is the deviation from zero voltage output characteristics. Refer to Section 1.0 “Electrical Char-
when the digital input code is zero. acteristics” for the voltage reference specifications.
4.0.4 GAIN ERROR
A gain error is the deviation from the ideal output,
VREF – 1 LSb, excluding the effects of offset error.

MCP4802/4812/4822
4.1.3 POWER-ON RESET CIRCUIT 4.1.4 SHUTDOWN MODE
The internal Power-on Reset (POR) circuit monitors the The user can shut down each DAC channel selectively
power supply voltage (VDD) during the device using a software command (<SHDN> = 0). During
operation. The circuit also ensures that the DAC Shutdown mode, most of the internal circuits in the
powers up with high output impedance (<SHDN> = 0, channel that was shut down are turned off for power
typically 500 k. The devices will continue to have a savings. The internal reference is not affected by the
high-impedance output until a valid write command is shutdown command. The serial interface also remains
received and the LDAC pin meets the input low active, thus allowing a write command to bring the
threshold. device out of the Shutdown mode. There will be no
If the power supply voltage is less than the POR analog output at the channel that was shut down and
threshold (VPOR = 2.0V, typical), the DACs will be held the VOUT pin is internally switched to a known resistive
in their Reset state. The DACs will remain in that state load (500 k typical. Figure 4-4 shows the analog
until VDD > VPOR and a subsequent write command is output stage during the Shutdown mode.
received. The device will remain in Shutdown mode until the
Figure 4-3 shows a typical power supply transient <SHDN> bit = 1 is latched into the device. When a
pulse and the duration required to cause a reset to DAC channel is changed from Shutdown to Active
occur, as well as the relationship between the duration mode, the output settling time takes < 10 µs, but
and trip voltage. A 0.1 µF decoupling capacitor, greater than the standard active mode settling time
mounted as close as possible to the VDD pin, can (4.5 µs).
provide additional transient immunity.
VOUT
Op
Amp
5V
Supply Voltages
VPOR Power-Down
VDD - VPOR Control Circuit
Transient Duration Resistive 500 k

Load
Resistive String DAC
Time
10
TA = +25°C FIGURE 4-4: Output Stage for Shutdown
Transient Duration (µs)
8
Mode.
4
Transients above the curve
will cause a reset
2
Transients below the curve
will NOT cause a reset
0
1 2 3 4 5
VDD - VPOR (V)
FIGURE 4-3: Typical Transient Response.

MCP4802/4812/4822
NOTES:

MCP4802/4812/4822
5.0 SERIAL INTERFACE 5.2 Write Command
The write command is initiated by driving the CS pin
5.1 Overview low, followed by clocking the four Configuration bits and
The MCP4802/4812/4822 devices are designed to the 12 data bits into the SDI pin on the rising edge of
interface directly with the Serial Peripheral Interface SCK. The CS pin is then raised, causing the data to be
(SPI) port, available on many microcontrollers, and latched into the selected DAC’s input registers.
supports Mode 0,0 and Mode 1,1. Commands and data The MCP4802/4812/4822 devices utilize a double-
are sent to the device via the SDI pin, with data being buffered latch structure to allow both DACA’s and
clocked-in on the rising edge of SCK. The DACB’s outputs to be synchronized with the LDAC pin,
communications are unidirectional and, thus, data if desired.
cannot be read out of the MCP4802/4812/4822 By bringing down the LDAC pin to a low state, the con-
devices. The CS pin must be held low for the duration tents stored in the DAC’s input registers are transferred
of a write command. The write command consists of into the DAC’s output registers (VOUT), and both VOUTA
16 bits and is used to configure the DAC’s control and and VOUTB are updated at the same time.
data latches. Register 5-1 to Register 5-3 detail the
input register that is used to configure and load the All writes to the MCP4802/4812/4822 devices are
DACA and DACB registers for each device. Figure 5-1 16-bit words. Any clocks after the first 16th clock will be
to Figure 5-3 show the write command for each device. ignored. The Most Significant four bits are
Configuration bits. The remaining 12 bits are data bits.
Refer to Figure 1-1 and SPI Timing Specifications No data can be transferred into the device with CS
Table for detailed input and output timing specifications high. The data transfer will only occur if 16 clocks have
for both Mode 0,0 and Mode 1,1 operation. been transferred into the device. If the rising edge of
CS occurs prior, shifting of data into the input registers
will be aborted.

MCP4802/4812/4822
REGISTER 5-1: WRITE COMMAND REGISTER FOR MCP4822 (12-BIT DAC)

W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x
A/B — GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
bit 15 bit 0

A/B — GA SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x x
bit 15 bit 0

A/B — GA SHDN D7 D6 D5 D4 D3 D2 D1 D0 x x x x
bit 15 bit 0
Where:
bit 15 A/B: DACA or DACB Selection bit

1 = Write to DACB
0 = Write to DACA
bit 14 — Don’t Care
bit 13 GA: Output Gain Selection bit
1 = 1x (VOUT = VREF * D/4096)
0 = 2x (VOUT = 2 * VREF * D/4096), where internal VREF = 2.048V.
bit 12 SHDN: Output Shutdown Control bit
1= Active mode operation. VOUT is available. 
0= Shutdown the selected DAC channel. Analog output is not available at the channel that was shut down.
VOUT pin is connected to 500 ktypical)
bit 11-0 D11:D0: DAC Input Data bits. Bit x is ignored.
Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

MCP4802/4812/4822
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1)
SCK (Mode 0,0)
config bits 12 data bits
SDI A/B — GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LDAC
VOUT
FIGURE 5-1: Write Command for MCP4822 (12-bit DAC).
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1)
SCK (Mode 0,0)
SDI A/B — GA SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
LDAC
VOUT
Note: X = “don’t care” bits.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1)
SCK (Mode 0,0)
SDI A/B — GA SHDN D7 D6 D5 D4 D3 D2 D1 D0 X X X X
LDAC
VOUT
Note: X = “don’t care” bits.

MCP4802/4812/4822
NOTES:

MCP4802/4812/4822
6.0 TYPICAL APPLICATIONS 6.3 Output Noise Considerations
The MCP4802/4812/4822 family of devices are The voltage noise density (in µV/Hz) is illustrated in
general purpose DACs for various applications where Figure 2-13. This noise appears at VOUTX, and is
a precision operation with low-power and internal primarily a result of the internal reference voltage.
voltage reference is required. Its 1/f corner (fCORNER) is approximately 400 Hz.
Applications generally suited for the devices are: Figure 2-14 illustrates the voltage noise (in mVRMS or
mVP-P). A small bypass capacitor on VOUTX is an
• Set Point or Offset Trimming
effective method to produce a single-pole Low-Pass
• Sensor Calibration Filter (LPF) that will reduce this noise. For instance, a
• Precision Selectable Voltage Reference bypass capacitor sized to produce a 1 kHz LPF would
• Portable Instrumentation (Battery-Powered) result in an ENREF of about 100 µVRMS. This would be
• Calibration of Optical Communication Devices necessary when trying to achieve the low DNL error
performance (at G = 1) that the MCP4802/4812/4822
6.1 Digital Interface devices are capable of. The tested range for stability is
.001µF through 4.7 µF.
The MCP4802/4812/4822 devices utilize a 3-wire
synchronous serial protocol to transfer the DAC’s setup VDD VDD
and input codes from the digital devices. The serial
protocol can be interfaced to SPI or Microwire C1 = 10 µF
C2 = 0.1 µF C1 C2 C1 C2
peripherals that is common on many microcontroller
units (MCUs), including Microchip’s PIC® MCUs and
dsPIC® DSCs. VDD
VOUTA CS1
In addition to the three serial connections (CS, SCK
1 µF
MCP48x2
and SDI), the LDAC signal synchronizes the two DAC C1 SDI
outputs. By bringing down the LDAC pin to “low”, all C2
DAC input codes and settings in the two DAC input reg-
VOUTB
PIC® Microcontroller
isters are latched into their DAC output registers at the
same time. Therefore, both DACA and DACB outputs
are updated at the same time. Figure 6-1 shows an
example of the pin connections. Note that the LDAC pin SDI AVSS SDO
MCP48x2
VOUTA
can be tied low (VSS) to reduce the required
connections from 4 to 3 I/O pins. In this case, the DAC SCK
1 µF
output can be immediately updated when a valid
16 clock transmission has been received and the CS VOUTB LDAC
pin has been raised.
CS0
6.2 Power Supply Considerations
The typical application will require a bypass capacitor AVSS VSS
in order to filter out the noise in the power supply FIGURE 6-1: Typical Connection
traces. The noise can be induced onto the power
Diagram.
supply's traces from various events such as digital
switching or as a result of changes on the DAC's
output. The bypass capacitor helps to minimize the 6.4 Layout Considerations
effect of these noise sources. Figure 6-1 illustrates an Inductively-coupled AC transients and digital switching
appropriate bypass strategy. In this example, two noises can degrade the output signal integrity, and
bypass capacitors are used in parallel: (a) 0.1 µF potentially reduce the device performance. Careful
(ceramic) and (b)10 µF (tantalum). These capacitors board layout will minimize these effects and increase
should be placed as close to the device power pin the Signal-to-Noise Ratio (SNR). Bench testing has
(VDD) as possible (within 4 mm). shown that a multi-layer board utilizing a
The power source supplying these devices should be low-inductance ground plane, isolated inputs and
as clean as possible. If the application circuit has isolated outputs with proper decoupling, is critical for
separate digital and analog power supplies, VDD and the best performance. Particularly harsh environments
VSS of the device should reside on the analog plane. may require shielding of critical signals.
Breadboards and wire-wrapped boards are not
recommended if low noise is desired.

MCP4802/4812/4822
6.5 Single-Supply Operation 6.5.1.1 Decreasing Output Step Size
The MCP4802/4812/4822 family of devices are rail-to- If the application is calibrating the bias voltage of a
rail voltage output DAC devices designed to operate diode or transistor, a bias voltage range of 0.8V may be
with a VDD range of 2.7V to 5.5V. Its output amplifier is desired with about 200 µV resolution per step. Two
robust enough to drive small-signal loads directly. common methods to achieve a 0.8V range are to either
Therefore, it does not require any external output buffer reduce VREF to 0.82V (using the MCP49XX family
for most applications. device that uses external reference) or use a voltage
divider on the DAC’s output.
6.5.1 DC SET POINT OR CALIBRATION Using a VREF is an option if the VREF is available with
A common application for the devices is a digitally- the desired output voltage range. However,
controlled set point and/or calibration of variable occasionally, when using a low-voltage VREF, the noise
parameters, such as sensor offset or slope. For floor causes SNR error that is intolerable. Using a
example, the MCP4822 provides 4096 output steps. If voltage divider method is another option and provides
G = 1 is selected, the internal 2.048V VREF would some advantages when VREF needs to be very low or
produce 500 µV of resolution. If G = 2 is selected, the when the desired output voltage is not available. In this
internal 2.048 VREF would produce 1 mV of resolution. case, a larger value VREF is used while two resistors
scale the output range down to the precise desired
level.
Example 6-1 illustrates this concept. Note that the
bypass capacitor on the output of the voltage divider
plays a critical function in attenuating the output noise
of the DAC and the induced noise from the environ-
ment.
EXAMPLE 6-1: EXAMPLE CIRCUIT OF SET POINT OR THRESHOLD CALIBRATION

VDD
(a) Single Output DAC:

MCP4801
MCP4811
MCP4821 VCC+
(b) Dual Output DAC: RSENSE
VDD
MCP4802
MCP4812
Comparator
MCP4822 R1 VTRIP
VOUT
DAC
0.1 µF VCC–
R2
SPI
3-wire
Dn G = Gain selection (1x or 2x)

VOUT = 2.048  G  ------
N
2 Dn = Digital value of DAC (0-255) for MCP4801/MCP4802
= Digital value of DAC (0-1023) for MCP4811/MCP4812
 R2  = Digital value of DAC (0-4095) for MCP4821/MCP4822
V trip = VOUT  --------------------
 R 1 + R 2 N = DAC bit resolution

MCP4802/4812/4822
6.5.1.2 Building a “Window” DAC If the threshold is not near VREF, 2VREF or VSS, then
creating a “window” around the threshold has several
When calibrating a set point or threshold of a sensor,
advantages. One simple method to create this
typically only a small portion of the DAC output range is
“window” is to use a voltage divider network with a pull-
utilized. If the LSb size is adequate enough to meet the
up and pull-down resistor. Example 6-2 shows this
application’s accuracy needs, the unused range is
concept.
sacrificed without consequences. If greater accuracy is
needed, then the output range will need to be reduced
to increase the resolution around the desired threshold.
EXAMPLE 6-2: SINGLE-SUPPLY “WINDOW” DAC
(a) Single Output DAC:

MCP4801
MCP4811
MCP4821
(b) Dual Output DAC:
MCP4802
MCP4812
VCC+ VCC+
MCP4822 RSENSE
VDD
R3
Comparator
R1 VTRIP
VOUT
DAC
VCC-
R2 0.1 µF
SPI
3-wire
VCC-
Dn
VOUT = 2.048  G  ------
N
2
G = Gain selection (1x or 2x)
Dn = Digital value of DAC (0-255) for MCP4801/MCP4802
N = DAC bit resolution
R2 R3
R 23 = ------------------- R1
R2 + R3 VOUT VO
Thevenin
Equivalent  V CC+ R 2  +  V CC- R 3 
V 23 = ------------------------------------------------------ R23
R2 + R3
V OUT R23 + V 23 R1
V trip = --------------------------------------------- V23
R 1 + R23

MCP4802/4812/4822
6.6 Bipolar Operation Example 6-3 illustrates a simple bipolar voltage source
configuration. R1 and R2 allow the gain to be selected,
Bipolar operation is achievable using the while R3 and R4 shift the DAC's output to a selected
MCP4802/4812/4822 family of devices by utilizing an offset. Note that R4 can be tied to VDD, instead of VSS,
external operational amplifier (op amp). This if a higher offset is desired. Also note that a pull-up to
configuration is desirable due to the wide variety and VDD could be used instead of R4, or in addition to R4, if
availability of op amps. This allows a general purpose a higher offset is desired.
DAC, with its cost and availability advantages, to meet
almost any desired output voltage range, power and
noise performance.
EXAMPLE 6-3: DIGITALLY-CONTROLLED BIPOLAR VOLTAGE SOURCE

R2
(a) Single Output DAC: VDD
MCP4801
VDD
MCP4811 R1 VCC+
MCP4821 R3 VO
VOUT
(b) Dual Output DAC: DAC
MCP4802
VIN+
VCC–
MCP4812 R4 0.1 µF
MCP4822 SPI
3-wire
Dn
VOUT = 2.048  G  ------
N
2 G = Gain selection (1x or 2x)
VOUT R 4
VIN+ = -------------------- = Digital value of DAC (0-1023) for MCP4811/MCP4812
R 3 + R4
R2 R2 N = DAC bit resolution
V O = V IN+  1 + ------ – V DD  ------
 R1   R 1
6.6.1 DESIGN EXAMPLE: DESIGN A The equation can be simplified to:

BIPOLAR DAC USING EXAMPLE 6-3
WITH 12-BIT MCP4822 OR – R2 – 2.05 R2 1
--------- = ----------------- ------ = ---
MCP4821 R1 4.096V R1 2
An output step magnitude of 1 mV, with an output range
If R1 = 20 k and R2 = 10 k, the gain will be 0.5.
of ±2.05V, is desired for a particular application.
Step 1: Calculate the range: +2.05V – (-2.05V) = 4.1V.
Step 4: Next, solve for R3 and R4 by setting the DAC to
Step 2: Calculate the resolution needed:
4096, knowing that the output needs to be
4.1V/1 mV = 4100 +2.05V.
Since 212 = 4096, 12-bit resolution is
desired. R4 2.05V +  0.5  4.096V  2
------------------------ = ------------------------------------------------------- = ---
Step 3:The amplifier gain (R2/R1), multiplied by full-  R3 + R4  1.5  4.096V 3
scale VOUT (4.096V), must be equal to the
desired minimum output to achieve bipolar If R4 = 20 k, then R3 = 10 k
operation. Since any gain can be realized by
choosing resistor values (R1+R2), the VREF
value must be selected first. If a VREF of 4.096V
is used (G=2), solve for the amplifier’s gain by
setting the DAC to 0, knowing that the output
needs to be -2.05V.

MCP4802/4812/4822
6.7 Selectable Gain and This circuit is typically used for linearizing a sensor
Offset Bipolar Voltage Output whose slope and offset varies.
Using a Dual Output DAC The equation to design a bipolar “window” DAC would
be utilized if R3, R4 and R5 are populated.
In some applications, precision digital control of the
output range is desirable. Example 6-4 illustrates how
to use the MCP4802/4812/4822 family of devices to
achieve this in a bipolar or single-supply application.
EXAMPLE 6-4: BIPOLAR VOLTAGE SOURCE WITH SELECTABLE GAIN AND OFFSET
R2
VDD
VCC+
VOUTA R1
DACA
Dual Output DAC:
(DACA for Gain Adjust) VCC+
MCP4802 VDD VO
MCP4812 R5
MCP4822 VOUTB R3 VIN+
DACB
(DACB for Offset Adjust)
SPI R4
0.1 µF VCC–
3
Dn VCC–
V OUTA = 2.048  G A  ------
N
2
Dn G = Gain selection (1x or 2x)
VOUTB = 2.048  G B  ------
N N = DAC bit resolution
2
DA , DB = Digital value of DAC (0-255) for MCP4802
VOUTB R 4 + V CC- R 3 = Digital value of DAC (0-1023) for MCP4812
VIN+ = -------------------------------------------------
R 3 + R4 = Digital value of DAC (0-4095) for MCP4822
R2 R2
V O = V IN+  1 + ------ – V OUTA  ------
R1 R1
Offset Adjust Gain Adjust
Bipolar “Window” DAC using R4 and R5

Thevenin VCC+ R4 + V CC- R 5 R4R5
Equivalent V45 = --------------------------------------------- R45 = -------------------
R4 + R 5 R4 + R5
V OUTB R 45 + V45 R 3 R2 R2
V IN+ = ------------------------------------------------ V O = V IN+  1 + ------ – V OUTA  ------
R 3 + R 45  R 1  R 1
Offset Adjust Gain Adjust

MCP4802/4812/4822
6.8 Designing a Double-Precision Step 1: Calculate the resolution needed:
DAC Using a Dual DAC 4.1V/1 µV = 4.1 x 106. Since 222 = 4.2 x 106,
22-bit resolution is desired. Since
Example 6-5 illustrates how to design a single-supply
DNL = ±0.75 LSb, this design can be done
voltage output capable of up to 24-bit resolution from a
with the 12-bit MCP4822 DAC.
dual 12-bit DAC (MCP4822). This design is simply a
voltage divider with a buffered output. Step 2: Since DACB’s VOUTB has a resolution of 1 mV,
its output only needs to be “pulled” 1/1000 to
As an example, if an application similar to the one
meet the 1 µV target. Dividing VOUTA by 1000
developed in Section 6.6.1 “Design Example:
would allow the application to compensate for
Design a Bipolar DAC Using Example 6-3 with 12-
DACB’s DNL error.
bit MCP4822 or MCP4821” required a resolution of
1 µV instead of 1 mV, and a range of 0V to 4.1V, then Step 3: If R2 is 100, then R1 needs to be 100 k.
12-bit resolution would not be adequate. Step 4: The resulting transfer function is shown in the
equation of Example 6-5.
EXAMPLE 6-5: SIMPLE, DOUBLE-PRECISION DAC WITH MCP4822
VDD
VCC+
VOUTA
MCP4822
(DACA for Fine Adjustment)
R1 VO
R1 >> R2
VDD
VCC–
VOUTB R2 0.1 µF
MCP4822
(DACB for Course Adjustment)
SPI
3-wire
DA
VOUTA = 2.048  G A  -------
12 Gx = Gain selection (1x or 2x)
2
DB Dn = Digital value of DAC (0-4096)
V OUTB = 2.048  GB  -------
12
2
V OUTA R 2 + VOUTB R 1
VO = ------------------------------------------------------
R 1 + R2

MCP4802/4812/4822
6.9 Building Programmable Current However, this also reduces the resolution that the
Source current can be controlled with. The voltage divider, or
“window”, DAC configuration would allow the range to
Example 6-6 shows an example of building a be reduced, thus increasing resolution around the
programmable current source using a voltage follower. range of interest. When working with very small sensor
The current sensor (sensor resistor) is used to convert voltages, plan on eliminating the amplifier’s offset error
the DAC voltage output into a digitally-selectable by storing the DAC’s setting under known sensor
current source. conditions.
Adding the resistor network from Example 6-2 would
be advantageous in this application. The smaller
RSENSE is, the less power dissipated across it.
EXAMPLE 6-6: DIGITALLY-CONTROLLED CURRENT SOURCE
VDD or VREF
(a) Single Output DAC: VDD

Load
MCP4801 VCC+
MCP4811 VOUT IL
MCP4821 DAC
(b) Dual Output DAC:
Ib
MCP4802 SPI
VCC–
MCP4812 3-wire
MCP4822
RSENSE
IL
I b = ---- G = Gain selection (1x or 2x)

V OUT  = Digital value of DAC (0-1023) for MCP4811/MCP4812
I L = ---------------  -------------
R sense  + 1 = Digital value of DAC (0-4095) for MCP4821/MCP4822
where Common-Emitter Current Gain N = DAC bit resolution

MCP4802/4812/4822
NOTES:

MCP4802/4812/4822
7.0 DEVELOPMENT SUPPORT
7.1 Evaluation and Demonstration

Boards
The Mixed Signal PICtail™ Demo Board supports the
MCP4802/4812/4822 family of devices. Refer to
www.microchip.com for further information on this
product’s capabilities and availability.

MCP4802/4812/4822
NOTES:

MCP4802/4812/4822
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
8-Lead MSOP Example:
XXXXXX 4822E
YWWNNN 009256
8-Lead PDIP (300 mil) Example:
XXXXXXXX MCP4802
XXXXXNNN E/P e^3 256
YYWW 1009
8-Lead SOIC (150 mil) Example:
XXXXXXXX MCP4812E
XXXXYYWW SN^^
e3 1009
NNN 256
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

MCP4802/4812/4822
/HDG3ODVWLF0LFUR6PDOO2XWOLQH3DFNDJH 06 >0623@
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
E
E1
NOTE 1
1 2
e
c φ
A A2
A1 L1 L
8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $
6WDQGRII $ ±
2YHUDOO:LGWK ( %6&
0ROGHG3DFNDJH:LGWK ( %6&
2YHUDOO/HQJWK ' %6&
)RRW/HQJWK /
)RRWSULQW / 5()
)RRW$QJOH ±
/HDG7KLFNQHVV F ±
/HDG:LGWK E ±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

MCP4802/4812/4822
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

MCP4802/4812/4822
/HDG3ODVWLF'XDO,Q/LQH 3 ±PLO%RG\>3',3@
NOTE 1
E1
1 2 3
D
E
A A2
A1 L
c
e
b1 eB
b
8QLWV ,1&+(6
1XPEHURI3LQV 1
3LWFK H %6&
7RSWR6HDWLQJ3ODQH $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $
%DVHWR6HDWLQJ3ODQH $ ± ±
6KRXOGHUWR6KRXOGHU:LGWK (
0ROGHG3DFNDJH:LGWK (
2YHUDOO/HQJWK '
7LSWR6HDWLQJ3ODQH /
/HDG7KLFNQHVV F
8SSHU/HDG:LGWK E
/RZHU/HDG:LGWK E
2YHUDOO5RZ6SDFLQJ H% ± ±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKWKHKDWFKHGDUHD
6LJQLILFDQW&KDUDFWHULVWLF
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH
%6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

MCP4802/4812/4822
/HDG3ODVWLF6PDOO2XWOLQH 61 ±1DUURZPP%RG\>62,&@
e
N
E1
NOTE 1
1 2 3
h α
b
h
c
A A2 φ
A1 L
L1 β
8QLWV 0,//,0(7(56
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $ ± ±
6WDQGRII $ ±
2YHUDOO:LGWK ( %6&
0ROGHG3DFNDJH:LGWK ( %6&
2YHUDOO/HQJWK ' %6&
&KDPIHU RSWLRQDO K ±
)RRW/HQJWK / ±
)RRWSULQW / 5()
)RRW$QJOH ±
/HDG7KLFNQHVV F ±
/HDG:LGWK E ±
0ROG'UDIW$QJOH7RS ±
0ROG'UDIW$QJOH%RWWRP ±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
6LJQLILFDQW&KDUDFWHULVWLF
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

MCP4802/4812/4822
/HDG3ODVWLF6PDOO2XWOLQH 61 ±1DUURZPP%RG\>62,&@

MCP4802/4812/4822
APPENDIX A: REVISION HISTORY
Revision A (April 2010)

• Original Release of this Document.

MCP4802/4812/4822
NOTES:

MCP4802/4812/4822
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX
Examples:
Device Temperature Package a) MCP4802-E/MS: Extended temperature,
Range MSOP package.
b) MCP4802T-E/MS: Extended temperature,
MSOP package,
Tape and Reel.
Device: MCP4802: Dual 8-Bit Voltage Output DAC
MCP4802T: Dual 8-Bit Voltage Output DAC c) MCP4802-E/P: Extended temperature,
(Tape and Reel, MSOP and SOIC only) PDIP package.
d) MCP4802-E/SN: Extended temperature,
MCP4812: Dual 10-Bit Voltage Output DAC
MCP4812T: Dual 10-Bit Voltage Output DAC SOIC package.
(Tape and Reel, MSOP and SOIC only) e) MCP4802T-E/SN: Extended temperature,
SOIC package,
MCP4822: Dual 12-Bit Voltage Output DAC
MCP4822T: Dual 12-Bit Voltage Output DAC Tape and Reel.
(Tape and Reel, MSOP and SOIC only) a) MCP4812-E/MS: Extended temperature,
MSOP package.
Temperature E = -40C to +125C (Extended) MSOP package,
Range: Tape and Reel.
c) MCP4812-E/P: Extended temperature,
PDIP package.
Package: MS = 8-Lead Plastic Micro Small Outline (MSOP) d) MCP4812-E/SN: Extended temperature,
P = 8-Lead Plastic Dual In-Line (PDIP)
SN = 8-Lead Plastic Small Outline - Narrow, 150 mil SOIC package.
(SOIC) e) MCP4812T-E/SN: Extended temperature,
SOIC package,
Tape and Reel.
a) MCP4822-E/MS: Extended temperature,

MSOP package.
MSOP package,
Tape and Reel.
c) MCP4822-E/P: Extended temperature,
PDIP package.
d) MCP4822-E/SN: Extended temperature,
SOIC package.
e) MCP4822T-E/SN: Extended temperature,
SOIC package,
Tape and Reel.

MCP4802/4812/4822
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PIC32 logo, rfPIC and UNI/O are registered trademarks of
MICROCHIP MAKES NO REPRESENTATIONS OR
Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control
QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip
FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-128-4
Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

WORLDWIDE SALES AND SERVICE
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393
Tel: 480-792-7200 Harbour City, Kowloon Denmark - Copenhagen
India - New Delhi
Fax: 480-792-7277 Hong Kong Tel: 45-4450-2828
Tel: 91-11-4160-8631
Technical Support: Tel: 852-2401-1200 Fax: 45-4485-2829
Fax: 91-11-4160-8632
http://support.microchip.com Fax: 852-2401-3431
India - Pune France - Paris
Web Address:
Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20
www.microchip.com
Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79
Atlanta Fax: 61-2-9868-6755
Japan - Yokohama Germany - Munich
Duluth, GA
China - Beijing Tel: 49-89-627-144-0
Tel: 678-957-9614 Tel: 81-45-471- 6166
Tel: 86-10-8528-2100 Fax: 49-89-627-144-44
Fax: 678-957-1455 Fax: 81-45-471-6122
Fax: 86-10-8528-2104 Italy - Milan
Boston Korea - Daegu
China - Chengdu Tel: 39-0331-742611
Westborough, MA Tel: 82-53-744-4301
Tel: 86-28-8665-5511 Fax: 39-0331-466781
Tel: 774-760-0087 Fax: 82-53-744-4302
Fax: 86-28-8665-7889 Netherlands - Drunen
Fax: 774-760-0088 Korea - Seoul
China - Chongqing Tel: 82-2-554-7200 Tel: 31-416-690399
Chicago
Tel: 86-23-8980-9588 Fax: 82-2-558-5932 or Fax: 31-416-690340
Itasca, IL
Tel: 630-285-0071 Fax: 86-23-8980-9500 82-2-558-5934 Spain - Madrid
Fax: 630-285-0075 China - Hong Kong SAR Tel: 34-91-708-08-90
Malaysia - Kuala Lumpur
Tel: 852-2401-1200 Tel: 60-3-6201-9857 Fax: 34-91-708-08-91
Cleveland
Independence, OH Fax: 852-2401-3431 Fax: 60-3-6201-9859 UK - Wokingham
Tel: 216-447-0464 China - Nanjing Tel: 44-118-921-5869
Malaysia - Penang
Fax: 216-447-0643 Tel: 86-25-8473-2460 Fax: 44-118-921-5820
Tel: 60-4-227-8870
Dallas Fax: 86-25-8473-2470 Fax: 60-4-227-4068
Addison, TX China - Qingdao Philippines - Manila
Tel: 972-818-7423 Tel: 86-532-8502-7355 Tel: 63-2-634-9065
Fax: 972-818-2924 Fax: 86-532-8502-7205 Fax: 63-2-634-9069
Detroit China - Shanghai Singapore
Farmington Hills, MI Tel: 86-21-5407-5533 Tel: 65-6334-8870
Tel: 248-538-2250 Fax: 86-21-5407-5066 Fax: 65-6334-8850
Fax: 248-538-2260
China - Shenyang Taiwan - Hsin Chu
Kokomo Tel: 86-24-2334-2829 Tel: 886-3-6578-300
Kokomo, IN Fax: 86-24-2334-2393 Fax: 886-3-6578-370
Tel: 765-864-8360
Fax: 765-864-8387 China - Shenzhen Taiwan - Kaohsiung
Tel: 86-755-8203-2660 Tel: 886-7-536-4818
Los Angeles Fax: 86-755-8203-1760 Fax: 886-7-536-4803
Mission Viejo, CA
Tel: 949-462-9523 China - Wuhan Taiwan - Taipei
Fax: 949-462-9608 Tel: 86-27-5980-5300 Tel: 886-2-2500-6610
Fax: 86-27-5980-5118 Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA China - Xian Thailand - Bangkok
Tel: 408-961-6444 Tel: 86-29-8833-7252 Tel: 66-2-694-1351
Fax: 408-961-6445 Fax: 86-29-8833-7256 Fax: 66-2-694-1350
Toronto China - Xiamen

Mississauga, Ontario, Tel: 86-592-2388138
Canada Fax: 86-592-2388130
Tel: 905-673-0699 China - Zhuhai
Fax: 905-673-6509 Tel: 86-756-3210040
Fax: 86-756-3210049
01/05/10

MCP4802

Uploaded by

MCP4802

Uploaded by

MCP4802/4812/4822

8/10/12-Bit Dual Voltage Output Digital-to-Analog Converter

 2010 Microchip Technology Inc. DS22249A-page 1

DS22249A-page 2  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. DS22249A-page 3

DS22249A-page 4  2010 Microchip Technology Inc.

ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE

 2010 Microchip Technology Inc. DS22249A-page 5

AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)

DS22249A-page 6  2010 Microchip Technology Inc.

FIGURE 1-1: SPI Input Timing Data.

 2010 Microchip Technology Inc. DS22249A-page 7

DS22249A-page 8  2010 Microchip Technology Inc.

Code (Decimal) 125C 85C 25C Ambient Temperature (ºC)

Ambient Temperature (ºC) Code (Decimal)

 2010 Microchip Technology Inc. DS22249A-page 9

Full Scale VOUT (V)

DS22249A-page 10  2010 Microchip Technology Inc.

FIGURE 2-15: IDD vs. Temperature and VDD.

 2010 Microchip Technology Inc. DS22249A-page 11

3.5 5.0V 5.5V

VIN Hi Threshold (V)

2.5 2.5 4.0V

VIN Low Threshold (V)

FIGURE 2-20: Gain Error vs. Temperature

DS22249A-page 12  2010 Microchip Technology Inc.

FIGURE 2-25: VOUT Low Limit vs.

 2010 Microchip Technology Inc. DS22249A-page 13

Time (1 µs/div) Time (1 µs/div)

Time (1 µs/div) Time (1 µs/div)

Time (1 µs/div) Frequency (Hz)

DS22249A-page 14  2010 Microchip Technology Inc.

TABLE 3-1: PIN FUNCTION TABLE FOR MCP4802/4812/4822

3.3 Serial Clock Input (SCK)

 2010 Microchip Technology Inc. DS22249A-page 15

DS22249A-page 16  2010 Microchip Technology Inc.

(a) 0.0V to 1023/1024 * 2.048V when gain setting = 1x. 001

FIGURE 4-1: Example for INL Error.

 2010 Microchip Technology Inc. DS22249A-page 17

DS22249A-page 18  2010 Microchip Technology Inc.

Transient Duration Resistive 500 k

FIGURE 4-3: Typical Transient Response.

 2010 Microchip Technology Inc. DS22249A-page 19

DS22249A-page 20  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. DS22249A-page 21

REGISTER 5-1: WRITE COMMAND REGISTER FOR MCP4822 (12-BIT DAC)

REGISTER 5-2: WRITE COMMAND REGISTER FOR MCP4812 (10-BIT DAC)

REGISTER 5-3: WRITE COMMAND REGISTER FOR MCP4802 (8-BIT DAC)

bit 15 A/B: DACA or DACB Selection bit

DS22249A-page 22  2010 Microchip Technology Inc.

config bits 12 data bits

SDI A/B — GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

FIGURE 5-1: Write Command for MCP4822 (12-bit DAC).

config bits 12 data bits

SDI A/B — GA SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

Note: X = “don’t care” bits.

FIGURE 5-2: Write Command for MCP4812 (10-bit DAC).

config bits 12 data bits

SDI A/B — GA SHDN D7 D6 D5 D4 D3 D2 D1 D0 X X X X

Note: X = “don’t care” bits.

FIGURE 5-3: Write Command for MCP4802 (8-bit DAC).

 2010 Microchip Technology Inc. DS22249A-page 23

DS22249A-page 24  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. DS22249A-page 25

EXAMPLE 6-1: EXAMPLE CIRCUIT OF SET POINT OR THRESHOLD CALIBRATION

(a) Single Output DAC:

Dn G = Gain selection (1x or 2x)

DS22249A-page 26  2010 Microchip Technology Inc.

EXAMPLE 6-2: SINGLE-SUPPLY “WINDOW” DAC

(a) Single Output DAC:

 2010 Microchip Technology Inc. DS22249A-page 27

EXAMPLE 6-3: DIGITALLY-CONTROLLED BIPOLAR VOLTAGE SOURCE

6.6.1 DESIGN EXAMPLE: DESIGN A The equation can be simplified to:

DS22249A-page 28  2010 Microchip Technology Inc.

Offset Adjust Gain Adjust

Bipolar “Window” DAC using R4 and R5

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%