Instruction cycle in 8085 microprocessor

Introduction :
✓The 8085 microprocessor is a popular 8-bit microprocessor that was first introduced by Intel in
1976. It has a set of instructions that it can execute, and the execution of each instruction involves a
series of steps known as the instruction cycle.
✓The instruction cycle of the 8085 microprocessor consists of four basic steps, which are:
1.Fetch: In this step, the microprocessor fetches the instruction from the memory location pointed to
by the program counter (PC). The PC is incremented by one after the fetch operation.
2.Decode: Once the instruction is fetched, the microprocessor decodes it to determine the operation
to be performed and the operands involved.
3.Execute: In this step, the microprocessor performs the operation specified by the instruction on the
operands.
4.Store: Finally, the result of the execution is stored in the appropriate memory location or register.
• Once the execution of an instruction is complete, the microprocessor returns to the fetch step to
fetch the next instruction to be executed. This cycle repeats until the program is complete or
interrupted.

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 8085 Machine Cycle
Machine Cycle:
✓ A machine cycle consists of the steps that a computer’s processor executes whenever it receives a machine
language instruction.
✓ It is the most basic CPU operation, and modern CPUs are able to perform millions of machine cycles per
second.
✓ The cycle consists of three standard steps: fetch, decode and execute.
✓ In some cases, store is also incorporated into the cycle.
✓ Four steps of machine cycle:
1. Fetch - Retrieve an instruction from the memory.
2. Decode - Translate the retrieved instruction into a series of computer commands.
3. Execute - Execute the computer commands.
4. Store - Send and write the results back in memory.

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✓The time required by the microprocessor to complete an operation of
accessing memory or input/output devices is called machine cycle.
✓ One time period of frequency of microprocessor is called t-state.
✓A t-state is measured from the falling edge of one clock pulse to the
falling edge of the next clock pulse.
✓Fetch cycle takes four t-states and execution cycle takes three t-stat

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Timing Diagram:

✓Timing Diagram is a graphical representation. T-states. The time

required to execute an instruction is called instruction cycle.
✓ The time required to access the memory or input/output devices is
called machine cycle.

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Opcode Fetch Machine Cycle:

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✓Opcode fetch cycle is part of any instruction execution.
✓In this machine cycle 8085 fetches opcode of instruction.
✓The following are the sequence of actions that are performed by 8085 to
fetch an opcode from memory.
✓ This machine cycle consists of 4 T-states.
✓8085 places 16-bit address from PC on to the address bus and issues ALE
(Address Latch Enable) pulse in first T-state (T1). This is used to de-multiplex
the address and data bus. It also issues IO/M’ signal to ‘0’. This indicates that
processor is performing memory related operation.

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• In second T-state (T2) processor issues RD’ control signal to memory. This
enables memory to put data present at the address location given in previous
T-state on to data bus. RD’ control signal is active for two clock pulses.
• In T3 state memory places opcode on Data bus. Processor reads opcode
present on data bus and de-asserts RD’ signal. Thus data bus goes into high
impedance state.
• In T4 state processor decodes instruction and necessary actions are
performed.

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 Memory Read machine cycle

✓This machine cycle is required when an operand is present in

memory.
✓This machine cycle requires three T-states.
✓The following are the sequence of actions performed by
microprocessor during this machine cycle.

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 Fig - Timing Diagram for Memory Read Machine Cycle

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• In the first T-state (T1) 8085 places address on address bus and issues ALE
signal. And also IO/M’ signal is made low, since it is memory related operation.
• In the second T-state (T2), processor issues RD’ control signal to memory. In
response to this memory places data on data bus.
• In the third T-state (T3), processor reads data from data bus, and de-asserts
RD’ signal.

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 Memory Write Machine cycle:
✓This machine cycle is required when the results of operation needs to
store in memory.
✓This machine cycle requires three T-states.
✓ The following are sequence of actions performed by processor in this
machine cycle

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 Fig - Timing Diagram for Memory Write Machine Cycle

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• In first T-state (T1), 8085 processor places 16- bit address on address bus and
issues ALE signal. And also it makes IO/M’ signal to low, indicating it is
memory related operation.
• In second T-state (T2), processor places data to be written on data bus and
asserts WR’ signal to the memory.
• In the third T-state (T3), memory stores the data and processor de-asserts
WR’ signal.

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 IO read machine cycle:
✓This machine cycle is required, when data needs to be read from an input
device.
✓This machine cycle requires three T-states.
✓The following are the sequence of actions performed by processor during
this machine cycle.

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 Fig - Timing Diagram for I/O Read Machine Cycle

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• In the first T-state (T1) 8085 places port address on address bus and issues
ALE signal. And also IO/M’ signal is made high, since it is IO related
operation.
• In the second T-state (T2), processor issues RD’ control signal to IO
peripheral. In response to this input device places data on data bus.
• In the third T-state (T3), processor reads data from data bus, and de-asserts
RD’ signal.

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 IO writes Machine cycle
✓This machine cycle is required when data needs to be output to an output
device.
✓This machine cycle requires three T-states.
✓The following are the sequence of actions performed by processor during
this machine cycle

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 Fig - Timing Diagram for I/O Write Machine Cycle

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• In first T-state (T1), 8085 processor places 8-bit port address on address bus
and issues ALE signal. And also it makes IO/M’ signal to high, indicating it is IO
related operation.
• In second T-state (T2), processor places data to be written on data bus and
asserts WR’ signal to the peripheral.
• In the third T-state (T3), peripheral accepts the data and processor de-asserts
WR’ signal.

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 Introduction to - 8086 microprocessor
✓8086 Microprocessor is an enhanced version of 8085Microprocessor that was
designed by Intel in 1976.
✓It is a 16-bit Microprocessor having 20 address lines and16 data lines that
provides up to 1MB storage.
✓It consists of powerful instruction set, which provides operations like
multiplication and division easily.
✓It supports two modes of operation, i.e. Maximum mode and Minimum
mode.
✓Maximum mode is suitable for system having multiple processors and
Minimum mode is suitable for system having a single processor.

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 Features of 8086
• It has an instruction queue, which is capable of storing six instruction bytes from the
memory resulting in faster processing.
• It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus,
and 16-bit external data bus resulting in faster processing.
• It is available in 3 versions based on the frequency of operation −
• 8086 → 5MHz
• 8086-2 → 8MHz
• (c)8086-1 → 10 MHz
• It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves
performance.
• Fetch stage can pre fetch up to 6 bytes of instructions and stores them in the queue.
• Execute stage executes these instructions.
• It has 256 vectored interrupts.
• It consists
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Difference between 8085 and 8086 Microprocessor

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 Architecture of 8086

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