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    End Examination April 2023-Sem6 ECE 321-VLSI Design

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    ShaimaAhammed Vembala
    vlsi

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    End Examination April 2023-Sem6 ECE 321-VLSI Design

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    ShaimaAhammed Vembala
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    vlsi

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    Copyright:

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    5 views2 pages

    End Examination April 2023-Sem6 ECE 321-VLSI Design

    Uploaded by

    ShaimaAhammed Vembala
    vlsi

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    STITUTE OF INFORMATION TECHNOLOGY KOTTAYAM


    Department of Electronics and Communication Engineering
    Indian Institute of
    Information Technology
    Kottayam
    END SEMESTER EXAMINATION- APRIL. 2023
    COURSE TITLE: ECE 321-VLSI Design
    Time: 24.04.2023,09:30 AM-12:30 PM Max. Marks: 100
    Course Instructor: Dr. Kaia S Batch: 2020 ECE

    Answer all Questions

    1. Explain different kind o f faults in logic circuits. (3marks)

    2. Discuss DFT, boundary Cell and draw scan chain (4marks)

    3. With an example explain observability and controllability. (3marks)

    4. Write the differences between testing and verification. (4marks)

    5. Explain the impact o f Dennard Scaling and discuss about DarkSilicon. (4 marks)

    6. Write any two techniques for power reduction in VLSI circuit design. (4 marks)

    7. Draw the dual o f the NMOS network given in Fig. 1. (4 marks)

    8. Give transistor level designs for 2-input NAND gates using static and dynamic CMOS, explaining

    how the latter is controlled by clock. (6 marks)

    9. Sketch the circuit o f a dynamic CMOS gate controlled by clock, which evaluates the function

    (A + B . C )’ . Describe an advantage and disadvantage compared with static CMOS. (5 marks)

    10. Explain VTC o f CMOS inverter and describe Noise Margin. (5 marks)

    11. Sketch a transistor level circuit for the function (A . B + C. D )’ in static CMOS. Calculate the

    logical effort. ( 3 + 3 = 6 marks)

    12. Write test vectors for all single stuck at faults in NAND, NOR, OR and AND gates. (8 marks)
    13. Consider NAND and NOR gates. Write the equivalent faults (4 marks)

    14. Explain the working o f dynamic NAND gate and XOR gates. (10 m arks)
    1/2
    15. Discuss the working o f transmission-gate based 2:1 multiplexer, inverted multiplexer and pass
    transistor logic. (10 marks)

    16. What are concurrent and procedural statements in Verilog. Discuss blocking and non-blocking
    statements with suitable examples. (10 marks)

    17. Consider s-a-1 fault in the circuit. Write the test vectors. (10 marks)

    2/2

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