Topic 3a

Bus Structure & IO Techniques

Jan 16 2023
By Dr. Ahuna
 Bus Structure of the 8085
The Bus Structure
 The Control Unit generates signals on data bus, address bus and control bus
within microprocessor to carry out the instruction, which has been decoded.
Typical buses and their timing are described as follows:
Data Bus
 The data bus carries data in binary form between microprocessor and other
external units such as memory. It is used to transmit data i.e. information,
results of arithmetic etc between memory and the microprocessor. Data bus
is bidirectional in nature.
 The data bus width of 8085 microprocessor is 8-bit i.e. 256 combinations of
binary digits and are typically identified as D0 – D7. Thus size of the data
bus determines what arithmetic can be done. If only 8-bit wide then largest
number is 111111112 (255 in decimal) while the lowest is 000000002.
 Bus Structure of the 8085
The Bus Structure
Address Bus
 Generally, 8085 microprocessor has 16 bit address bus and the lines are
generally identified as A0 - A15.
 The higher order address lines (A8 – A15) are unidirectional and the lower
order lines (A0 – A7) are multiplexed (time-shared) with the eight data bits
(D0 – D7) and hence, they are bidirectional.
 The address bus carries the address of memory location to be written into or
to be read from.
 The address bus is unidirectional. This means bits flowing occurs only in
one direction, only from microprocessor to peripheral devices.
 Bus Structure of the 8085
The Bus Structure
Control Bus
 The control bus is used for sending control signals to the memory and I/O
devices. The control bus consists of various lines which have specific functions
for coordinating and controlling microprocessor operations. The following
control and status signals are used by 8085 processor:
 ALE (output): Address Latch Enable is a pulse that is provided when an address
appears on the AD0 – AD7 lines, after which it becomes 0.
 𝑅𝐷 (active low output): The Read signal indicates that data are being read from
the selected I/O or memory device and that they are available on the data bus.
 𝑊𝑅 (active low output): The Write signal indicates that data on the data bus
are to be written into a selected memory or I/O location.
 IO/𝑀 ഥ (output): It is a signal that distinguished between a memory operation
and an I/O operation. When 𝐼𝑂/𝑀 ഥ = 0, it is a memory operation and 𝐼𝑂/𝑀ഥ=
1 it is an I/O operation.
 S1 and S0 (output): These are status signals used to specify the type of operation
being performed; they are listed in the table below.
 Bus Structure of the 8085
The Bus Structure
Control Bus

S1 S0 States
0 0 Halt
0 1 Write
1 0 Read
1 1 Fetch
 Bus Structure of the 8085
The Bus Structure
 The schematic representation of the 8085 bus structure is as shown in Fig. 1
and the microprocessor performs primarily four operations:
 Memory Read: Reads data (or instruction) from memory.
 Memory Write: Writes data (or instruction) into memory.
 I/O Read: Accepts data from input device.
 I/O Write: Sends data to output device.
 The 8085 processor performs these functions using address bus, data bus
and control bus as shown in Fig. 1.
 Bus Structure of the 8085
The Bus Structure

Fig. 1 The 8085 bus structure

 Bus Structure of the 8085
The 8085 Bus Buffering
 A digital buffer (or a voltage buffer) is an electronic circuit element used
to isolate an input from an output. It has one input line and one output line
and the logic level of the output is the same as that of the input.
 This circuit is primarily used to increase the driving capability of a logic
circuit and is also known as a driver.

The Single Input Digital Buffer

 Bus Structure of the 8085
The 8085 Bus Buffering
Tri-state buffer
 A Tri-state Buffer can be thought of as an input controlled switch with an
output that can be electronically turned “ON” or “OFF” by means of an
external “Control” or “Enable” ( EN ) signal input.
 This control signal can be either a logic “0” or a logic “1” type signal
resulting in the Tri-state Buffer being in one state allowing its output to
operate normally producing the required output or in another state were its
output is blocked or disconnected.
 A tri-state buffer requires two inputs. One being the data input and the other
being the enable or control input as shown.
 Bus Structure of the 8085
The 8085 Bus Buffering
Active-High Tri-state buffer
 An Active-high Tri-state Buffer such as the 74LS241 octal buffer, is activated
when a logic level “1” is applied to its “enable” control line and the data passes
through from its input to its output.
 When the enable control line is at logic level “0”, the buffer output is disabled and
a high impedance condition, Hi-Z is present on the output.
 Bus Structure of the 8085
The 8085 Bus Buffering
Active-Low Tri-state buffer
 An Active-low Tri-state Buffer is the opposite to the above and is activated when a
logic level “0” is applied to its “enable” control line. The data passes through from
its input to its output.
 When the enable control line is at logic level “1”, the buffer output is disabled and
a high impedance condition, Hi-Z is present on the output.
 Bus Structure of the 8085
The 8085 Bus Buffering
Tri-state Buffer Control
 The Tri-state Buffer is used in many electronic and microprocessor circuits
as to allow multiple logic devices to be connected to the same wire or bus
without damage or loss of data.
 For example, suppose we have a data line or data bus with some memory,
peripherals, I/O or a CPU connected to it. Each of these devices is capable
of sending or receiving data to each other onto this single data bus at the
same time creating what is called a contention.
 Bus Structure of the 8085
The 8085 Bus Buffering
Tri-state Buffer Control – cont’d
 Contention occurs when multiple devices are connected together because
some want to drive their output high and some low. If these devices start to
send or receive data at the same time a short circuit may occur when one
device outputs to the bus a logic “1”, the supply voltage, while another is
set at logic level “0” or ground, resulting in a short circuit condition and
possibly damage to the devices as well as loss of data.
 Digital information is sent over these data buses or data highways either
serially, one bit at a time, or it may be up to eight (or more) wires together
in a parallel form such as in a microprocessor data bus allowing multiple
tri-state buffers to be connected to the same data highway without damage
or loss of data as shown.
 Bus Structure of the 8085
The 8085 Bus Buffering
Address and data buffers
 Address and data buffers are used for bidirectional data transfer. They perform the
unidirectional data transfer when they send out the Least Significant Byte of the
address.
 These buffers are only used for increasing the driving capacity of the current.
Through the internal bus data goes to the buffers. The Least Significant Byte of the
address goes to the buffers from the internal address latch to the other.
 Hence the address or data are sent out on the address ranging from AD7 to AD0 and
can drive every external chips, like RAM, EPROM, and other peripheral chips
meant for carrying the work. Likewise, all the data received by the 8085
microprocessor from the outside is also buffered internally.
 Also in a practical microcomputer system, the driving capacity for the data pins,
after the internal buffering procedure, might not be satisfactory. So there will
always be external buffer chips to carry out the entire work.
 Bus Structure of the 8085
The 8085 Bus Buffering
8085 Bus Latching
 Latching is a method of decreasing the number of buses and increasing
computing efficiency of a microprocessor. For example the 8085
microprocessor requires 16 bit address and 8 bit data. For accessing all
addresses and data separately, we would require (16+8) = 24 bus lines. But
this may make the system bulky and also the control signal bits would
increase.
 The simple fundamental is that there remains 16 number of lines. First 8
lines work as both Address and Data bus while next 8 lines work only as
address bus. Depending on the need of microprocessor, it selects first 8 bus
lines as Address or Data but not both at same time using a special signal
called Address Latch Enable (ALE). This selection by the microprocessor
is called Latching in a microprocessor.
 Bus Structure of the 8085
The 8085 Bus Buffering
8085 Bus Latching
 ALE (Address Latch Enable): In the 8085, AD0 to AD7 lines are
multiplexed and the lower half (byte) of address (A0 – A7) is available only
during T1 of the machine cycle.
 This lower half of address lines are also necessary during T2 and T3 of
machine cycle to access specific location in memory or I/O port. This
means that the lower half of an address must be latched in T1 of the
machine cycle, so that it is available throughout the machine cycle.
 The latching of lower half of an address bus is done using external latch,
i.e. the ALE signal from 8085 Microprocessor.
 Bus Structure of the 8085
The 8085 Bus Buffering
8085 Bus Latching
IO Techniques
 IO Techniques
IO Structure of a Typical Microcomputer
 The IO devices connected to a microcomputer system provides an efficient
means of communication between the microcomputer system and the outside
world. These IO devices are commonly called peripherals and include
keyboards, CRT displays, printers and disks (floppy disk, hard disk and
Compact Disc (CD)).
 The characteristics of the IO devices are normally different from the
characteristics of the microprocessor. Since the characteristics of the IO devices
are not compatible with that of the microprocessor, interface hardware circuitry
between the microprocessor and IO device are necessary.
 There are three major types of data transfer between the microcomputer and an
IO device. They are as follows:
1) Programmed IO
2) Interrupt driven IO
3) Direct memory access (DMA)
 IO Techniques
IO Structure of a Typical Microcomputer – cont’d
 In programmed IO the data transfer is accomplished through an IO port and
controlled by software. In interrupt driven IO, the IO device will interrupt the
processor and initiate data transfer.
 In DMA, the data transfer between memory and IO can be performed by
bypassing the microprocessor. Each type of data transfer scheme mentioned
above, includes different methods of data transfer schemes.
 Figure 3.17 shows all the types of data transfer schemes in a microcomputer and
it can also be called IO structure of a microcomputer.
 IO Techniques
IO Structure of a Typical Microcomputer – cont’d

Fig. 3.17 : IO structure of a typical microcomputer

 IO Techniques
Memory Mapped (programmed) I/O Technique
 Memory mapped IO uses one address space for memory and I/O devices. In
other words, some addresses are assigned to memory while others are assigned
to store the addresses of IO devices. There is one set of read and write
instruction lines. The same set of instructions work for both memory and IO
operations. Therefore, the instructions used to manipulate memory can be used
for IO devices too.
I/O Mapped/Isolated IO/Standard IO/Port IO Technique
 IO mapped IO uses two separate address spaces for memory locations and for
IO devices. There are two separate control lines for both memory and IO
transfer. In other words, there are different read-write instruction for both IO and
memory. IO read and IO write are for IO transfer whereas memory read and
memory write are for memory transfer. IO mapped IO is also called port-
mapped IO or isolated IO.
 IO Techniques
Memory mapped vs IO Mapped Techniques
Memory Mapped I/O I/O mapped I/O
16-bit device address 8-bit device address
Data transfer between any general-purpose Data is transfer only between accumulator and
register and I/O port. I.O port
The I/O map is independent of the memory
The memory map (64K) is shared between
map; 256 input device and 256 output devices
I/O device and system memory.
can be connected
More hardware is required to decode 16-bit Less hardware is required to decode 8-bit
address address
Arithmetic or logic operation can be directly Arithmetic or logical operation cannot be
performed with I/O data directly performed with I/O data
Uses same address space for both memory Uses two separate address spaces for memory
and I/O devices and I/O devices
Uses the same instructions for both I/O and Uses separate instructions for read and write
memory operations instructions in I/O and memory
 IO Techniques
Interrupt driven I/O
 IO device interrupts processor when it is ready for data transfer – Processor can
be doing other tasks while waiting for Processor can be doing other tasks while
waiting for last data transfer to complete – very efficient.
 All IO in modern computers is interrupt driven.
Handshake controlled I/O
 Handshaking is an I/O control method to synchronize I/O devices with the
microprocessor.
 As many I/O devices accepts or release information at a much slower rate than
the microprocessor, this method is used to control the microprocessor to work
with a I/O device at the I/O devices data transfer rate.
 IO Techniques
Handshake controlled I/O – cont’d
Example
 Supposing that we have a printer connected to a system. The printer can print
100 characters/second, but the microprocessor can send much more information
to the printer at the same time.
 When the printer gets enough data to print it places a logic 1 signal at its Busy
pin, indicating that it is busy in printing. The microprocessor now tests the busy
bit to decide if the printer is busy or not.
 When the printer becomes free, it changes the busy bit to logic 0 and the
microprocessor again sends more data to be printed. This process of
interrogating the printer is called handshaking.
 IO Techniques
Polled I/O
 In polled I/O, the CPU must regularly check— or poll — each channel or
port in turn to determine if it has information for input or is ready to
accept data for output.
 A flag register can be used to check the port’s status.
 A port’s status is examined in case an action is required by the computer
 Polling is time consuming because the CPU must pause between
executing processing instructions and poll each port.
Jan 18 2023 IO Interfacing
By Dr. Ahuna

Interfacing IO and Peripheral Devices

 The IO devices are generally slow devices. So, they are connected to the system
bus through ports. The ports are buffer IC which is used to temporarily hold the
data transmitted from the microprocessor to IO device or to hold the data
transmitted from IO device to the microprocessor.
 To transfer data from the input device to the processor, the following operations
are performed:
1) The input device will load the data to the port.
2) When the port receives the data, it sends message to the processor to read the
data.
3) The processor will read the data from the port.
4) After the data has been read by the processor the input device will load the
next data into the port.
Jan 18 2023 IO Interfacing
By Dr. Ahuna
Example 1
 Interface an 8-bit DIP switch with the 8085 such that the address assigned to the
DIP switch is F0H.
Solution
 IN instruction is used to get data from DIP switch and store it in accumulator.
Steps involved in the execution of this instruction are:
1) Address F0H is placed in address lines A0 – A7 and a copy of it in lines A8 –
A15.

1) The IOR signal is activated (IOR = 0), which makes the selected input device
to place its data in the data bus.
2) The data in the data bus is read and stored in the accumulator
Jan 18 2023 IO Interfacing
By Dr. Ahuna
Example 1
Solution – cont’d
 A0 – A7 lines are connected to a NAND gate decoder such that the output of
NAND gate is 0.
 The output of NAND gate is ORed with the IOR signal and the output of OR
gate is connected to 1G and 2G of the 74LS244.
 When 74LS244 is enabled (See Figure 13), data from the DIP switch is placed
on the data bus of the 8085.
 The 8085 reads data and stores it in the accumulator. Thus data from DIP
switches is transferred to the accumulator.
Jan 18 2023 IO Interfacing
By Dr. Ahuna
Example 1
Solution – cont’d

Fig. 13 Interfacing of 8-bit DIP switch with 8085

Jan 18 2023
By Dr. Ahuna
Jan 18 2023
By Dr. Ahuna

Topic 3b

8085 Timing Diagrams