Module 4

Questions

1. A MN Flip Flop (FF) has 2 inputs M and N which are equivalent to

the J and K inputs of JK FF respectively. The output of MN FF is the
complement of JK FF output.
a. Tabulate the characteristic table of the FF
b. Tabulate the excitation table of the FF
c. Derive the characteristic equation for Q(t+1) in terms of Q(t),
M and N.
d. Using MN FF design a Mod 8 binary down counter.

2. Design a counter with the repeated binary sequence 1, 3, 5, 7, 2,

4, 8, 10, 12, 14 using SR Flip Flops. Treat unused states as don’t
cares. Write the Flip Flop input equations.

3. Derive the state diagram for an FSM that has an input w and an
output z. The machine has to generate z=1 when the previous
four values of w were 1001 or 1111; otherwise z=0. An example
of the desired behaviour is w 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 z
0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 Derive the next-state and
output equations for the obtained FSM.

4. Write the algorithm for bit counting circuit and draw its ASM
chart. With respect to this, differentiate traditional flow chart and
ASM chart. Also design the datapath circuit for the same and
draw the ASM chart for its control circuitry.

5. Explain the elements of ASM chart with their symbols.

6. Draw the 3-bit Johnson counter. Write the count sequence and
decoding logic required for the output

7. Derive the Flip Flop (FF) input equations for a synchronous BCD
down counter using JK FFs.

8.[1.] Distinguish between the following:

i) Synchronous and asynchronous clear

ii) Blocking and non-blocking assignments.

9. What is mealy and moore model?

10. Construct JK flipflop using D flipflop, 2 to 1 line mux and
inverter.

11. Design sequential circuit for serial adder using JK flip flop.

12. Design a sequential circuit with two JK flip flops A and B and 2
inputs E and x. If E =0 circuit remains in the same state
regardless of the value of x. When E=1, x=1, the circuit goes
through the state transition from 00 to 01 to 10 to 11 back to 00
and repeats. When E=1, x=0 the state transition from 00 to 11 to
10 to 01 to 00 and repeats.

13. Design a sequential circuit with two D-flip-flops A, B and one

input x. When x=0 the state of the circuit remains same. When
x=1, the circuit goes through the state transition from 00 to 01 to
11 to 10 back to 00and repeats.

14. Given, JA=x, KA=B’ JB=x, KB=A Draw the circuit diagram.
Derive state table, state equation and state diagrams.

15.[2.] Explain counter with unused state using example. (Shared in

whatsapp)

16. Given JA=Bx+B’Y’ KA=B’xy’ JB=A’x KB=A+xy’ Z=Ax’y’+Bx’y’

From this, draw logic diagram of the circuit, derive state equation
and state table.

17. With a circuit diagram, explain the working of a D flip flop with
a direct reset input.

18. Design a serial adder. Also, write the state table and state
diagram for the same.

19.[3.] Explain 5 stage switch tail ring counter with neat diagram.

20. A sequential circuit has two JK flip-flops A and B, one input x,

and one output y. It is described by the following output and flip-
flop input functions. JA=(Bx’)’ JB=((AB’)’(Bx)’)’ KA=(A’+B)’ KB=JB
Y=(ABx’)’ Draw the state table and state diagram.

21.[4.] Draw the circuit and waveforms (including the delay) for
modulo-6 counter with synchronous reset and asynchronous
 reset. Explain both the circuits properly to highlight the problem
associated with asynchronous reset.

22.[5.] Give behavioral VHDL code for negative edge triggered T-

flipflop. Use wait-until syntax.

23.[6.] Convert JK flip-flop to T flip-flop. Show all the design steps

24.[7.] Convert D flip-flop to JK flip-flop. Show all the design steps

Solutions

Answer 1:
Answer 2
.
Answer 3:

For the given question it is asked to derive a state diagram for an FSM
with one input w and one output z the sequences 1001or1111 using
overlapping method.

Explanation:

A State Diagram is a graphical representation of a FSM.

Let's have the following conditions;

→Input: w

→Output: z, where z=1 when the previous four values of w were

1001or1111; otherwise, z=0.

→Overlapping inputs are allowed, means that same bit can be part of two
successive patterns

State Diagram:- (Mealy Overlapping)

This is the state diagram for the given question which can detect
1001or1111 with overlapping input patterns.

Explanation:

In the state diagram, each state represents memory of the last input bits,
and then detect the sequence of four bits. And the state transition will be
based on input w, based on the value of w, the state transition will happen
and move to next state.

Therefore, the state diagram for detection of input sequence 1001or1111

is,
Answer 7:

Determine the state transitions for a BCD counter. The BCD sequence for a
down counter is 9 → 8 → 7 → ... → 0 → 9.

Create a state table for the BCD counter. Assign binary values to each BCD
digit: 9 (1001), 8 (1000), ..., 0 (0000). In a state table, list the current state
and the next state for each step in the BCD sequence. This helps in
determining the required transitions for the flip-flops.

Derive the JK inputs for each flip-flop using the excitation table. Use the
state transitions to find the required inputs. For JK flip-flops, the inputs can
be derived by comparing the current state and the next state.

The JK flip-flop has inputs J and K which determine the next state. The
excitation table for JK flip-flops helps in finding the logic needed to achieve
the desired state transitions. For example, if the current state is 1 and the
next state is 0, then J=0 and K=1.

Simplify the input equations using Karnaugh maps or Boolean algebra. For
each flip-flop, derive the simplest form of the input equations. Simplifying
the equations helps in reducing the complexity of the circuit. Techniques
like Karnaugh maps can be used to minimize the logic expressions for the
JK inputs.

The JK inputs for the BCD down counter are: J0 = Q3, K0 = 1; J1 = Q0, K1
= Q3; J2 = Q1Q0, K2 = Q3; J3 = Q2Q1Q0, K3 = 1.

Answer 10:

Answer 11:
We will use two JK flip-flops:

1. JK Flip-Flop for Sum (S): This will store the sum of the current
addition.

2. JK Flip-Flop for Carry (C): This will store the carry for the next
addition.

Step 5.1: Sum Flip-Flop (S)

The sum (S) depends on the current inputs A, B, and the carry-in Cin. The
equation for sum (S) is:

S=A⊕B⊕Cin

Step 5.2: Carry Flip-Flop (C)

The carry bit (C) depends on the current inputs A, B, and Cin.

The equation for carry (C) is:

C=(A⋅B)+(Cin⋅(A⊕B))

Now, let's design the JK flip-flops' input equations to generate the correct
states for sum and carry.

Step 5.3: JK Flip-Flop for Sum (S)

We need to derive the JK inputs for the flip-flop that will store the sum bit.
This can be done based on the full adder's behavior and using the
characteristic table of JK flip-flops. We define the JK inputs such that:

 JS=S

 KS=S’

Step 5.4: JK Flip-Flop for Carry (C)

For the carry bit, the JK flip-flop will store the carry for the next cycle. The
JK inputs for the carry flip-flop are determined by the carry output (C):

 JC=C

 KC=C’

Step 6: Final Circuit Design

Now we can summarize the circuit design:

1. Inputs: A, B, and Cin

2. JK Flip-Flop for Sum (S):

o Inputs JS and Ks are derived from the sum equation.

 o Output S stores the sum of the current bit addition.

3. JK Flip-Flop for Carry (C):

o Inputs JC and KC are derived from the carry equation.

o Output C stores the carry bit to be passed to the next addition.

This setup will allow the serial adder to add bits one by one, keeping track
of the sum and carry with each clock pulse.

Final Block Diagram

1. Inputs:

o A and B are serial input bits.

o Cin is the initial carry bit (usually 0).

2. Flip-Flops:

o First JK flip-flop for storing the sum S.

o Second JK flip-flop for storing the carry C.

3. Outputs:

o S for the sum output.

o C for the carry output (to the next addition).

Answer 12:

Given that two JK flip-flops A and B and two inputs E and F. If E=0, the
circuit remains in the same state regardless of the value of F. When E=1
and F=1, the circuit go through the state transitions from 00 to 01, to 10,
to 11, back to 00, and repeats. When E=1 and F=0, the circuit goes
through the state transitions from 00 to 11, to 10, to 01, back to 00, and
repeats.

State table
Boolean expressions for the flipflop inputs.

JA=m2+m7+d(8,9,10,11,12,13,14,15)KA=m10+m15+d(0,1,2,3,4,5,6,7)JB
=m2+m3+m10+m11+d(4,5,6,7,12,13,14,15)KB=m6+m7+m14+m15+d(
0,1,2,3,8,9,10,11)

Explanation:

Next state equations are written for the AB using the excitation table of JK
flipflop
Answer 13:
Answer 14:

To draw the circuit diagram, you need to understand the inputs and
outputs of the JK flip-flops. Given that JA = x and KA = B', JB = x and KB =
A, you can create the circuit by connecting these inputs to the JK flip-flops.
Use the outputs A and B from the flip-flops as part of the inputs for KA and
KB.

Explanation:

The JK flip-flop has two inputs, J and K, and two outputs, Q and Q'. The
given equations JA = x and KA = B' mean that the J input of flip-flop A is
connected to a constant high (x), and the K input is connected to the
inverted output of flip-flop B. Similarly, JB = x and KB = A mean that the J
input of flip-flop B is connected to a constant high, and the K input is
connected to the output of flip-flop A.

 Develop the state table by listing all possible states of flip-flops A

and B (00, 01, 10, 11) and determining the next state based on the
given JK inputs.

Explanation:

The state table shows the current state of the flip-flops and the next
state based on the inputs. For each current state (A, B), use the JK
inputs to determine what the next state (A+, B+) will be. Since JA =
x and JB = x, the J inputs are always high, meaning the flip-flops will
toggle if K is low.

 Derive the state equations from the state table. The state equation
for A+ is derived from KA = B', meaning A will toggle if B is 0.
Similarly, the state equation for B+ is derived from KB = A, meaning
B will toggle if A is 1.

Explanation:

State equations are derived from the conditions under which each
flip-flop toggles. The equation for A+ is A+ = JA * KA' + JA' * KA.
Since JA = x, A+ = KA'. For B+, B+ = JB * KB' + JB' * KB. Since JB =
x, B+ = KB'.

 Draw the state diagram by using the state equations to determine

transitions between states. Each state (00, 01, 10, 11) will have
transitions to other states based on the input conditions derived
from the state equations.

 Explanation:
 The state diagram visually represents the transitions between
different states of the flip-flops. Use arrows to indicate transitions
based on the state equations, showing how the circuit moves from
one state to another based on the inputs.

Conclusion

The correct state table, state equations, and state diagram are
derived from the given JK flip-flop input equations. The circuit
diagram is drawn by connecting the JK inputs according to the
equations JA = x, KA = B', JB = x, and KB = A.

Answer 16: