VLSI Design - VHDL Introduction

VHDL stands for very high-speed integrated circuit hardware description language. It is a
programming language used to model a digital system by dataflow, behavioral and structural
style of modeling. This language was first introduced in 1981 for the department of Defense
(DoD) under the VHSIC program.

Describing a Design

In VHDL an entity is used to describe a hardware module. An entity can be described using,

 Entity declaration
 Architecture
 Configuration
 Package declaration
 Package body

Entity Declaration

It defines the names, input output signals and modes of a hardware module.
Syntax −
entity entity_name is
Port declaration;
end entity_name;

An entity declaration should start with ‘entity’ and end with ‘end’ keywords. The direction will
be input, output or inout.

In Port can be read

Out Port can be written
Inout Port can be read and written
Buffer Port can be read and written, it can have only one source.
Architecture −
Architecture can be described using structural, dataflow, behavioral or mixed style.
Syntax −
architecture architecture_name of entity_name
architecture_declarative_part;

begin
Statements;
end architecture_name;
Here, we should specify the entity name for which we are writing the architecture body. The
architecture statements should be inside the ‘begin’ and ‘énd’ keyword. Architecture declarative
part may contain variables, constants, or component declaration.

Data Flow Modeling

In this modeling style, the flow of data through the entity is expressed using concurrent
(parallel) signal. The concurrent statements in VHDL are WHEN and GENERATE.
Besides them, assignments using only operators (AND, NOT, +, *, sll, etc.) can also be used to
construct code.
Finally, a special kind of assignment, called BLOCK, can also be employed in this kind of code.
In concurrent code, the following can be used −

 Operators
 The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);
 The GENERATE statement;
 The BLOCK statement

Behavioral Modeling

In this modeling style, the behavior of an entity as set of statements is executed sequentially in
the specified order. Only statements placed inside a PROCESS, FUNCTION, or PROCEDURE
are sequential.
PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code that are
executed sequentially.
However, as a whole, any of these blocks is still concurrent with any other statements placed
outside it.
One important aspect of behavior code is that it is not limited to sequential logic. Indeed, with
it, we can build sequential circuits as well as combinational circuits.
The behavior statements are IF, WAIT, CASE, and LOOP. VARIABLES are also restricted and
they are supposed to be used in sequential code only. VARIABLE can never be global, so its
value cannot be passed out directly.

Structural Modeling

In this modeling, an entity is described as a set of interconnected components. A component

instantiation statement is a concurrent statement. Therefore, the order of these statements is not
important. The structural style of modeling describes only an interconnection of components
(viewed as black boxes), without implying any behavior of the components themselves nor of
the entity that they collectively represent.
In Structural modeling, architecture body is composed of two parts − the declarative part
(before the keyword begin) and the statement part (after the keyword begin).
Logic Operation – AND GATE

X Y Z
0 0 0
0 1 0
1 0 0
1 1 1
VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;

entity and1 is
port(x,y:in bit ; z:out bit);
end and1;

architecture virat of and1 is

begin
z<=x and y;
end virat;

Waveforms

Logic Operation – OR Gate

 X Y Z
0 0 0
0 1 1
1 0 1
1 1 1
VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;

entity or1 is
port(x,y:in bit ; z:out bit);
end or1;

architecture virat of or1 is

begin
z<=x or y;
end virat;

Waveforms

Logic Operation – NOT Gate

X Y
0 1
1 0
VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity not1 is
port(x:in bit ; y:out bit);
end not1;

architecture virat of not1 is

begin
y<=not x;
end virat;

Waveforms

Logic Operation – NAND Gate

X Y Z
0 0 1
0 1 1
1 0 1
1 1 0
VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity nand1 is
port(a,b:in bit ; c:out bit);
end nand1;

architecture virat of nand1 is

begin
c<=a nand b;
end virat;

Waveforms

Logic Operation – NOR Gate

X Y z
0 0 1
0 1 0
1 0 0
1 1 0
VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity nor1 is
port(a,b:in bit ; c:out bit);
end nor1;

architecture virat of nor1 is

begin
c<=a nor b;
end virat;

Waveforms

Logic Operation – XOR Gate

X Y Z
0 0 1
0 1 1
1 0 1
1 1 0
VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity xor1 is
port(a,b:in bit ; c:out bit);
end xor1;

architecture virat of xor1 is

begin
c<=a xor b;
end virat;

Waveforms

Logic Operation – X-NOR Gate

X Y Z
0 0 1
0 1 1
1 0 1
1 1 0
VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity xnor1 is
port(a,b:in bit ; c:out bit);
end xnor1;

architecture virat of xnor1 is

begin
c<=not(a xor b);
end virat;

Waveforms
 VHDL Programming Combinational Circuits

VHDL Code for a Half-Adder

VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port (A,B:in bit; sum,carry:out bit);
end half_adder;

architecture data of half_adder is

begin
sum<= A xor B;
carry <= A and B;
end data;

Waveforms
VHDL Code for a Full Adder

Library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
port(a,b,c:in bit; sum,carry:out bit);
end full_adder;

architecture data of full_adder is

begin
sum<= a xor b xor c;
carry <= ((a and b) or (b and c) or (a and c));
end data;

Waveforms
VHDL Code for a Half-Subtractor

Library ieee;
use ieee.std_logic_1164.all;

entity half_sub is
port(A,B:in bit; D,Br:out bit);
end half_sub;

architecture data of half_sub is

begin
D<= A xor B;
Br<= ((not A) and B));
end data;

Waveforms
VHDL Code for a Full Subtractor

Library ieee;
use ieee.std_logic_1164.all;

entity full_sub is
port(A,B,C:in bit; D, Br:out bit);
end full_sub;

architecture data of full_sub is

begin
D <= A xor B xor C;
Br <= ((not A) and C) or ((not A) and B) or (B and C);
end data;

Waveforms
VHDL Code for a Multiplexer (Selector)

Library ieee;
use ieee.std_logic_1164.all;

entity mux is
port(S1,S0,I0,I1,I2,I3:in bit; Y:out bit);
end mux;

architecture data of mux is

begin
Y<= (not S0 and not S1 and I0) or
(S0 and not S1 and I1) or
(not S0 and S1 and I2) or
(S0 and S1 and I3);
end data;

Waveforms

VHDL Code for a Demultiplexer

Library ieee;
use ieee.std_logic_1164.all;

entity demux is
port(a,b,F:in bit; A,B,C,D:out bit);
end demux;

architecture data of demux is

begin
A<= ((not a) and (not b) and F);
B<= ((not a) and b and F);
C<= (a and (not b) and F);
D<= (a and b and F);
end data;

Waveforms
VHDL Code for a 8 x 3 Encoder

library ieee;
use ieee.std_logic_1164.all;

entity enc is
port(D0,D1,D2,D3,D4,D5,D6,D7:in bit; x,y,z: out bit);
end enc;

architecture vcgandhi of enc is

begin
x<=D4 or D5 or D6 or D7;
y<=D2 or D3 or D6 or D7;
z<=D1 or D3 or D5 or D7;
end vcgandhi;
Waveforms

VHDL Code for a 3 x 8 Decoder

library ieee;
use ieee.std_logic_1164.all;

entity dec is
port(A,B,C:in bit; Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7: out bit);
end dec;

architecture vcgandhi of dec is

begin
Y0<=(not A) and (not B) and (not C);
Y1<=(not A) and (not B) and C;
Y2<=(not A) and B and (not C);
Y3<=(not A) and B and C;
Y4<=A and (not B) and (not C);
Y5<=A and (not B) and C;
Y6<=A and B and (not C);
Y7<=A and B and C;
end vcgandhi;

Waveforms
 VHDL Programming for Sequential Circuits

VHDL Code for an SR Latch

library ieee;
use ieee.std_logic_1164.all;

entity srl is
port(r,s:in bit; q,qbar:buffer bit);
end srl;

architecture virat of srl is

signal s1,r1:bit;
begin
q<= r nand qbar;
qbar<= s nand q;
end virat;

Waveforms
VHDL Code for an SR Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity srflip is
port(r,s,clk:in bit; q,qbar:buffer bit);
end srflip;

architecture virat of srflip is

signal s1,r1:bit;
begin
s1<=s nand clk;
r1<=r nand clk;
q<= s1 nand qbar;
qbar<= r1 nand q;
end virat;

Waveforms
VHDL Code for a 4 - bit Up Counter
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(Clock, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end counter;

architecture virat of counter is

signal tmp: std_logic_vector(3 downto 0);
begin
process (Clock, CLR)

begin
if (CLR = '1') then
tmp < = "0000";
elsif (Clock'event and Clock = '1') then
mp <= tmp + 1;
end if;
end process;
Q <= tmp;
end virat;

Waveforms
VHDL Code for a 4-bit Down Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dcounter is
port(Clock, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end dcounter;

architecture virat of dcounter is

signal tmp: std_logic_vector(3 downto 0);

begin
process (Clock, CLR)
begin
if (CLR = '1') then
tmp <= "1111";
elsif (Clock'event and Clock = '1') then
tmp <= tmp - 1;
end if;
end process;
Q <= tmp;
end virat;

Waveforms
4-bit RIPPLE CARRY ADDER

Code for Full Adder

Code for 16-bit Ripple Carry Adder

VHDL code for 4-bit Binary Comparator

Library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity VHDL_Binary_Comparator is

port ( inp-A,inp-B: in std_logic_vector(3 downto 0);

greater, equal, smaller: out std_logic );

end VHDL_Binary_Comparator ;

architecture bhv of VHDL_Binary_Comparator is

begin

greater <= '1' when (inp-A > inp-B)

else '0';

equal <= '1' when (inp-A = inp-B)

else '0';

smaller <= '1' when (inp-A < inp-B)

else '0';

end bhv;
SHIFT REGISTER

library ieee;
use ieee.std_logic_1164.all;

entity shift_register is
port (
i_clk : in std_logic;
i_rstb : in std_logic;
i_data : in std_logic_vector(1 downto 0);
o_data : out std_logic_vector(1 downto 0));
end shift_register;

architecture rtl of shift_register is

signal r0_data : std_logic_vector(1 downto 0);
signal r1_data : std_logic_vector(1 downto 0);
signal r2_data : std_logic_vector(1 downto 0);
signal r3_data : std_logic_vector(1 downto 0);

begin

o_data <= r3_data;

p_sreg : process(i_clk,i_rstb)

begin

if(i_rstb='0') then
r0_data <= (others=>'0');
r1_data <= (others=>'0');
r2_data <= (others=>'0');
r3_data <= (others=>'0');

elsif(rising_edge(i_clk)) then
r0_data <= i_data;
 r1_data <= r0_data ;
r2_data <= r1_data ;
r3_data <= r2_data ;
end if;
end process p_sreg;
end rtl;

SERIEL TO PARALLEL CONVERTER

library ieee;
use ieee.std_logic_1164.all;

entity serial2parallel is
generic( G_N : integer:=8 );
port ( i_clk : in std_logic;
i_rstb : in std_logic;
i_sync_reset : in std_logic;
i_data_ena : in std_logic;
i_data : in std_logic;
o_data_valid : out std_logic;
o_data : out std_logic_vector(G_N-
1 downto 0));
end serial2parallel;

architecture rtl of serial2parallel is

signal r_data_enable : std_logic;
signal r_data : std_logic_vector(G_N-1 downto 0);
signal r_count : integer range 0 to G_N-1;

begin

p_serial2parallel : process(i_clk,i_rstb)

begin
if(i_rstb='0') then
 r_data_enable <= '0';
r_count <= 0;
r_data <= (others=>'0');
o_data_valid <= '0';
o_data <= (others=>'0');

elsif(rising_edge(i_clk)) then
o_data_valid <= r_data_enable;

if(r_data_enable='1') then
o_data <= r_data;
end if;

if(i_sync_reset='1') then
r_count <= 0;
r_data_enable <= '0';

elsif(i_data_ena='1') then
r_data <= r_data(G_N-2 downto 0)&i_data;

if(r_count>=G_N-1) then
r_count <= 0;
r_data_enable <= '1';
else
r_count <= r_count + 1;
r_data_enable <= '0';
end if;

else
r_data_enable <= '0';
end if;
end if;
end process p_serial2parallel;

end rtl;