Central Processing Unit (CPU) : Topic

Chapter 3
Central Processing Unit (CPU)

The TMS320C5x DSP central processing unit (CPU) can perform high-speed arithmetic within a short instruction cycle by means of its highly parallel architecture, which consists of the following elements:
Program controller Central arithmetic logic unit (CALU) Parallel logic unit (PLU) Auxiliary register arithmetic unit (ARAU) Memory-mapped registers
This chapter does not discuss the memory and peripheral segments, except in relation to the CPU.
Topic
3.1 3.2 3.3 3.4 3.5
Page
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Central Arithmetic Logic Unit (CALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Parallel Logic Unit (PLU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Auxiliary Register Arithmetic Unit (ARAU) . . . . . . . . . . . . . . . . . . . . . 3-17 Summary of Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3-1
Functional Overview
3.1 Functional Overview

The block diagram shown in Figure 31 outlines the principal blocks and data paths within the C5x. The succeeding sections provide further details of the functional blocks of the CPU. The internal hardware of the C5x executes functions that other processors typically implement in software or microcode. For example, the C5x contains hardware for single-cycle 16 16-bit multiplication, data shifting, and address manipulation. This hardware-intensive approach provides computing power previously unavailable on a single chip.
Table 31 presents a summary of the C5xs internal hardware. This summary table is alphabetized. The table includes the internal processing elements, registers, and buses. All of the symbols used in the table correspond to the the functional blocks illustrated in Figure 31, the succeeding block diagrams in this chapter, and the text throughout this document.
3-2
Functional Overview
Figure 31. Block Diagram of C5x DSP Central Processing Unit (CPU)
CLKMD1 CLKMD2 CLKMD3 IS DS PS RW STRB READY BR XF HOLD HOLDA IAQ BIO RS IACK MP/MC INT(14) PROGRAM BUS Software waitstates PDWSR IOWSR Program Controller 16 CWSR(5) X1 CLKOUT1 X2/CLKIN CLKIN2 PFC PAER MUX COMPARE MCS RD WE NMI Address 4 ROM MUX A15A0 Stack (8x16) PC PASR IREG BMAR ST0 ST1 PMST RPTC IMR IFR GREG BRCR TREG1(5) TREG2(4) Serial Port 1
Instruction RBIT PROGRAM BUS MUX D15D0
Serial Port 2
DATA BUS 7 LSB from IREG 3 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 CBCR(8) CBSR1 CBSR2 CBER1 CBER2 INDX 32 32 PRESCALER SFR(016) 32 Emulation DRB PRESCALER SFL(016) MULTIPLIER PREG(32) 32 MUX PSCALER (6,0,1,4) PLU TREG0 MUX Timer ST0 [DP] MUX 9 DBMR Time-Division Multiplexed Serial Port
DATA BUS
Buffered Serial Port
ST0 [ARP]
Host Port Interface
MUX I/O Ports PA0
ARCR
. . .
MUX ARAU MUX 32 Data/Program MUX SARAM Data/Program DARAM B0 MUX Data DARAM B2 B1 MUX MUX POSTSCALER (07) ST1 [C] 32 PROGRAM BUS DATA BUS ALU(32) 32 32
PA15
ACCH
ACCL 32
ACCB(32)
Notes: All registers and data lines are 16-bits wide unless otherwise specified. Not available on all devices.
3-3
Functional Overview
Table 31. C5x CPU Internal Hardware Summary

Symbol A15A0 ACC(32) ACCB(32) ACCH ACCL ALU(32) AR0AR7 ARAU ARB(3) ARCR ARP(3) BMAR BRAF(1) BRCR C CALU CBCR(8) CBER1, CBER2 CBSR1, CBSR2 CNF COMPARE D15D0 DATA BUS DBMR dma(7) DP(9) Name Address bus Accumulator Accumulator buffer Accumulator high byte Accumulator low byte Arithmetic logic unit Auxiliary registers Auxiliary register arithmetic unit Auxiliary register buffer bits Auxiliary register compare register Auxiliary register pointer bits Block move address register Block repeat active flag bit Block repeat counter register Carry bit Central arithmetic logic unit Circular buffer control register Circular buffer end registers Circular buffer start registers Configuration control bit Compare of program address Data bus Data bus Dynamic bit manipulation register Data memory address (immediate register) Data memory page pointer bits
3-4
Functional Overview
Table 31. C5x CPU Internal Hardware Summary (Continued)

Symbol DRB GREG HM(1) IFR IMR INDX INTM(1) IPTR(5) IREG MCS MP/MC MULTIPLIER MUX NDX(1) OV(1) OVLY(1) OVM(1) P-SCALER (6, 0, 1, 4) PAER PASR PC PFC PLU PM(2) PMST POSTSCALER(07) Name Direct data memory address bus Global memory allocation register Hold mode bit Interrupt flag register Interrupt mask register Index register Interrupt mode bit Interrupt vector pointer bits Instruction register Microcall stack Microprocessor/microcomputer bit Multiplier Multiplexer Enable extra index register bit Overflow bit RAM overlay bit Overflow mode bit Product shifter Block repeat program address end register Block repeat program address start register Program counter Prefetch counter Parallel logic unit Product shifter mode bits Processor mode status register Accumulator postscaling shifter
3-5
Functional Overview
Table 31. C5x CPU Internal Hardware Summary (Continued)

Symbol PREG(32) PRESCALER, SFL(016), SFR(016) PROGRAM BUS RAM(1) RPTC ST0, ST1 STACK SXM(1) TC(1) TREG0 TREG1(5) TREG2(4) TRM(1) XF(1) Name Product register Prescaling shifters Program bus Program RAM enable bit Repeat counter register Status registers Stack Sign-extension mode bit Test/control bit Temporary register (multiplicand) Temporary register (dynamic shift count) Temporary register (bit pointer in dynamic bit test) Enable multiple temporary registers bit External flag pin status bit
3-6

Central Processing Unit (CPU) : Topic

Uploaded by

Central Processing Unit (CPU) : Topic

Uploaded by

Chapter 3

Central Processing Unit (CPU)

Central Processing Unit (CPU)

3.1 Functional Overview

Instruction RBIT PROGRAM BUS MUX D15D0

Buffered Serial Port

Host Port Interface

MUX I/O Ports PA0

Central Processing Unit (CPU)

Table 31. C5x CPU Internal Hardware Summary

Table 31. C5x CPU Internal Hardware Summary (Continued)

Central Processing Unit (CPU)

Table 31. C5x CPU Internal Hardware Summary (Continued)

You might also like