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    Analog Assignment 7

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    simranjit28p
    Analog VLSI

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    Analog Assignment 7

    Uploaded by

    simranjit28p
    2 views5 pages
    Analog VLSI

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    © © All Rights Reserved

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    DOCX, PDF, TXT or read online from Scribd

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    Analog VLSI

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    2 views5 pages

    Analog Assignment 7

    Uploaded by

    simranjit28p
    Analog VLSI

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 5

    Indian Institute of Technology Roorkee

    Analog VLSI Circuit Design


    (ECC-537)

    (Final Project)

    Submitted to: Submitted by:


    Dr Bishnu Prasad Das Sagar
    24
    Simranjit Singh
    24915017
    Aim: Design of two-stage op-amp:

    Design a two-stage op-amp with miller compensation. Determine W and L for all transistors
    and the value of the compensation capacitor (Cc) for the following specifications:

    Gain > 70 dB
    Slew Rate >0.1 V/ns
    Supply voltage=1.8 V
    Load capacitance= 1 pF
    Input Common Mode Range= 0.9 V to 1.7 V
    CMRR>80 dB
    Gain bandwidth Product >100 MHz
    Phase margin>60°

    Do the calculation and characterize the following parameters in cadence SPECTRE:

    (a) Plot differential gain versus frequency (both magnitude and phase plot) using AC
    simulation. What is the unity gain bandwidth, and what is the phase margin through
    simulation?
    (b) Plot common mode gain and CMRR versus frequency.
    (c) Characterize the step response and the slew rate at the output for the following step inputs
    at In+.
    (i) 1μV (ii)1mV (iii)1V
    (d) Find the power dissipation in the op-amp.
    (e) Draw the layout of the two-stage op-amp. Extract the RC of the layout, simulate the RC-
    extracted layout, and report the differential gain, CMRR, GBP, and phase margin.

    Abstract: This report presents the design and simulation of a two-stage operational amplifier (op-amp)
    with Miller compensation, targeting high gain, stability, and speed for analog VLSI applications. The
    design specifications include a gain of over 70 dB, a gain-bandwidth product (GBP) exceeding 100
    MHz, and a phase margin greater than 60°, with a supply voltage of 1.8 V and a load capacitance of 1
    pF. Transistor sizing and compensation capacitor values were optimized to meet performance criteria.
    Simulations in Cadence SPECTRE verified key parameters such as differential gain, common-mode
    rejection ratio (CMRR), slew rate, and power dissipation, ensuring compliance with design goals.
    Introduction
    Operational amplifiers (op-amps) are fundamental building blocks in analog circuit design, widely used
    in applications ranging from signal amplification and filtering to more complex functions like analog
    computation and feedback control systems. Among various op-amp architectures, the two-stage op-
    amp is particularly favored for its ability to achieve high gain, wide bandwidth, and low power
    consumption, making it suitable for modern integrated circuit (IC) applications.
    A two-stage op-amp typically consists of a differential input stage followed by a high-gain output
    stage, with a compensation network to stabilize its frequency response. The differential input stage
    provides high input impedance, low offset voltage, and good common-mode rejection ratio (CMRR).
    The second stage amplifies the signal further, ensuring that the overall gain meets the desired
    specifications. However, these advantages come with stability challenges, especially in high-gain, high-
    speed applications.
    To address stability, Miller compensation is employed, a widely used technique where a compensation
    capacitor (denoted Cc) is connected between the output of the first stage and the input of the second
    stage. This approach shifts the non-dominant pole to a higher frequency, creating a single dominant
    pole that ensures a stable phase margin. The Miller effect effectively reduces the bandwidth of the first
    stage, improving stability without sacrificing gain or bandwidth.
    In this project, the goal is to design a two-stage op-amp with Miller compensation that meets the
    following performance criteria:
     Gain: Greater than 70 dB

     Gain-Bandwidth Product (GBP): Greater than 100 MHz

     Phase Margin: Greater than 60°

     Slew Rate: Greater than 0.1 V/ns

     CMRR: Greater than 80 dB

     Input Common-Mode Range (ICMR): 0.9 V to 1.7 V

     Supply Voltage: 1.8 V

     Load Capacitance: 1 pF

    The design process begins with the selection of transistor sizes (W/L) and the value of the
    compensation capacitor to achieve the specified gain and stability. The op-amp is simulated using
    Cadence SPECTRE, an industry-standard tool for IC design verification. Key performance
    parameters such as AC response, transient response, slew rate, power dissipation, and layout-extracted
    parasitics are characterized through simulations.
    This report highlights the methodology used to meet the design specifications, including transistor
    sizing calculations, Miller capacitor selection, and various simulation results. Furthermore, it discusses
    the impact of design choices on performance, focusing on stability, speed, and power efficiency.
    The successful completion of this project demonstrates the application of analog design principles in
    VLSI circuits and the importance of optimizing both performance and stability in op-amp architectures.
    This design process serves as a valuable learning experience in balancing competing design
    requirements, a crucial skill for analog VLSI design engineers.

    Design Methodology
    The design of a two-stage operational amplifier (op-amp) with Miller compensation follows a
    systematic approach to ensure that performance meets the specified criteria. The methodology involves
    several key steps: selecting appropriate transistor dimensions, determining the Miller compensation
    capacitor value, and verifying the design through simulation in Cadence SPECTRE. Below is a step-
    by-step breakdown of the design process.
    1. Design Specifications and Initial Requirements
    The following specifications serve as the foundation for the design:
     Gain: > 70 dB

     Gain-Bandwidth Product (GBP): > 100 MHz

     Phase Margin: > 60°


     Slew Rate: > 0.1 V/ns

     CMRR: > 80 dB

     Supply Voltage: 1.8 V

     Load Capacitance: 1 pF

     Input Common-Mode Range (ICMR): 0.9 V to 1.7 V

    2. Transistor Sizing (W/L Ratio Calculation)


    To achieve the desired gain, bandwidth, and slew rate, careful transistor sizing is essential. The
    following steps were taken:
     Input Pair Design: The sizing of the differential pair M 1 and M2 are determined from
    Minimum input Common Mode Range (ICMR) or using Gain-bandwidth Product. The
    differential input transistors were sized to ensure high transconductance (g m) and low input-
    referred noise.

     Second Stage Design: The sizing of the M6 Transistor is calculated from Gain and size of M 3
    and M4. The second stage transistors were optimized for high output impedance and large
    voltage gain.

     Current Mirror Design: The sizing of the mirror transistors M 1 and M2 are determined from
    Maximum input Common Mode Range (ICMR). The biasing current sources were designed
    for stability and minimal power consumption.

     W/L Ratios Calculation: The transistor width-to-length ratios were determined using standard
    equations.

    3. Miller Compensation Capacitor (Cc) Calculation


    The Miller compensation capacitor C c stabilizes the op-amp by introducing a dominant pole and
    increasing the phase margin. It is calculated using:
    Where gm1 is the transconductance of the first stage and P 1 is the target dominant pole frequency. The
    capacitor value is fine-tuned during simulations to achieve the required phase margin.

    4. AC Simulation for Frequency Response


     An AC simulation was conducted to evaluate the differential gain and phase across
    frequencies.

     The unity-gain bandwidth and phase margin were extracted to verify compliance with stability
    and bandwidth requirements.

    5. Transient Analysis for Slew Rate and Step Response


     Step inputs of varying amplitudes (1 µV, 1 mV, 1 V) were applied to the input to observe the
    slew rate and step response.
     The slew rate was measured as the maximum rate of output voltage change, ensuring it
    exceeded 0.1 V/ns.

    6. Common-Mode Gain and CMRR Measurement


     Common-mode gain was simulated and compared with differential gain to calculate the CMRR
    across frequencies, ensuring it met the 80 dB threshold.

    7. Power Dissipation Calculation


    Power dissipation was determined by measuring the total current drawn from the supply voltage. The
    design was optimized to minimize power while maintaining performance.

    8. Layout Design and RC-Extraction


     The op-amp layout was created following best practices for minimizing parasitic and matching
    critical transistors.

     RC-extraction was performed to model parasitic resistances and capacitances accurately. Post-
    layout simulations were run to verify that the extracted design met all specifications, including
    gain, GBP, phase margin, and CMRR.

    This structured approach ensures that the two-stage op-amp design meets the specified performance
    targets while maintaining stability and efficiency.

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