III Mh Adc Lab (b20es0303) Manual

School of Electronics and
Communication Engineering
Program : B.Tech. in Mechatronics
Analog and Digital Circuits Lab
LABORATORY MANUAL
III Semester
2021-25
Rukmini Educational
Charitable Trust
School of Mechanical Engineering
VISION
“Aspires to be recognized globally for outstanding value based education in mechanical and allied areas and
research leading to well-qualified engineers, who are innovative, entrepreneurial, successful in their career and
committed to the development of the country.”
MISSION
1. To impart quality education to the students and enhance their skills to make them globally
competitive engineers in mechanical and allied areas.
2. To promote multidisciplinary study, cutting edge research and expand the frontiers of engineers’
profession in mechanical and allied areas.
3. To create state-of-art facilities with advanced technology for providing students and faculty with
opportunities for innovation, application and dissemination of knowledge.
4. To prepare for critical uncertainties ahead for mechanical engineering and allied areas and to
face the challenges through clean, green and healthy solution.
5. To collaborate with industries, institutions and such other agencies nationally and internationally
to undertake exchange programs, research, consultancy and to facilitate students and faculty
with greater opportunities for individual and societal growth.
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

The After few years of graduation, the graduates of B.Tech Mechatronics Engineering will:
PEO 1: Work as an Engineer in mechanical and electronics sectors in multidisciplinary role
PEO 2: Act as an administrator in public, private and government organizations or start own business
with further training and education.
PEO 3: Pursue higher education to work in colleges, universities as professors or as scientists in
research establishments.
PEO 4: Adopt lifelong learning philosophy for continuous improvement in working environment either
as a member of team or lead the team.
PROGRAM SPECIFIC OUTCOMES (PSOs)

On successful completion of the program, the graduates of B.Tech. Mechatronics Engineering will be
able to:
PSO 1: Apply mechatronics engineering knowledge and skills in Design, Manufacturing, Automation
and Electronics to obtain realistic outcomes.
PSO 2: Identify, formulate, analyze and solve problems in mechatronics engineering and allied
domains.
PSO 3: Conduct investigations in Mechanical and Electronics Engineering and allied areas to provide
optimal and sustainable solutions
PROGRAM OUTCOMES (POs)
On successful completion of the program, the graduates of B.Tech. Mechatronics Engineering will be
able to:
PO-1: Engineering Knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, to solve problems in mechatronics engineering.
PO-2: Problem Analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics, natural
sciences and engineering sciences.
PO-3: Design/Development of Solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate consideration
for the public health and safety, and the cultural, societal, and environmental considerations.
PO-4: Conduct Investigations of Complex Problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions for complex problems.
PO-5: Modern Tool Usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modelling to complex engineering activities with an
understanding of the limitations.
PO-6: The Engineer and Society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
PO-7: Environment and Sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
PO-8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms
of the engineering practice.
PO-9: Individual and Team Work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
PO-10: Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and write effective
reports and design documentation, make effective presentations, and give and receive clear instructions.
PO-11: Project Management and Finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and leader
in a team, to manage projects and in multidisciplinary environments.
PO-12: Life-long Learning: Recognize the need for, and have the preparation and ability to engage in
independent and lifelong learning in the broadest context of technological change.
REVA University School of ME
CONTENTS
Sl. Title Page No.

No.
1 Course Objectives & Outcomes 03
2 Laboratory Safety 06
3 Component Details 7
4 Draw an input & output characteristics of common emitter 10

configuration.
Design a Single stage BJT CE Amplifier and obtain frequency
5 response curve and find Bandwidth, Input & Output 14
Impedances.
Design a Two stage voltage series BJT Amplifier and Obtain
6 frequency response curve, also find Bandwidth. 18
Design a BJT Hartley Oscillator & Colpitt’s Oscillator for
7 21
frequency ≥100kHz.
8 Design an OPAMP Inverting & Non Inverting Amplifier. 26
9 Introduction to Digital Electronics 29

10 Study Experiment: Realization of Logic Gates 37
11 Realization of parallel Adder and Subtractor. 41
Realization of 4:1 MUX and 1:4 DEMUX using basic/universal
13 48
gates.
Arithmetic circuit realization (Half/Full, Adder/Subtractor)
14 53
using MUX.
Construction and verification of JK master slave, T, D flip flop
15 61
using logic gates.
16 Construction and realization of 3- bit ripple up/down counter 67
using IC 7476 and other logic gates.
18 Specifications of Equipment’s 71
Analog & Digital Electronics lab (B22ES0305) SEM 3 2

Course Title Analog and Digital Circuits Course Type Integrated

III
Course Code B20ES0303 Credits 4 Class Semester
Contact Work Total Number of
TLP Assessment
Load Classes
Credits Hours in Weightage
Course Per Semester
Structure Theory
3 3 3
Practice 1 2 2 Theory practical IA SEE

Hours Hours
Tutorial 0 0 0
Total 4 5 5 39 26 50 % 50 %
COURSE OBJECTIVE (S)
1. Understand how Bipolar Junction transistors are modeled and how the models are
used in the design and analysisof useful circuits.
2. Perform a load-line analysis of the most common BJT configurations.
3. Become acquainted with the design process for BJT biasing.
4. Apply concepts for the design of Amplifiers
5. Analyze the concepts of Oscillator circuits.
6. Illustrate Boolean laws and systematic techniques for minimization of expressions.
7. Demonstrate the methods for simplifying Boolean expressions.
8. Familiarize the commonly used terms like min-term, canonical expression, SOP etc.
9. Introduce the Basic concepts of combinational and sequential logic.
COURSE OUTCOMES (COs)
After the completion of the course, the student will be able to:
CO Course POs PSOs
Outcomes
CO1 Develop the capability to analyze and design simple circuits containing 1-6 1,2
non-linear
elements such as transistors using the concepts of load lines and operating
points
CO2 Compute the DC values of voltages and currents in biasing circuits. 1-5 1,2
CO3 Analyze the working of Operational Amplifier, oscillators and their 1- 1,2
Characteristics. 5,10
CO4 Construct the K-map from a Boolean expression and to find the minimal 1-5 1,2
SOP/POS
forms
CO5 Design digital circuits using gates, encoders and decoders. 1,4 1,2
Determine the output and performance of given combinational and
CO6 sequentialcircuits. 1,5 1,2

PRACTICE:
Sl. Title of the Experiment Tools and Expected
No Techniques Skill
/Ability
Draw input & output characteristics of common emitter Spring board,
1. configuration. multimeters,
Trainer kit,
Design a Single stage BJT RC Coupled Amplifier and Spring board, CRO Frequency response curve
obtain frequency response curve and find Trainer kit, Ohms and find Bandwidth, Input&
2 Bandwidth,Input & Output Impedances. Law, Fall of Output Impedances.
Resistance.
Design a Two stage voltage series BJT Amplifier and Frequency response curve
3. Obtain frequency response curve, also find Bandwidth, and find Bandwidth, Input&
Input & Output Impedances. Spring board, CRO Output Impedances.
Design a BJT Hartley & Colpitts’s Oscillators for
4. frequency ≥100kHz. Spring board, CRO Frequency of an
Oscillator
5. Design an OPAMP Inverting & Non-Inverting Amplifier. Spring board, CRO Amplitude and Phase
Realization of basic gates, XOR and XNOR gates using Design and circuit
6. NAND & NOR.
IC Trainer Kit debugging. Working in
a team
Realization of parallel Adder and Subtractor using Design and circuit
7. IC Trainer Kit Debugging. Working in a
IC7483.
team
Realization of 4:1 MUX and 1:4 DEMUX using Design and circuit
8. IC Trainer Kit debugging. Working in
basic/universal gates.
a team
Design and circuit
Arithmetic circuit realization (Half/Full,
9. IC Trainer Kit debugging. Working in a
Adder/Subtractor)using MUX.
team
Design and circuit
Construction and verification of JK master slave, T, D
flip-flop using logic gates.
team
Design and circuit
Construction and realization of 3- bit ripple up/down
counter using IC 7476 and other logic gates.
team
Challenge Experiments:
1. Voltage follower and summers using uA741 op-amp.

2. Square and triangular waveform generation using uA 741 op-amp.
3. Design and realize a 3-bit synchronous up counter using D flip- flops.
4. Perform above experiments using any Suitable Simulator.

Use symbols properly.

1. Tabular column and circuit diagrams should be drawn with pencil & all entries in the
tabular form should be made with pen.
2. Draw the graph in the lab itself, if the graph is correct then only paste in the record.
Every week you have to submit the completed record without fail.
3. Hand writing in the record should be neat.
4. Ensure no mistakes in circuit diagram, graph sheet & result.
5. Take the signature in the observation book by the concerned faculty before you leave
the lab.
6. Well prepare before you come to the lab about the experiment you are conducting.
7. Always clarify the doubts related to the experiment, so that same will be useful for
viva exam.
8. Focus on the Design, Connections, Procedure, Safety, Result Analysis, Application,
Future enhancement etc.

Laboratory Safety
General precautions:
 Avoid any circuit that may lead to electrical shock
 All electrical wires protected by MCB, ELCB, and fuses.
 Be careful in using electrolytic capacitors and arcing circuits that have a potential
explosion and may cause blindness and severe burns.
 Be careful about burning components, and arcing may lead to a fire.
 Use of fire extinguishers in case of fire hazards
Precautions to be taken when preparing a circuit:

 While circuit connection, students are advised to reduce/switch off power supplies
 Students are allowed to power on the supply only after verification of faculty/staff
 Check for all the circuit connections before powering the circuit to avoid shorting
or ground looping that may lead to electrical shocks or damage to equipment.
 Check if any connections are leading to a short circuit in two different voltage
levels.
 Check if you have connected load at the output.
Other Precautions:
 No loose wires or metal pieces should be lying on the table or near the circuit to
cause shorts and sparking.
 Avoid using long wires that may get in your way while making adjustments or
changing leads.
 Keep high voltage parts and connections out of the way from accidental touching
and from any contacts to test equipment or any components connected to other
voltage levels.
 Be Aware of bracelets, rings, metal watchbands, and loose necklaces (if you are
wearing any of them); they conduct electricity and can cause burns. Please do not
wear them near an energized circuit.
 When working with energized circuits (while operating switches, adjusting controls,
adjusting test equipment), use only one hand while keeping the rest of your body
away from conducting surfaces.

Component Details
Colour coding of 4 Band Carbon Resistors
B.B. ROY of Great Britain had a Very Good Wolf.

The above mnemonics for the order: Black Brown Red Orange Yellow Green Blue
Violet Grey and White.
Decoding the value of Carbon resistors:

1. Hold the resistor so that the colour bands are at the left end of the resistor.
2. Write down the numeric value of the First Band.
3. Write down the numeric value of the second band at the right of the first
numeric.
4. Read the numeric value of the third band & write down those many zeros at
the right of the third numeric.
The most common types of resistors are the E12 and E24 series. The E12 series of
resistors are available in twelve resistance values per decade. The E24 series are
available in twenty four resistance values per decade.
E12 Series: 10,12,15,18,22,27,33,39,47,56,68,82, 100, 120, 150, 180, 220, 270,

330, 390, 470, 560, 680, 820 Ohms.
E24 Series: 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51,
56, 62, 68, 75, 82, 91. • 100, 110, 120, 130, 150, 160, 180, 200, 220, 240, 270, 300,
330, 360, 390, 430, 470, 510, 560, 620, 680, 750, 820, 910 Ohms.

Standard commercial Values of E12 series Carbon resistors:
Ohms Kilo Ohms Mega Ohms

1 10 100 1 10 100 1 10
1.2 12 120 1.2 12 120 1.2 12
1.5 15 150 1.5 15 150 1.5 15
1.8 18 180 1.8 18 180 1.8 18
2.2 22 220 2.2 22 220 2.2 22
2.7 27 270 2.7 27 270 2.7
3.3 33 330 3.3 33 330 3.3
3.9 39 390 3.9 39 390 3.9
4.7 47 470 4.7 47 470 4.7
5.6 56 560 5.6 56 560 5.6
6.8 68 680 6.8 68 680 6.8
8.2 82 820 8.2 82 820 8.2
Terminal identification of Transistors

SL/SK-100, BC-107,108, CL/CK-100, 2N2222 Series:
Transistors with different packages:

Do it yourself
 Identify the values of Resistors by Color Coding.
 Identify the values of Capacitors
 Identify the terminals of Transistor
 Know the specifications of Transistor
 Download the specification sheet of Transistor on internet and read the
Specification Parameters
 Learn to test Transistor by using DMM
 Learn the applications of the circuit & Importance of Impedance
measurement.
Activity
 Design Amplifier circuits for different values of Ic / Vcc Rig up the circuit &
Measure DC Condition. Find bandwidth by plotting frequency response curve.
Measure Input & Output Impedances.
PIN DETAILS 0F µA 741:

Experiment # 1: BJT CHARACTERISTICS (CE CONFIGURATION)

AIM: To plot the input and output characteristics of a transistor connected in
Common Emitter Configuration.
COMPONENTS REQUIRED: Transistor BC 107, Resistor 100 kΩ, 1kΩ, DC Ammeter,

multimeters, Bread Board, power supply, Connecting Wires
THEORY: In common emitter configuration the emitter is common to both input

and output. For normal operation the Base-Emitter junction is forward biased and
base-collector junction is reverse biased. The input characteristics are plotted
between IB and VBE keeping the voltage VCE constant. This characteristic is very
similar to that of a forward biased diode. The input dynamic resistance is
calculated using
ri = Δ VBE / Δ IB at constant VCE.
The output characteristics are plotted between IC and VCE keeping IB constant.
These curves are almost horizontal. The output dynamic resistance is given by,
ro = ΔVCE / Δ IC at constant IB.
At a given operating point, we define DC and AC current gains (beta) as follows
Current gain β = Δ IC/ Δ IB at constant VCE.
CIRCUIT DIAGRAM:

Ideal Graph:
Input Characteristics Output Characteristics
PROCEDURE:
INPUT CHARACTERISTICS
1. Connect the circuit as per the circuit diagram.

2. For plotting the input characteristics the output voltage V CE is kept constant at
1V and for different values of VBE . Note down the values of I C
3. Repeat the above step by keeping VCE at 2V and 4V.
4. Tabulate all the readings.
5. plot the graph between VBE and IB for constant VCE
OUTPUT CHARACTERISTICS:
1. Connect the circuit as per the circuit diagram
2. For plotting the output characteristics, the input current I B is kept constant at
10μA and for different values of VCE note down the values of IC
3. Repeat the above step by keeping IB at 20 μA, 50 μA 75 μA .
4. Tabulate the all the readings.
5. Plot the graph between VCE and IC for constant IB.

TABULAR FORM:
INPUT CHARACTERISTICS:
VCE = 1 V VCE= 2 V VCE= 4 V
S. RPS
No. Voltage VBE IB VBE IB VBE IB
(V) (µA) (V) (µA) (V) (µA)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
OUTPUT CHARACTERISTICS:
IB = 10 µA IB = 20 µA IB = 50 µA
S. RPS
No. Voltage VCE IC VCE IC VCE IC
(V) (mA) (V) (mA) (V) (mA)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

CALCULATIONS:
a) Input characteristics:
Input resistance ri = Δ VBE / Δ IB at VCE constant
=
b) Output characteristics:
Output dynamic resistance ro = ΔVCE / Δ IC at IB constant
=
Current gain β = Δ IC / Δ IB at VCE constant
=
PRECAUTIONS:
1. Connections must be given very carefully.
2. Switch-on the power only after thorough checking of all the connections.
3. Readings should be noted without parallax error.
4. The applied voltage, current should not exceed the maximum rating of the
given transistor.
RESULT:

Experiment # 2: Single Stage R-C Coupled BJT Amplifier

Aim: Design a single stage R-C coupled BJT CE amplifier and obtain frequency
response curve and to the find Bandwidth, Input & Output Impedances.
Components/Instruments Required: Transistor, Capacitors, Resistors, Power

supply, Signal Generator, Multimeters, DRB, CRO Probes, Connecting wires etc.
R-C Coupled BJT Amplifier

Circuit Diagram:
Design: Design a voltage divider bias amplifier for Ic=4mA by choosing transistor
having hfe=100
Given IC = 4 mA and hfe = 100 Let Vcc = 12 V. VCE= 1/2VCC
Assuming VE= Vcc

12
 2V
6 6
We Know VE=IE x RE =2V
RE = 2  2  2  500Ω
IE IC 4mA
Choose RE = 470Ω
Applying KVL to the Collector Emitter loop to find RC
VCC ICRC  VCE  VE  0

VCC  VCE  VE
R C
IC

RC  12  6  2 = 1kΩ
4mA
VB  VBE  VE = 0.7+2 = 2.7V
VV R2
B CC
R1 R2
2.7  R2

12 R1  R2

R2
0.225 
R1  R2
R2=0.225R1+0.225R2
0.775R2=0.225R1
Let R2 = 4.7kΩ
R1 = 16.18kΩ Choose 15kΩ
Bypass capacitor CB and Coupling capacitors CC1 and CC2
1
Let XCE = RE at frequency f = 100 Hz
10
1 R
= E
2  f CE 10
CE = 72.3 F
Select CE = 100 F
Also use CC1 and CC2 = 0.47 F (Ceramic)
Ideal Graph:

Procedure:
1. Connections are made as shown in circuit diagram.
2. Measure the D.C. Bias condition.
3. The input voltage Vin is adjusted to a convenient value (Approximately 20 to
40 mV) within the distortion less limit and value must be kept constant
throughout the experiment.
4. Frequency of the input signal is varied from 100Hz to 2MHz in Decade steps
and at each step, corresponding output Vo peak to peak is noted down.
5. All readings are tabulated and graph of Voltage gain in dB V/s frequency is
drawn on a Semi-Log sheet.
6. 3dB bandwidth is determined from the frequency response curve.
7. Measure Input & Output Impedances.
Observations:
VBE= Volts. VCE= Volts. (Q – Point Voltage)
Tabular Column:
Input Voltage Vin= 20 mVpp
Gain Gain
Sl. Frequency Vo in dB=20 Sl. Frequency Vo in dB=20
# in Hz. Volts. log10 # in Hz. Volts. log10
(Vo/Vin) (Vo/Vin)
1 100 Hz 20 20 kHz
2 200 Hz 21 30 kHz
3 300 Hz 22 40 kHz
4 400 Hz 23 50 kHz
5 500 Hz 24 60 kHz
6 600 Hz 25 70 kHz
7 700 Hz 26 80 kHz
8 800 Hz 27 90 kHz
9 900 Hz 28 100 kHz
10 1kHz 29 200 kHz
11 2 kHz 30 300 kHz
12 3 kHz 31 400 kHz
13 4 kHz 32 500 kHz
14 5 kHz 33 600 kHz
15 6 kHz 34 700 kHz
16 7 kHz 35 800 kHz
17 8 kHz 36 900 kHz
18 9 kHz 37 1 MHz
19 10 kHz 38 2 MHz

To measure Input Impedance:
1. A DRB is connected in series with the input as shown in figure.

2. In the mid frequency region (where the gain is constant around 20KHz.) with
Ri= 0, (i.e., all the knobs of DRB in Zero position.) the output voltage is
measured.
3. Now the DRB resistance is increased from lower value to higher value till the
output voltage falls to half of the initial value.
4. The corresponding DRB value gives the input impedance.
To measure Output Impedance:
1. A DRB is connected across the output as shown in figure.

2. In the mid frequency region (where the gain is constant around 20KHz.) with
Ro = max, (i.e., all the knobs of DRB in Maximum position.) the output voltage
is measured.
3. Now the DRB resistance is decreased from higher value to lower value till the
output voltage falls to half of the initial value.
4. The corresponding DRB value gives the input impedance.
Result Analysis:
Mid-band Gain in dB =
Bandwidth =
Input Impedance Zi =
Output Impedance Zo =

Experiment # 3: Design a two stage R-C Coupled BJT CE voltage series

amplifier
Aim: To design & test a two stage R-C Coupled BJT CE voltage series amplifier and
determine the gain, Frequency response, input and output impedances.
Components/Instruments Required: Transistors, Capacitors, Resistors, CRO, Power
supply, Signal generator, Connecting Wires, CRO Probes etc.
Circuit diagram:
Design:
Design the voltage divider bias circuit for Ic=4mA & Vcc=12V
Given IC = 4 mA and Vcc = 12 V, Choose hfe = 100, VCE = ½ Vcc = 6V
Assuming VE= Vcc

12
 2V
6 6
We Know VE=IE x RE =2V

RE = 2  2  2  500Ω Choose RE = 470 Ω
IE IC 4mA
Applying KVL to the Collector Emitter loop to find RC
VCC ICRC  VCE  VE  0

VCC  VCE  VE
R C
IC
RC  12  6  2 = 1kΩ
4mA
VB  VBE  VE = 0.7+2 = 2.7V
VB  V CC R2
R1  R2

2.7  R2

12 R1  R2
R2
0.225 
R1  R2
R2=0.225R1+0.225R2
0.775R2=0.225R1
Let R2 = 4.7kΩ
R1 = 16.18kΩ Choose 15kΩ
Design for II stage is same as that of first stage Use 470Ω as RE
Let CE=47µF (Emitter by-pass Capacitor) for both the stages.
Coupling Capacitors CC1 = CC2 = CC3 = 0.47µF
Procedure:
1. Connections are made as shown in circuit diagram.
2. Measure the D.C. Bias condition.
3. The input voltage Vin is adjusted to a convenient value (Approximately 20 to
40 mV) within the distortion less limit and value must be kept constant
throughout the experiment.
4. Frequency of the input signal is varied from 100Hz to 2MHz in Decade steps
and at each step, corresponding output Vo peak to peak is noted down.
5. All readings are tabulated and graph of Voltage gain in dB V/s frequency is
drawn on a Semi-Log sheet.
6. 3dB bandwidth is determined from the frequency response curve.
7. Measure Input & Output Impedances.
Ideal Graph:

Tabular Column:
Vi = mV
Gain dB=20
Sl. Frequency Vo in Gain dB=20 Sl. Frequency Vo in
log10
# in Hz. Volts. log10 (Vo/Vin) # in Hz. Volts.
(Vo/Vin)
1 100 Hz 20 20 kHz
2 200 Hz 21 30 kHz
3 300 Hz 22 40 kHz
4 400 Hz 23 50 kHz
5 500 Hz 24 60 kHz
6 600 Hz 25 70 kHz
7 700 Hz 26 80 kHz
8 800 Hz 27 90 kHz
9 900 Hz 28 100 kHz
10 1kHz 29 200 kHz
11 2 kHz 30 300 kHz
12 3 kHz 31 400 kHz
13 4 kHz 32 500 kHz
14 5 kHz 33 600 kHz
15 6 kHz 34 700 kHz
16 7 kHz 35 800 kHz
17 8 kHz 36 900 kHz
18 9 kHz 37 1 MHz
19 10 kHz 38 2 MHz
To Measure Input And Output Impedance:

Procedure is same as in Experiment No.1
Measure Zi and Zo compare the values with single Stage Amplifier.
Result:
Mid-band Gain in dB =
Bandwidth =
Input Impedance Zi =
Output Impedance Zo =

Experiment # 4: BJT Hartley and Colpitt’s Oscillators.
a. Hartley oscillator
Aim: Design a BJT – Hartley Oscillator for fo = 100 kHz.
Circuit Diagram:
Note: In Multisim 14 Simulator use Transistor 15CMH-TL-E to simulate the circuit.

Since SL 100 is not available.
Construction: The Hartley oscillator consists of a BJT- CE amplifier with tank circuit.
The resistors R1, R2, RC& RE provide necessary bias conditions for the circuit.
Capacitor CE provides A. C. ground thereby preventing any signal degeneration. This
also provides temperature stabilization. The function of CC 1& CC2 is to block D. C.
and to provide an A. C. path.
The frequency network is a parallel resonant circuit consisting of Inductors L 1, L2&
Capacitor C. the junction of L1& L2 is earthed. One side of L 1 is connected to base
via CC1 and other end is connected to emitter via C E. So L1 is in the input circuit.
Similarly one end of L2 is connected to oscillator via CC2 and other end is connected
to emitter via CE. So L2 is in the output circuit. The two parts are inductively coupled
& forms an auto transformer.
Circuit Working: When a collector voltage is switched “ON”, a transient current is

produced in the tank circuit. The oscillating current in the tank circuit produces A.C.
voltage across L1. In this way a feedback between output and input circuits is
accomplished through auto transformer action. So there is a phase reversal of 180 0
between output & input. The common emitter amplifier also produces a further 1800
phase shift between input and output voltages. Thus total phase shift becomes 3600.

Ultimately a state of equilibrium is reached where the losses in the circuit are made
by consuming power from the power supply. This makes the feedback +ve which is
the essential condition for oscillations. When the loop gain ‫׀׀‬Aβ‫ ׀׀‬of the amplifier is
greater than 1, oscillations are sustained and frequency of oscillations is determined
in the circuit. The frequency of oscillations is given by:
f = 1 / 2√ LeffX C where Leff= L1 + L2
Hartley oscillator is very popular and is commonly used as a local oscillator in Radio
receivers. The Hartley oscillator is extensively used in all broadcast bands including
FM 88 to 108MHz.
Dis-Advantages:
 Harmonic rich content at the output due to inductances.
Design of Amplifier:
VCE=5V, IC=2mA, VCC=2VCE=10V.
1 1
V   V  10  1V
RE
10 CC 10
VRE 1
RE =   500Ω . Choose 470Ω.
IC 2mA
RC = = 2kΩ. Choose 2.2 kΩ
Assume hfe =50

I 2mA
I  C   0.04mA  40μ A
B
hfe 50
VR2 = VRE - VBE = 1V + 0.6V = 1.6V. & VR1 = VCC - VR2 = 10 - 1.6V = 8.4V.
R1=VR1/IR1 = 8.4/10XIB = 8.4/10X0.04mA = 8.4/4mA = 22kΩ
R2=VR2/IR2 = 1.6/9XIB = 1.6/9X0.04mA = 1.6/0.36mA = 4.7kΩ
Design of Tank Circuit:

Let L1 = 1mH, L2 = 2.2mH
L1+L2 = 3.2mH
Let fo= 100 kHz.
fo = 1 / 2 Leff C where Leff = L1 + L2
Then C = 1/4π2Leff F2
C =791.5pF, Choose 800pF, (The value of L & C may be changed as per the
design frequency.)

Procedure:
1. Connect the circuit as shown in the diagram.
2. Measure the D.C. bias condition & vary the POT to get the output.
3. Observe the output on CRO & measure the Frequency & Amplitude and
draw waveforms on graph sheet.
4. Compare the designed values of frequency with practical values of
frequency.
Observations:
VBE = Volts. VCE = Volts.
Result Analysis:
Designed frequency f= Hz.
Simulated frequency fo = Hz. Output Voltage Vopp

b. Colpitt’s oscillator
Aim: Design a BJT – Colpitt’s Oscillator for frequency fo = 100 kHz.
Circuit Diagram:
Note: In Multisim 14 Simulator use Transistor 15C02MH-TL-E to simulate the circuit.

Since SL 100 is not available.
Construction: Colpitt’s oscillator consists of a BJT – CE amplifier with tank circuit.
The resistances R1, R2, RC& RE bias the BJT. The frequency determining network is a
parallel resonant circuit consisting of capacitors C1, C2& Inductor L. The junction of
C1& C2 is grounded. The voltage developed across C 1 provides the regenerative
feedback required for the sustained oscillations.
Circuit Working: The voltage VCC is responsible for the charging of the capacitors.
When the capacitors are fully charged to their rated voltages, they discharge through
the inductor L of the tank circuit, which produces damped harmonic oscillations.
The oscillations across C1 are applied to the Base-Emitter junction & appears in the
amplified form in the collector circuit and supply losses to the tank circuit, which is
then coupled to tank circuit through C 2 to neutralize the losses in the tank circuit.
The starting end of C1& finishing end of C2 are 1800 out of phase. The further phase
shift of 1800 is produced by BJT-CE amplifier. In this way the energy is supplied to
the tank circuit in phase with the oscillations & ‫׀׀‬Aβ‫ ׀׀‬is greater than one, the
oscillations are sustained in the circuit.
The Colpitt’s oscillator is named after its inventor Edwin H. Colpitt’s. One of the key
features of this type of oscillator is simplicity & robustness.
The Colpitt’s oscillator is an LC oscillator generally LC oscillators are designed to
operate in the Radio frequency range above 1 MHz. however they can also be
designed to produce oscillations in Low audio frequency range. The frequency of
oscillations is given by:
f= 1/2LCeff

Where Ceff = C1 x C2 / (C1+ C2)

Since Colpitt’s oscillator is a high frequency oscillator, the capacitors will be
selected in Pico-Farads range. Real time circuits will oscillate at a slightly lower
frequency due to Junction capacitances of the BJT & for other stray capacitances.
Sinusoidal oscillators are used for various applications in Electronics &
Telecommunications like Sine wave used as a carrier signal in modulation circuits,
testing frequency response of various Amplifiers, Filters & in Closed loop control
systems etc.
Observations:
VBE = Volts. VCE = Volts.
Note: Design of Amplifier is as same as Hartley oscillator
Design of Tank Circuit:
Let fo = 100 kHz.
Choose C1 & C2 =1000pF
fo= 1/2LCeff
Where Ceff = C1 x C2 / (C1+ C2)
L = 1/4π2Ceff x fo2
L = 5mH
Procedure is as same as Hartley oscillator
Result:
Designed frequency f= Hz.
Simulated frequency fo = Hz. Output Voltage Vopp
Do it yourself
 Identify the values of Resistors by Color Coding.
 Identify the terminals of Transistors & Test it by DMM.
 Learn Circuit operation.
 Know the frequency range & applications of the circuit
Activity
Design the Oscillator Tank circuit for different values of frequencies & measure the
frequency of oscillations and compare with design.

Experiment # 5: OP-AMP Inverting & Non- Inverting amplifiers
Aim: To design an OPAMP Inverting & Non Inverting amplifiers & test it
Components/Instruments required: IC 741(OPAMP), Resistors, Power supply,

Function generator, CRO, Connecting wires, CRO probes etc.
Circuit diagram:
a. Inverting Amplifier
Design:
We know that Av = -Rf/Ri
Let Rf = 10kΩ and Ri = 1kΩ
Av = -Rf/Ri
Av = -10k/1k
Av = -10
Therefore Output is amplified by 10 times and also inverted i.e. 180 0 out of phase
with the Input.
Expected Waveforms:

b. Non Inverting Amplifier
Design:
We know that Av = 1+ (Rf/Ri)
Let Rf = 10kΩ and Ri = 1kΩ
Av = 1+ (Rf/Ri)
Av = 1+ (10k/1k)
Av = 11
Therefore Output is amplified by 11 times and also in phase with the input.
Expected Waveforms:
Result Analysis:

Procedure:
1. Rig-up the circuit as shown above.
2. Switch on Power Supply. Set input voltage to 1 Volt Peak-Peak through
Function Generator.
3. Observe the output on CRO. Note down the Input & Output peak to peak
voltages and compare.
4. Sketch the Input & Output Waveforms on a graph sheet.
Test an OPAMP in Laboratory:

To test an OPAMP practically in Laboratory Rig-up a Voltage-follower circuit and
apply a voltage (say 2 Vpp) and measure the voltage at the output. Voltage must be
same and in Phase.
Challenge:
 Verify the CMRR of the Given OPAMP
 Realize an OPAMP Integrator/Differentiator circuit
 Realize an OPAMP Summer/Averager circuit

Introduction to Digital Electronics

In 1854 George Boole introduced a systematic treatment of logic and developed an
algebraic system now known as Boolean algebra. In 1938, C.E. Shannon introduced
a two valued Boolean algebra called switching algebra, which demonstrated that,
the properties of bi-stable electrical switching circuits could be represented through
this algebra. With passage of time Boolean algebra has emerged as a powerful tool
and forms the foundation of many theories of computer science and engineering.
Boolean algebra like any other mathematical system may be defined with a set of
elements, a set of operators and number of axioms or postulates. A set of element
is a collection of objects having a common property.
A logic gate is an elementary building block of a digital circuit. Most logic gates have
two inputs and one output. At any given moment, every terminal is in one of the
two binary conditions low (0) or high (1), represented by different voltage levels.
The logic state of a terminal can, and generally does, change often, as the circuit
processes data. In most logic gates, the low state is approximately zero volts (0 V),
while the high state is approximately five volts positive (+5 V).
There are three basic logic gates: AND, OR, & NOT, and two Universal logic gates
NAND and NOR other logic gates are emerged from basic gates such as X-OR and X-
NOR. Comparing Boolean algebra with arithmetic and ordinary algebra we note the
following differences:
 Boolean algebra does not have additive or multiplicative inverses; hence

there are no subtraction or division operations.
 Boolean algebra defines an operator called complement which is not available
in normal algebra.
 Normal algebra deals with real number, which constitute an infinite set of
elements whereas Boolean algebra deals with a set of only two elements 0
and 1 (defined as two valued Boolean algebra).
 The distributive law of '+' over '.' i.e., x + (y. z) = (x + y). (x + z) is valid for
Boolean algebra but not for normal algebra.
Using combinations of logic gates, complex operations can be performed. In theory,

there is no limit to the number of gates that can be arrayed together in a single
device. But in practice, there is a limit to the number of gates that can be packed
into a given physical space. Arrays of logic gates are found in digital integrated
circuits (lC’s).
As IC technology advances, the required physical volume for each individual logic
gate decreases and digital devices of the same or smaller size become capable of
performing ever- more complicated operations at ever-increasing speeds.

Why are NAND and NOR Gates called Universal Gates?
They are called universal gates because all of the other gates may be constructed
using only those two gates. That is important because it's a lot cheaper in practice
to make lots of similar things than a bunch of different things (different gates).
All other gates/functions can be implemented by NOR or NAND gates. So they are
called universal gates. In fact, in chips, entire logic maybe built using only NAND or
NOR gates.
Eg: Inverter - NAND with inputs shorted,

AND - NAND followed by an inverter (using NAND) OR - giving inverted inputs
to NAND gate.
Implementing with NAND is easier when considering power and area of the chip.
They are called universal gates as they can be used to design all other logic circuit.
Elements like X-OR, NOR etc. Also these gates can be realized through easy combina-
tion of diodes thus making them easy to use base elements in any chip designing
project.
NAND, NOR gates are called universal gates because they can be used to create all
the remaining logical gates. Like sending the same input to the inputs of the NAND
or NOR will make it a NOT gate. Because from them you can create any other one!
You can make any other gate using NAND and NOR. Any other gate i.e. AND, OR, XOR
etc can be created using these basic gates i.e. it needs only NAND and NOR gates to
create logical circuits.
AND Gate
The AND gate is a basic digital logic gate that implements logical conjunction - it
behaves according to the truth table to the right. A HIGH output (1) results only if
all the inputs to the AND gate are HIGH (1). If none or not all inputs to the AND gate
are HIGH, a LOW output results. The function can be extended to any number of
inputs.
Truth Table
Input Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

OR Gate
The OR gate is a digital logic gate that implements logical disjunction – it behaves
according to the truth table to the right. A HIGH output (1) results if one or both the
inputs to the gate are HIGH (1). If neither input is high, a LOW output (0) results. In
another sense, the function of OR effectively finds the maximum between two
binary digits, just as the complementary AND function finds the minimum.
Truth Table
Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
NOT Gate
In digital logic, an inverter or NOT gate is a logic gate which implements logical
negation. The truth table is shown on the right.
Truth Table
Input Output
A Y
0 1
1 0

NAND Gate
In digital electronics, a NAND gate (NOT-AND) is a logic gate which produces an

output which is false only if all its inputs are true; thus its output is complement to
that of an AND gate. A LOW (0) output results only if all the inputs to the gate are
HIGH (1); if any input is LOW (0), a HIGH (1) output results. A NAND gate is made
using transistors and junction diodes. By De Morgan's theorem, a two-input NAND
gate's logic may be expressed as AB=A+B, making a NAND gate equivalent
to inverters followed by an OR gate.
The NAND gate is significant because any Boolean function can be implemented by
using a combination of NAND gates. This property is called functional completeness.
It shares this property with the NOR gate. Digital systems employing certain logic
circuits take advantage of NAND's functional completeness.
The function NAND (a1, a2, ..., an) is logically equivalent to NOT(a1 AND a2 AND ...
AND an).
NAND gates with two or more inputs are available as integrated circuits in transistor-
transistor logic, CMOS, and other logic families.
Truth Table
Input Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

NOR Gate
The NOR gate is a digital logic gate that implements logical NOR - it behaves
according to the truth table to the right. A HIGH output (1) results if both the inputs
to the gate are LOW (0); if one or both input is HIGH (1), a LOW output (0) results.
NOR is the result of the negation of the OR operator. It can also be seen as an AND
gate with all the inputs inverted. NOR is a functionally complete operation—NOR
gates can be combined to generate any other logical function. It shares this property
with the NAND gate. By contrast, the OR operator is monotonic as it can only change
LOW to HIGH but not vice versa.
In most, but not all, circuit implementations, the negation comes for free—
including CMOS and TTL. In such logic families, OR is the more complicated
operation; it may use a NOR followed by a NOT. A significant exception is some forms
of the domino logic family.
Truth Table
Input Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

EX-OR Gate
XOR gate (sometimes EOR, or EXOR and pronounced as Exclusive OR) is a
digital logic gate that gives a true (1 or HIGH) output when the number of true inputs
is odd. An XOR gate implements an exclusive or; that is, a true output results if one,
and only one, of the inputs to the gate is true. If both inputs are false (0/LOW) or
both are true, a false output results. XOR represents the inequality function, i.e.,
the output is true if the inputs are not alike otherwise the output is false. A way to
remember XOR is "one or the other but not both".
XOR can also be viewed as addition modulo 2. As a result, XOR gates are used to
implement binary addition in computers. A half adder consists of an XOR gate and
an AND gate. Other uses include subtractors, comparators, and controlled inverters.
Truth Table
Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

Front Panel of Digital IC Trainer Kit

Identification of Controls on Digital IC Trainer Kit

Experiment # 6: Realization of Logic gates

Aim: To study the operation of Logic gates
1. AND Gate
2. OR Gate
3. NOT Gate
4. EX-OR Gate
5. NAND Gate
6. NOR Gate
Components &equipment’s required: 74LS:08, 32, 04, 86, 00 & 02, IC Trainer Kit,
4mm. Patch cards etc.
1. AND Gate: IC 7408:
Truth Table
Input Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
2. OR Gate: IC 7432:
Truth Table
Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

3. NOT Gate: IC 7404:
Truth Table
Input Output
A Y
0 1
1 0
4. EX-OR Gate: IC 7486:
Truth Table
Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
5. NAND Gate: IC 7400:

Truth Table
Input Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

6. NOR Gate: IC 7402:
Truth Table
Input Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
7. Truth Table verification of Logic gates using NAND & NOR gates (Universal gates)
Functio
Using NAND gates Using NOR gates
n
NOT
gate
AND
gate

OR gate
EX-OR
gate
Procedure:
1. The connections are made as shown in Circuit(by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is
connected to the Output Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in
Truth Table & the Output is observed on LED’s.
Faults & Debugging:

1. Check Continuity of given Patch Chords before circuit Connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All
output LED Indicators will be in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin
details.
4. Check operating voltage connected to IC (+Vcc& Gnd.)
5. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

Experiment #7: Realization of Parallel Adder and Subtractor

Aim: Realization of Parallel Adder and Subtractor using IC 7483.
Parallel adder:
The 7483 IC is a 4-bit parallel adder chip. Note: the chip can also be listed as a
74LS83. The LS signifies that the chip is a newer, lower-power, faster version. A
binary parallel adder is a digital function that produces the arithmetic sum of two
binary numbers in parallel. It consists of full adders connected in cascades with the
output carry from one full adder connected to input carry of the next full adder.
Parallel adder Theory:

A parallel adder is an arithmetic combinational logic circuit that is used to add more
than one bit of data simultaneously. A full adder adds two bits and a carry to give
an output. However, to add more than one bit of data in length a parallel adder is
used. A parallel adder adds corresponding bits simultaneously using full adders and
keeps generating a carry and pushing it towards the next most significant bit to be
added. An n-bit parallel adder uses n full adders connected in cascade with each full
adder adding the two corresponding bits of both the numbers.
For example, for a binary number A3A2A1A0 and B3B2B1B0, a full adder connected
in cascade would add D0 and B0 and send the result to be displayed (LSB). If a carry
is generated, it will be passed on to the input of the next full adder.
How to design a 4-bit parallel adder?

To add two Hex codes we need four full adders connected in cascade. This is because
a hex code can be represented by four binary bits. The four full adders will connect
to each other via their CARRY outputs. And depending on the position of the bits the
full adders add, the SUM outputs of the full adders will be connected to the display.
The least significant bit will be connected to the LSB of the display. The most
significant bit will be connected to the pin one bit before the MSB of the display.
The carry output of the final full adder will be connected to the MSB pin of the
display.
We can use two hex 4×4 keypads to generate the input bits or we can just add the
bits manually. If you want a circuit diagram without the hex keypads as inputs let us
know in the comments. Each row of the keypad is connected to a full adder
depending on its significance. The first full adder receives inputs from the first row
of the hex keypad, the second receives inputs from the second row of the hex keypad
and the carry from the first and so on. The resultant combinational logic circuit is
shown below.
Components & equipment’s required: 7483, 7486 & 7404, Digital IC Trainer Kit,
4mm. Patch cards etc.

PIN Diagram:
Circuit Diagram:
Note: A1, A2, A3, A4 & B1, B2, B3, B4 & Cin are the Inputs.
S1, S2, S3, S4 and Cout are the Outputs.

Here A1, B1 & S1 are the LSB Bits.

S is considered as selection Input to select for Addition or Subtraction.
For Addition S=0 & For Subtraction S=1.
4 Bit Adder Operation
If control input S = 0, Addition can be performed.

Example 1: When Cin = 0.
If A4 ,A3, A2, A1 = 1 1 0 0
B4, B3, B2, B1 = 0 0 1 1
Then Sum = S4, S3, S2, S1 = 1 1 1 1
In this Case Cout = 0
Example 2: When Cin = 0.

If A4 ,A3, A2, A1 = 1 1 0 1
B4, B3, B2, B1 = 1 0 1 1
Then Sum = S4, S3, S2, S1 = 1 0 0 0
Example 3: When Cin = 1

1
If A4 ,A3, A2, A1 = 1 1 0 1
B4, B3, B2, B1 = 1 0 1 1
Then Sum = S4, S3, S2, S1 = 1 0 0 1
Problems:
A := 1111 1111 1100 1100 0111
B := 0000 0000 0011 0011 1110
Cin : = 0 1 0 1 1
Sum = (Do it yourself)

4 Bit Subtractor +Ve Result
Cout&Cin is shorted & S= 1 (Logic 1)
By normal Subtraction method

Example 1: Subtract
A4 ,A3, A2, A1 = 1 0 0 1
B4, B3, B2, B1 = 0 0 1 1 Give this from Trainer Kit
Then Difference = S4, S3, S2, S1 = 0 1 1 0
By 1’s Compliment method
I Step: B4, B3, B2, B1 = 0 0 1 1 given number

= 1 1 0 0 1’s complement of Subtrahend.
II Step:
Adding 1’s complement of Subtrahend to the minuend
A4 ,A3, A2, A1 = 1 0 0 1 Given Larger Number
B4, B3, B2, B1 = + 1 1 0 0
=10101
End around carry.

III Step:
Add end around carry to the result.
0 1 0 1 Result except carry
+ 1 Adding carry
0 1 1 0 True Result – Trainer Kit
In this case, Cin& S are held at logic 1.
Example 1: Subtract
A4 ,A3, A2, A1 = 1 0 0 1
B4, B3, B2, B1 = 0 0 1 1 Give this from Trainer Kit
Then Difference = S4, S3, S2, S1 = 0 1 1 0
I Step: B4, B3, B2, B1 =0011 given number

=1100 1’s complement of Subtrahend.
+ 1 Adding 1 to get 2’s Complement.
= 1101 2’s omplement of subtrahend.

II Step:
B4, B3, B2, B1 = + 1 1 0 1
10110
Carry generated
III Step:
Neglect the carry to get true Answer
Therefore Answer = 0 1 1 0 - Trainer Kit
4 Bit Subtractor – Ve Result
Cout&Cin is shorted & S= 1 (Logic 1)

By normal Subtraction method
Example 1: Subtract
A4 ,A3, A2, A1 = 0 0 1 1 3
B4, B3, B2, B1 = 1 0 0 1 9 Give this from Trainer Kit
Then Difference = S4, S3, S2, S1 = -6

II Step:
Adding 1’s complement of Subtrahend to the minuend
B4, B3, B2, B1 = +0 1 1 0
= 1 0 0 1 Trainer Kit Final Output
Here No End around carry.

III Step:
Here theoretically perform 1’s Compliment operation to get True Answer.
1 0 0 1 (Trainer Kit Output)
1’s Compliment
0 1 1 0 True Answer

In this case, Cin & S are held at logic 1.
Example 1: Subtract
A4 ,A3, A2, A1 = 0 0 1 1 3
B4, B3, B2, B1 = 1 0 0 1 9 Give this from Trainer Kit
Then Difference = S4, S3, S2, S1 = -6

+ 1 Adding 1 to get 2’s Complement.
= 0 1 1 1 2’s Complement of subtrahend.
II Step:
A4, A3, A2, A1 = 0 0 1 1 Given Larger Number
B4, B3, B2, B1 = + 0 1 1 1
1 0 1 0 Trainr Kit Final Output
Carry Not generated
III Step: Here theoretically perform 2’s Compliment operation to get True Answer.
1 0 1 0 (Trainer Kit Output)
2’s Compliment
0 1 1 0 True Answer
Problems:
A := 0110 1100 0 1 00 0111 1111
B:= 0100 0111 0110 1100 1111
Diff = (Do it yourself)
Procedure:
5. Given problems should be worked out & get the outputs.

Faults & Debugging:

details.

Experiment #8: 4:1 Multiplexer / 1:4 De-multiplexer

Using Basic/universal gates
Aim: Realization of 4:1 Multiplexer and 1:4 De-multiplexer Using Basic/universal

gates.
Multiplexer:
 Multiplexer has many data input lines and one output line.
 Multiplexer (MUX) places the data of one of its input lines on the output line.
 MUX has a set of “n” address lines to select one of 2n input line
 SOP realization is possible using MUX.
A multiplexer is a combinatorial circuit that is given a certain number (usually a

power of two) data inputs, let us say 2n, and n address inputs used as a binary
number to select one of the data inputs. The multiplexer has a single output, which
has the same value as the selected data input.
In other words, the multiplexer works like the input selector. Only one input is
selected at a time, and the selected input is transmitted to the single output.
Demultiplexer:
A demultiplexer (DEMUX) is a device which essentially performs the opposite opera-
tion to the MUX. That is, it functions as an electronic switch (or data distributor) to
route an incoming data signal to one of several outputs.
The demultiplexer is the inverse of the multiplexer, in that it takes a single data
input and n address inputs. It has 2n outputs. Output is inverted in IC 74139 1:4
Demultiplixer.
Components &equipments required: IC 74153, 74139, 7404, 7408, 7432, 7400 &
7420. Digital IC Trainer Kit, 4mm. Patch cards etc.
Connection Diagram MUX:

Truth Table:
Address
Enable
Select Data Inputs Output
Inputs Comments
Inputs
S1 S0 I0 I1 I2 I3 Y
0 0
0 0 0 X X X I0 Selected
1 1
0 0
1 1
0 0
1 1
0 0
1 1
1 X X X X X X X MUX Disabled
Circuit Diagram:

Connection Diagram DEMUX:
Truth Table:
Address
Data Input Select Data Outputs
Inputs Comments
S1 S0 Y0 Y1 Y2 Y3
(Da) (Db)
0 0 0 0 0 1 1 1 Y0 Selected
0 1 1 0 1 1 Y1 Selected
1 0 1 1 0 1 Y2 Selected
1 1 1 1 1 0 Y3 Selected
Circuit Diagram:


Procedure:
5. X in the truth table indicates Don’t care condition since depending on the
selection line the data line will be selected.
Faults & Debugging:

details.

Experiment #9: Arithmetic Circuit Realization

(Half/Full Adder/Subtractor) using Mux.
Aim: Realization of Arithmetic Circuit (Half/Full, Adder/Subtractor) using Dual Mux

IC74153.
Components &equipments required: IC 74153, 7404. Digital IC Trainer Kit, 4mm.
Patch cards etc.
Realization of Half Adder Using IC 74153
Truth Table: Implementation Table:

TRUTH TABLE
Input Output
A B S C
0 0 0 0 0
1 0 1 1 0
2 1 0 1 0
3 1 1 0 1
Circuit Diagram:

OR
Truth Table:
Input Output
A B S C
S1 S0 Ia Ib
0 0 0 0 0
1 0 1 1 0
2 1 0 1 0
3 1 1 0 1
Circuit Diagram:
Realization of Full Adder Using IC 74153

Input Output
A B Cin S Cout
0 0 0 0 0 0
1 0 0 1 1 0
2 0 1 0 1 0
3 0 1 1 0 1
4 1 0 0 1 0
5 1 0 1 0 1
6 1 1 0 0 1
7 1 1 1 1 1
Circuit Diagram:

OR

Input Output
A B S Cout
Cin
S1 S0 Ia Ib
0 0 0 0 0 0
cin Logic
1 0
1
0 0 1 0
2 0 1 0 1 0
cin
3 0 1 1
0 1
4 1 0 0 1 0
cin
5 1 0 1
0 1
6 1 1 0 0 1
cin Logic
7 1 1 1 1 1
1
Circuit Diagram:
Realization of Half Subtractor Using IC 74153


Input Output
A B D B
0 0 0 0 0
1 0 1 1 1
2 1 0 1 0
3 1 1 0 0
Circuit Diagram:
OR
Truth Table:
Input Output
A B D B
S1 S0 Ia Ib
0 0 0 0 0
1 0 1 1 1
2 1 0 1 0
3 1 1 0 0

Circuit Diagram:
Realization of Full Subtractor Using IC 74153
Input Output
A B Bin D Bout
0 0 0 0 0 0
1 0 0 1 1 1
2 0 1 0 1 1
3 0 1 1 0 1
4 1 0 0 1 0
5 1 0 1 0 0
6 1 1 0 0 0
7 1 1 1 1 1
Circuit Diagram:

Truth Table:
OR
Implementation Table:
Input Output
A B Bin D Bout
0 0 0 0 0 0
Bin Bin
1 0 0 1
1 1
2 0 1 0 1 1
Logic
3 0 1 1 0 1
1
4 1 0 0 1 0
Logic
5 1 0 1 0 0
0
6 1 1 0 0 0
Bin Bin
7 1 1 1
1 1
Circuit Diagram:

Procedure:
Faults & Debugging:

details.

Experiment #10: Master- Slave JK, T and D Flip-Flop
Aim: Construction and verification of JK Master-Slave, T & D Flip-Flops using logic

gates.
JK Flip-Flop: One way of overcoming the problem with oscillation that occurs with
a JK Flip-Flop when J= K = 1 is to use a so-called master-slave flip- flop which is
illustrated in the circuit diagram.
The master-slave flip-flop is essentially two back-to-back JKFFs, note however, that
feedback from this device is fed back both to the master FF and the slave FF.
Any input to the master-slave flip-flop at J and K is first seen by the master FF part
of the circuit while CLK is High (= 1). This behaviour effectively "locks" the input into
the master FF. An important feature here is that the complement of the CLK pulse
is fed to the slave FF. Therefore the outputs from the master FF are only "seen" by
the slave FF when CLK is Low (=0). Therefore on the High-to-Low CLK transition the
outputs of the master are fed through the slave FF. This means that at most one
change of state can occur when J=K = 1 and so oscillation between the states Q=O
and Q= 1 during the same CLK pulse does not occur.
Master-Slave JK Flip-flop
The master-slave flip-flop eliminates all the timing problems by using two SR flip-
flops connected together in a series configuration. One flip-flop acts as the “Master”
circuit, which triggers on the leading edge of the clock pulse while the other acts as
the “Slave” circuit, which triggers on the falling edge of the clock pulse. This results
in the two sections, the master section and the slave section being enabled during
opposite half-cycles of the clock signal.
The TTL 74HC76 is a Dual JK flip-flop IC, which contains two individual JK type
bistable’s within a single chip enabling single or master-slave toggle flip-flops to be
made. Other JK flip flop IC’s include the 74LS107 Dual JK flip-flop with clear, the
74LS109 Dual positive-edge triggered JK flip flop and the 74LS112 Dual negative-
edge triggered flip-flop with both preset and clear inputs.
The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in
a series configuration with the slave having an inverted clock pulse. The outputs
from Q and Q from the “Slave” flip-flop are fed back to the inputs of the “Master”
with the outputs of the “Master” flip flop being connected to the two inputs of the
“Slave” flip flop. This feedback configuration from the slave’s output to the master’s
input gives the characteristic toggle of the JK flip flop.
The input signals J and K are connected to the gated “master” SR flip flop which
“locks” the input condition while the clock (Clk) input is “HIGH” at logic level “1”.
As the clock input of the “slave” flip flop is the inverse (complement) of the
“master” clock input, the “slave” SR flip flop does not toggle. The outputs from the
“master” flip flop are only “seen” by the gated “slave” flip flop when the clock input
goes “LOW” to logic level “0”.

When the clock is “LOW”, the outputs from the “master” flip flop are latched and
any additional changes to its inputs are ignored. The gated “slave” flip flop now
responds to the state of its inputs passed over by the “master” section.
Then on the “Low-to-High” transition of the clock pulse the inputs of the “master”
flip flop are fed through to the gated inputs of the “slave” flip flop and on the “High-
to-Low” transition the same inputs are reflected on the output of the “slave” making
this type of flip flop edge or pulse-triggered.
Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the
data to the output on the falling-edge of the clock signal. In other words,
the Master-Slave JK Flip flop is a “Synchronous” device as it only passes data with
the timing of the clock signal.
Components &equipments required: IC 7400, & 7410. Digital IC Trainer Kit, 4mm.
Patch cards etc.
Circuit Diagram:

Truth Table:
Inputs Outputs
Comments
J K CLK Qn n
Indeterminate
0 0 X X X 1 1
State
0 1 X X X 1 0 FF Preset(Set)
1 0 X X X 0 1 FF Cleared(Reset)
1 1 0 0 X Q n-1 n-1 Previous
1 1 0 1 0 1 Reset
1 1 1 0 1 0 Set
1 1 1 1 n-1 Q n-1 Toggle
Note:
Keep = 1 and =1 for verifying the Truth Table of JK Master-
Slave FF & T FF.
Q n is Output level before giving Clock pulse.
Circuit Diagram:

Truth Table:
Inputs Outputs
Comments
T CLK Qn n
Indeterminate
0 0 X X 1 1
State
0 1 X X 1 0 FF Preset(Set)
1 0 X X 0 1 FF Cleared(Reset)
1 1 0 X Q n-1 n-1 Previous
1 1 1 n-1 Q n-1 Toggle
Circuit Diagram:

Truth Table:
Inputs Outputs
Comments
D CLK Qn n
Indeterminate
0 0 X X 1 1
State
0 1 X X 1 0 FF Preset(Set)
1 0 X X 0 1 FF Cleared(Reset)
1 1 0 0 1 Data transferred
1 1 1 1 0 Data transferred
Circuit Diagram:

Procedure:
2. The input terminals (JK, T & D) are connected to the toggle switches & the
output is connected to the Output Connector (LED’s).
4. Connect clock pin to the bounce less pulsar HIGH or LOW
5. The Logic levels are applied at the Inputs as indicated in Truth Table & the
Output is observed on LED’s.
6. X in the truth table indicates Don’t Care condition.
Faults & Debugging:

details.
5. To check outputs apply Clock correctly as specified in Procedure.

Experiment #11: 3 Bit ripple up/down Counters

Aim: Construction and realization of 3 bit ripple up/down counter using IC 7476 and
other logic gates.
Counters: The synchronous design of any sequential circuit application for example
counter is a design in which all the flip-flops are connected to a common clock input
that is, all the flip-flops are clocked simultaneously. Therefore to get the next state
of application actual inputs of the flip-flop should be designed according to the
requirement.
Hence excitation tables are used to design the actual inputs of the flip-flops to get
the next stage. The excitation table gives the combination of input for the required
output condition before and after the application of clock.
Ripple Counter
A ripple counter is an asynchronous counter where only the first flip-flop is clocked
by an external clock. All subsequent flip-flops are clocked by the output of the
preceding flip-flop. Asynchronous counters are also called ripple-counters because
of the way the clock pulse ripples it way through the flip-flops.
The MOD of the ripple counter or asynchronous counter is 2n if n flip-flops are used.
For a 4-bit counter, the range of the count is 0000 to 1111 (24-1). A counter may
count up or count down or count up and down depending on the input control. The
count sequence usually repeats itself. When counting up, the count sequence goes
from 0000, 0001, 0010, ... 1110 , 1111 , 0000, 0001, ... etc. When counting down
the count sequence goes in the opposite manner: 1111, 1110, ... 0010, 0001, 0000,
1111, 1110, ... etc.
The complement of the count sequence counts in reverse direction. If the un

complemented output counts up, the complemented output counts down. If the
uncomplemented output counts down, the complemented output counts up.
There are many ways to implement the ripple counter depending on the
characteristics of the flip flops used and the requirements of the count sequence.
 Clock Trigger: Positive edged or Negative edged
 JK or D flip-flops
 Count Direction: Up, Down, or Up/Down
Asynchronous counters are slower than synchronous counters because of the delay
in the transmission of the pulses from flip-flop to flip-flop. With a synchronous
circuit, all the bits in the count change synchronously with the assertion of the clock.
Examples of synchronous counters are the Ring and Johnson counter.
It can be implemented using D-type flip-flops or JK-type flip-flops.
The circuit below uses 2 D flip-flops to implement a divide-by-4 ripple counter (2n =
22 = 4). It counts down.

Components & equipment’s required: IC 7476, 7400, 7404, 7408 & 7410. Digital IC
Trainer Kit, 4mm. Patch cards etc.
Circuit Diagram:
Note:
 J & K inputs of Flip-Flops are connected to logic 1 or Keep it open to operate
under toggle mode.
 When Preset = 1, Clear = 0; Counter is cleared Q0 = Q1 = Q2 = 0
 When Preset = 0, Clear = 1; Counter is preset Q0 = Q1 = Q2 = 1
 Keep Preset = 1, Clear = 1 for count mode.
Truth Table:
No. of Flip-Flop
Clock Outputs
Pulses Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

Circuit Diagram:
Truth Table:
No. of Flip-Flop
Clock Outputs
Pulses Q2 Q1 Q0
0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8 1 1 1

Circuit Diagram:
Truth Table:
No. of Flip-Flop
Clock Outputs
Pulses Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 0 0 0
Circuit Diagram:
Note:
 When Mode control is at logic 1 counter works as an Up-counter.
 When Mode control is at logic 0 counter works as a Down-counter.

Specifications of Equipment’s












Ratings of Transistors from Specification sheet

Since the specification sheet is the communication link between the manufacturer
and user, it is particularly important that the information provided be recognized
and correctly understood.
The following is an example of general purpose transistors with the casing. Most
specification sheets are broken down into maximum ratings, thermal characteristics
and electrical characteristics. The electrical characteristics are further broken down
into “on” and “off” and small signal characteristics. The “on” and “off”
characteristics refers to dc limits where as the small signal characteristics include
the parameters of importance to ac.
Structur Case IC VCE hFE Ptot Category Possible
Code substitutes
e style max max. min max. (typical use)
BC182
BC107 NPN TO18 100mA 45V 110 300mW Audio, low power
BC547
BC547B NPN TO92C 100mA 45V 200 500mW Audio, low power BC107B
General purpose,
BC548B NPN TO92C 100mA 30V 220 500mW BC108B
low power
General purpose,
2N3055 NPN TO3 15A 60V 20 117W ---
high power
General purpose,
BC478 PNP TO18 150mA 40V 125 360mW BC178
low power
BC177 PNP TO18 100mA 45V 125 300mW Audio, low power BC477
General purpose,
BC178 PNP TO18 200mA 25V 120 600mW low power
BC478
General purpose,
TIP32A PNP TO220 3A 60V 25 40W TIP32C
high power

Note: the data in this table is from several sources which may be modified or
changed. Most of the discrepancies are minor, but please refer data sheets from
supplier if you require precise data. The above table contents are explained below:
Structure: This shows the type of transistor, NPN or PNP. The polarities of the two
types are different, so if you are looking for a substitute it must be the same type.
Case style: There is a diagram showing the leads for some of the most common case
styles in the Connecting section above. This information is also available in suppliers'
catalogues.
IC max. : Maximum collector current.
VCE max. : Maximum voltage across the collector-emitter junction. You can ignore
this rating in low voltage circuits.
hFE: This is the current gain (strictly the DC current gain). The guaranteed minimum
value is given because the actual value varies from transistor to transistor - even for
those of the same type! Note that current gain is just a number so it has no units.
The gain is often quoted at a particular collector current IC which is usually
in the middle of the transistor's range, for example '100@20mA' means the gain is at
least 100 at 20mA. Sometimes minimum and maximum values are given. Since the
gain is roughly constant for various currents but it varies from transistor to transistor
this detail is only really of interest to experts.
Ptot max: Maximum total power which can be developed in the transistor, note that
a heat sink will be required to achieve the maximum rating. This rating is important
for transistors operating as amplifiers. The power is roughly IC × VCE. For transistors
operating as switches the maximum collector current (IC max.) is more important.

Category: This shows the typical use for the transistor, it is a good starting point
when looking for a substitute. Catalogues may have separate tables for different
categories.
Possible substitutes: These are transistors with similar electrical properties which
will be suitable substitutes in most circuits. However, they may have a different
case style so you will need to take care when placing them on the circuit board.

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School of Electronics and

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

PROGRAM SPECIFIC OUTCOMES (PSOs)

PO-1: Engineering Knowledge: Apply the knowledge of mathematics, science, engineering

PO-10: Communication: Communicate effectively on complex engineering activities with the

Sl. Title Page No.

4 Draw an input & output characteristics of common emitter 10

9 Introduction to Digital Electronics 29

Analog & Digital Electronics lab (B22ES0305) SEM 3 2

Course Title Analog and Digital Circuits Course Type Integrated

Practice 1 2 2 Theory practical IA SEE

COURSE OBJECTIVE (S)

COURSE OUTCOMES (COs)

Analog & Digital Electronics lab (B20ES0303) SEM 3 3

1. Voltage follower and summers using uA741 op-amp.

Analog & Digital Electronics lab (B20ES0303) SEM 3 4

Use symbols properly.

Analog & Digital Electronics lab (B20ES0303) SEM 3 5

Precautions to be taken when preparing a circuit:

Analog & Digital Electronics lab (B20ES0303) SEM 3 6

B.B. ROY of Great Britain had a Very Good Wolf.

Decoding the value of Carbon resistors:

E12 Series: 10,12,15,18,22,27,33,39,47,56,68,82, 100, 120, 150, 180, 220, 270,

Analog & Digital Electronics lab (B20ES0303) SEM 3 7

Standard commercial Values of E12 series Carbon resistors:

Ohms Kilo Ohms Mega Ohms

Terminal identification of Transistors

Transistors with different packages:

Analog & Digital Electronics lab (B20ES0303) SEM 3 8

PIN DETAILS 0F µA 741:

Analog & Digital Electronics lab (B20ES0303) SEM 3 9

Experiment # 1: BJT CHARACTERISTICS (CE CONFIGURATION)

COMPONENTS REQUIRED: Transistor BC 107, Resistor 100 kΩ, 1kΩ, DC Ammeter,

THEORY: In common emitter configuration the emitter is common to both input

Analog & Digital Electronics lab (B20ES0303) SEM 3 10

Input Characteristics Output Characteristics

1. Connect the circuit as per the circuit diagram.

Analog & Digital Electronics lab (B20ES0303) SEM 3 11

Analog & Digital Electronics lab (B20ES0303) SEM 3 12

Analog & Digital Electronics lab (B20ES0303) SEM 3 13

Experiment # 2: Single Stage R-C Coupled BJT Amplifier

Components/Instruments Required: Transistor, Capacitors, Resistors, Power

R-C Coupled BJT Amplifier

VCC ICRC  VCE  VE  0

Analog & Digital Electronics lab (B20ES0303) SEM 3 14

Analog & Digital Electronics lab (B20ES0303) SEM 3 15

Analog & Digital Electronics lab (B20ES0303) SEM 3 16

To measure Input Impedance:

1. A DRB is connected in series with the input as shown in figure.

1. A DRB is connected across the output as shown in figure.

Analog & Digital Electronics lab (B20ES0303) SEM 3 17

Experiment # 3: Design a two stage R-C Coupled BJT CE voltage series

We Know VE=IE x RE =2V

Applying KVL to the Collector Emitter loop to find RC

VCC ICRC  VCE  VE  0

Analog & Digital Electronics lab (B20ES0303) SEM 3 18

Analog & Digital Electronics lab (B20ES0303) SEM 3 19

To Measure Input And Output Impedance:

Analog & Digital Electronics lab (B20ES0303) SEM 3 20

Experiment # 4: BJT Hartley and Colpitt’s Oscillators.