0% found this document useful (0 votes)
13 views

3_6T SRAM

Memory Design and testing lecture 3

Uploaded by

pluscommander972
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
13 views

3_6T SRAM

Memory Design and testing lecture 3

Uploaded by

pluscommander972
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 48

EC 4136:

Memory Design & Testing

Memory-I: Static Random


Access Memory (SRAM)

Dr. Pooran Singh


Dept. of Electrical & Computer Engineering (ECE)
Ecole Centrale School of Engineering,
1
Mahindra University
Array-Structured Memory Architecture
2L-2 K Bit line
Storage cel
AK

Row Decoder
A K -1 1 Word line

A L -2 1

M.2K
M.2k columns
Amplify swing to
Sense amplifiers / Drivers
= 2 words
k eachamplitude
rail-to-rail with M bits
A0
Column decoder Selects appropriate
A K -2 1 word

Input-Output
Read/write ckts
(M bits)

M bit data
2
Array-Structured Memory Architecture
b0 b1 b3

b0w0 b0w1 b0w2 b0w3 b1w0 b1w1 b1w2 b1w3 b3w0 b3w1 b3w2 b3w3
WL

Col.
Decoder
(word
Col. MUX Col. MUX Col. MUX
selector)
R/W ckts R/W ckts R/W ckts
for each bit for each bit for each bit

b0 b1 b3

bmwn = bit ‘m’ of word ‘n’ 4 bit Word


3
Hierarchical Memory Architecture
Block 0 Block i Block P -2 1

Row
address

Column
address
Block
address

Global data bus


Control Block selector Global
circuitry amplifier/driver

I/O
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
4
Read-Write Memories (RAM)
❑ STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential

❑ DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
5
6-transistor CMOS SRAM Cell
WL

VDD
M2 M4

Q
M5 Q M6

M1 M3

BL BL
pull-up or load devices (M2, M4) ❑ Data Holding
pull-down devices (M1, M3) ❑ Read
access or pass-gate devices (M5, M6)
❑ Write 7
Basic Principle of Data Storage in
SRAM: Positive Feedback: Bi-
Stability
V i1 V o1 = V i 2 V o2
Vo1 Vi2
V o2 = V i1

V i1 Vo2

A
V i2 = Vo1

B
V i1 =Vo2

A cross-coupled inverter provides a basic storage elem8ent


CMOS SRAM Analysis (Read)
VDD
PRE
PRE

WL0

cell WL0
VDD VDD

Cbit Cbit BL VDD BIT


BL BL
cell BL

WLn
8
SRAM Cell: Read Operation

WL = VDD

VDD
M2 M4
Q
M 5 ‘0’ Q ‘1’
M6
VDD VDD

Cbit M1 M3 Cbit

BL BL

9
CMOS SRAM Analysis (Read)
IREAD
WL
VDD
VDD
BL M4 Cbit
BL
Q=0
Q=1 M6
M5
dVbl
V DD M1 V DD V DD Cbit + I READ = 0
IREAD dt
Cbit Cbit

Cbit BIT = Taccess
IREAD
IREAD = read current Taccess = Access Time
M1 in linear region BIT = bit − differential
Assume, bitline voltage drops slowly
=> M5 is in saturation
10
Bitline Capacitances per Cell
WL

VDD Cov
M2 M4

Q
M5 Q
M6

M1 M3 Cmetal
Cjunction
BL BL

(
Cbit _ percell = C junction + Cov +C ) metal

11
Bit-line Capacitances
❑ Junction capacitance of access transistors
❑ Gate-to-drain overlap capacitances
❑ Metal capacitance of the bit-line

(
Cbit = Nrow C junction + Cov + Cmetal )
Cjunction = junction cap of each access device
Cov = gate − to − drain overlap cap of each access device
Cmetal = metal cap of per cell
12
CMOS SRAM Analysis (Read)
WL
RM5 Q =V READ
VDD VDD
BL VREAD M4
BL
Q =VREAD
Q=1 M6 RM1
M5

VDD M1 VDD VDD

Cbit Cbit

M5 and M1 from a resistor divider Q =VREAD

VREAD=read voltage
WL
13
CMOS SRAM Analysis (Read)
WL IREAD
VDD VDD
BL M4
BL
Q = VREAD Cbit
Q=1 M6
M5

 BIT
VDD M1 VDD VDD
IREAD
Cbit
Cbit = T access
Cbit
I READ

14
Computation of Read Voltage
WL

VDD
BL M4
BL
M5 in saturation
Q = VREAD
Q=1 M6
M1 in linear
M5

VDD M1 VDD VDD


IREAD
Cbit Cbit

15
Destructive Read
Vread Q
WL = VDD

V DD Q =VREAD
M2 M4
Q
M5 Q M6 WL
Correct Read
M1 M3

Q
BL BL

Q
Vtrip = switching
VREAD > Vtrip threshold of WL
=> destructive read inverter M4-M5 Destructive Read
16
Noise Margin for Read Operation
A simple definition (can be used for first-order design)

Read Margin = Vtrip −Vread

VDD − Vthp + M 3 M 4 Vthn 


Vtrip = 
1+ M 3 M 4  stronger pull − down = lower Vtrip

VDD − Vthp + ratio− pd − pup Vthn  stronger pull − up = higher V trip
= 
1 + ratio− pd − pup 
 1 stronger pull − down = lower Vread
VREAD = (VDD − Vthn )1− 1− 
 1+ ratio− pd −ax  stronger access = higher Vread
 

17
SRAM Analysis (Read)
0.9
0.8
M1
read voltage [V]

0.7 VDD = 2.5V ratio− pd−ax =


0.6
Vth = 0.5V M 5
0.5
0.4
0.3
0.2
0.1 Weaker access & stronger pull-down
0
0 1 2 3 4 5

pull-down to access beta ratio

❑ A stronger pull-down device reduces VREAD.


❑ A stronger access device increases VREAD.
18
Cell sizing for Trip Voltage
1.4
trip voltage
1.3

1.2 Stronger pull-down &


weaker pull-up
1.1 VDD = 2.5V
Vth = 0.5V
1
0 1 2 3 4 5

pull-down to pull-up beta ratio

❑ A stronger pull-up device increases Vtrip.


❑ A weaker pull-down device increases Vtrip.
19
Read Access Speed

For lower read access time:


Higher Iread
stronger access & stronger pull-down
Pull-up device does not contribute to read
speed
Pull-up can be made weaker (i.e. of smaller
width) which will also reduce area

20
Noise Margin for Read Operation
For better read margin:
Smaller Vread => Higher ratio-pd-ax
=> weaker access & stronger pull-down
Higher Vtrip => Lower ratio-pd-pup
=> weaker pull-down & stronger pull-up
• Read margin requirement for access device
contradicts with read speed requirement
• Read voltage requirement for pull-down device
contradicts trip point requirement
• Read voltage is more sensitive to pull-down strength
compared to trip voltage
• Generally a larger pull-down helps read margin but it
cannot be too large

21
Write Operation
WL = VDD BL = VDD
V DD
M M
2 4
Q BL=0
M5 ‘0’ Q M
‘1’ 6
WL

M1 M3

BL = VDD BL=0
Q

Q
charging current WL
dis-charging current Write Operation
22
Write Operation : Key
❑ The major writing process is dischraging
the node storing ‘1’ to ‘0’.
❑ During this discharging process (initially)
the “ON” pull-up PMOS fights with the
“ON” access device.
❑ We need to make sure the node storing
‘1’ can be reduced below the switching
threshold of the other inverter.

23
CMOS SRAM Analysis (Write)
WL
VDD
We want to reduce Q to a
M4
a very low value V Q
Q= 0 M6
M5
Q= 1
=> Assume VQ is low
enough such that M 4
M1
V DD goes to saturation and
BL = 1 BL = 0 M6 goes to linear

24
Write Operation: Cell Sizing
0.8
VDD = 2.5V
VQ (write voltage)

0.6 Vtp = Vtn = 0.5V

0.4
[V]

0.2

0
0 0.2 0.4 0.6 0.8
pull-up to access beta ratio

❑ A stronger pull-up PMOS degrades writability


❑ A weaker access device degrades writability
25
Sizing Conflicts
Read Read noise Writability
speed margin

Pull-down Strong Strong Less


important

Access Strong Weak Strong

Pull-up Don’t care Strong Weak

❑ Careful sizing of each device is necessary to meet all the


requirement for cell design
❑ A good starting point : Wp:Waccess:Wpull-down = 1:1.5:2
26
SRAM Cell Design Parameters
❑ Read Margin
▪ Read and trip voltage
▪ Static Noise Margin
❑ Speed
▪ Read current
▪ Access time
▪ Bit-differential
❑ Write
▪ Write Margin
▪ Write time

27
Cell Design Parameters: Read margin

WL = VDD
VDD

VREAD =
M
Measure the dc Vtrip = 4
voltage at this Measure Q
point
M dc voltage
5
at this
point M3
M Q = V DD
1

BL = VDD

Read voltage estimation Trip voltage estimation


28
A More Accurate Measure of Read
Noise Margin: Static Noise Margin
WL=VDD M1 / M2 WL=VDD

VDD Q Q VDD
M5 M6
Static noise
margin
+
VQ - M3 / M 4 VQ

V
Q 30
Cell Design Parameters: Read Current
BIT
WL = VDD Access Time = Taccess =Cbit
I READ
IREADTaccess
bit − differential =  BIT =
Cbit
M5

IREAD = Measure M1 Q = VDD


the dc current

BL = VDD

Access time or bit differential estimation


30
Cell Design Parameters: Access Time
VDD
PRE

WL0 PRE, WL0

cell
VDD VDD

Cbit Cbit BL VDD BIT

BL cell BL BL

WLn
31
Cell Design Parameters: Bit-differential
VDD
PRE
PRE

WL0

cell WL0
VDD VDD

Cbit Cbit BL VDD BIT

BL cell BL BL

WLn
32
Cell Design Parameters: Write Margin
WL = VDD BL = VDD
VDD
M2 M4 BL=VW
Q
M5 ‘0’Q ‘1’
M6
BL=0
M1 M3 WL

BL = VDD BL=VW

Write Margin = Reduce VW from


VDD to 0 and find out the maximum
value of VW till which you can WL
write to the cell
A larger value of write margin ensures a more reliable
write operation 34
Peripheral Circuits
❑ Decoders
❑ Column multiplexers
❑ Read circuits
▪ Pre-charge circuits
▪ Sense amplifiers
▪ Timing requirements
❑ Write circuits

34
Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion

(N)AND Decoder

NOR Decoder

35
Hierarchical Decoders
Multi-stage implementation improves performance
• ••

WL 1

WL 0

A 0A 1 A 0A 1 A 0A1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3

• ••
NAND decoder using
2-input pre-decoders
A1 A0 A0 A1 A3 A2 A2 A3

36
Dynamic Decoders
Precharge devices GND GND VDD

WL3
VDD
WL3

WL 2
WL2 VDD

WL1
WL 1
V DD
WL0
WL 0

VDD  A0 A0 A1 A1
A0 A0 A1 A1 

2-input NOR decoder 2-input NAND decoder

37
4-input TG based column decoder/MUX
BL 0 BL 1 BL 2 BL 3

S0
A0 S0
S1
S1

S2
S2
A1 S3
S3

Advantages: speed (tpd does not add to overall memory access time)
Only one extra transistor in signal path

38
Column MUX
bit0 bit3
b0W0 b0W1 b0W 2 b0W3 b3W 0 b3W1 b3W2 b3W3
R0
A0
row dec.

A3 R15

s0
column dec.

A4 s1
A5 s2
s3

d0 d3 40
Column MUX BL = Red BL = Green
R0
A0 row dec.

A3 R15

s0
column dec.

A4 s1
A5 s2
s3

d0 d0 40
Read Operation BL = Red BL = Green
R0
A0 row dec.

A3 R15

s0
column dec.

A4 s1
A5 s2
s3

d0 d0 41
Read Operation and Sense
Amplifiers
make V as small
C  V as possible
tp =
Iav

large small

Idea: Use Sense Amplifer

small
transition s.a.

input output

42
Differential Sensing ―SRAM
V DD V DD
PRE

PRE
BIT
BL BL
EQ
BL VDD
WL i

WL0 BL

SRAM cell i SAE !out


Diff.
out
x Sense x
Amp

Output

SRAM sensing scheme


43
Current Latch based Sense Amplifier
O2
SAE
SAE
PINV PINVB

O1
O2 SAE O1
NINV NINVB

NDR NDRB 1.SAE = low => O1 and O2


I1 I2 are precharged to VDD
VBL=VDD
VBL 2.SAE = high => both O1
=VDD -  and O2 starts to discharge
NCLK 3.If !VBL < VBL=> I1 > I2 => O1
SAE discharges at a faster rate
4.When the voltage diff.
between O1 and O2 is high
enough the cross-coupled
inverter amplifies it
44
Current Latch based Sense Amplifier
O1 OUT
SAE
PINV PINVB SAE

O1
O2
NINV NINVB
O2 OUTB

NDR NDRB
VIN=VTEST VINB=VTEST-∆ O2

SAE O1
NCLK
SAE

The output latch converts the SAE OUT OUTB


dynamic O1 & O2 to static
signals OUT and OUTB 46
Offset Voltage
Assume width of NDRB is larger
SAE
SAE than the width of NDR
PINV PINVB

O1 I1  WDR (VDD −Vs −Vth )


O2
NINV NINVB I 2  WDRB (VDD −Vs −  −Vth )
NDR NDRB
if WDRB = WDR + w
I1 I2 even if   0,
VBL=VDD
VBL it is possible I 2  I1
=VDD - 

SAE
NCLK To have I1 = I 2 under W mismatch
we need to have a minimum 

Minimum input voltage difference required for correct


sensing is defined as the offset voltage 47
Write Operation BL = Red BL = Green
R0
A0 row dec.

A3 R15

s0
column dec.

A4 s1
A5 s2
s3

d0 d0 48
Write Circuits
VDD
BL = VDD
PRE

WL0 BL=0
WL
cell
Cbit Cbit Q
BL BL
s0 s0 Q
s0 WL

read path

WE
WE WE Sense Amp

d0 d0=0 49

You might also like