Digital Integrated

Circuits
A Design Perspective

Semiconductor
Memories

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Chapter Overview
 Memory Classification
 Memory Architectures
 The Memory Core
 Periphery
 Reliability
 Case Studies

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Semiconductor Memory Classification

Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory

Random Non-Random EPROM Mask-Programmed

Access Access
E2PROM Programmable (PROM)

SRAM FIFO FLASH

DRAM LIFO
Shift Register
CAM

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Memory Architecture: Decoders
M bits M bits

S0 S0
Word 0 Word 0
S1
Word 1 A0 Word 1
S2 Storage Storage
Word 2 A1 Word 2
cell cell

Nwords
A K2 1
SN 2 2
Word N 2 2 Decoder
Word N 2 2
SN 2 1
Word N 2 1 Word N 2 1
K 5 log2N

Input-Output Input-Output
(M bits) (M bits)

Intuitive architecture for N x M memory Decoder reduces the number of select signals
Too many select signals:
N words == N select signals
K = log2N

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Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing to
rail-to-rail amplitude

Selects appropriate
word

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Hierarchical Memory Architecture

Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
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Read-Only Memory Cells
BL BL BL
VDD
WL
WL WL
1

BL BL BL

WL WL
WL
0
GND

Diode ROM MOS ROM 1 MOS ROM 2

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MOS OR ROM
BL[0] BL[1] BL[2] BL[3]

WL[0]
V DD
WL[1]

WL[2]
V DD

WL[3]

V bias

Pull-down loads

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MOS NOR ROM
V DD
Pull-up devices

WL[0]

GND
WL [1]

WL [2]

GND
WL [3]

BL [0] BL [1] BL [2] BL [3]

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MOS NOR ROM Layout
Cell (9.5 x 7 )

Programmming using the

Active Layer Only

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

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MOS NOR ROM Layout
Cell (11 x 7 )

Programmming using
the Contact Layer Only

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

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MOS NAND ROM
V DD
Pull-up devices

BL [0] BL [1] BL [2] BL [3]

WL [0]

WL [1]

WL [2]

WL [3]

All word lines high by default with exception of selected row

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Precharged MOS NOR ROM
f V DD
pre

Precharge devices

WL [0]

GND
WL [1]

WL [2]
GND
WL [3]

BL [0] BL [1] BL [2] BL [3]

PMOS precharge device can be made as large as necessary,

but clock driver becomes harder to design.

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Non-Volatile Memories
The Floating-gate transistor (FAMOS)

Floating gate Gate

D
Source Drain

tox G

tox
S
n+ p n+_
Substrate

Device cross-section Schematic symbol

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Floating-Gate Transistor Programming

20 V 0V 5V

20 V 0V 5V
10 V 5V 2 5V 2 2.5 V

S D S D S D

Avalanche injection Removing programming Programming results in

voltage leaves charge trapped higher V T .

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 FLOTOX EEPROM
Floating gate Gate I

Source Drain

20–30 nm -10 V V GD

10 V

n1 n1
Substrate
p
10 nm

Fowler-Nordheim
FLOTOX transistor
I-V characteristic

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EEPROM Cell
BL

WL
Absolute threshold control
is hard
VDD Unprogrammed transistor
might be depletion
 2 transistor cell

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Flash EEPROM

Control gate
Floating gate

erasure Thin tunneling oxide

n 1 source n 1 drain
programming
p-substrate

Many other options …

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Characteristics of State-of-the-art NVM

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Read-Write Memories (RAM)
 STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential

 DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended

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6-transistor CMOS SRAM Cell

WL

V DD
M2 M4
Q
M5 Q M6

M1 M3

BL BL

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CMOS SRAM Analysis (Read)
WL

V DD
BL M4
BL
Q= 0
Q= 1 M6
M5

V DD M1 V DD V DD

Cbit Cbit

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CMOS SRAM Analysis (Read)
1.2
1
Voltage Rise (V)

0.8
0.6
0.4
0.2
Voltage rise [V]
0
0 0.5 1 1.2 1.5 2 2.5 3
Cell Ratio (CR)

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CMOS SRAM Analysis (Write)
WL
V DD
M4

Q= 0 M6
M5
Q= 1

M1
V DD
BL = 1 BL = 0

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6T-SRAM — Layout
VDD
M2 M4

Q Q
M1 M3

GND
M5 M6 WL

BL BL

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Resistance-load SRAM Cell
WL
V DD
RL RL

Q Q
M3 M4

BL M1 M2 BL

Static power dissipation -- Want R L large

Bit lines precharged to V DD to address t p problem

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SRAM Characteristics

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3-Transistor DRAM Cell
BL 1 BL 2

WWL

RWL WWL

M3 RWL

M1 X X V DD 2 V T
M2
V DD
CS BL 1

BL 2 V DD 2 V T DV

No constraints on device ratios

Reads are non-destructive
Value stored at node X when writing a “1” = V WWL-VTn

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3T-DRAM — Layout
BL2 BL1 GND

RWL
M3

M2

WWL
M1

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1-Transistor DRAM Cell

Write: C S is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance
CS
V = VBL – V PRE = V BIT – V PRE ------------
C S + CBL

Voltage swing is small; typically around 250 mV.

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DRAM Cell Observations
 1T DRAM requires a sense amplifier for each bit line, due
to charge redistribution read-out.
 DRAM memory cells are single ended in contrast to
SRAM cells.
The read-out of the 1T DRAM cell is destructive; read
and refresh operations are necessary for correct
operation.
 Unlike 3T cell, 1T cell requires presence of an extra
capacitance that must be explicitly included in the design.
 When writing a “1” into a DRAM cell, a threshold voltage
is lost. This charge loss can be circumvented by
bootstrapping the word lines to a higher value than VDD

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Sense Amp Operation

V BL V(1)

V PRE
D V(1)

V(0)
Sense amp activated t
Word line activated

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 1-T DRAM Cell
Capacitor

M 1 word
line
Metal word line
SiO2
Poly
n+ n+ Field Oxide Diffused
bit line
Inversion layer
Poly
induced by Polysilicon
Polysilicon
plate bias gate plate

Cross-section Layout

Uses Polysilicon-Diffusion Capacitance

Expensive in Area

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SEM of poly-diffusion capacitor 1T-DRAM

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 Advanced 1T DRAM Cells
Word line
Cell plate Capacitor dielectric layer
Insulating Layer

Cell Plate Si

Transfer gate Isolation

Refilling Poly
Capacitor Insulator Storage electrode

Storage Node Poly

Si Substrate
2nd Field Oxide

Trench Cell Stacked-capacitor Cell

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Periphery

 Decoders
 Sense Amplifiers
 Input/Output Buffers
 Control / Timing Circuitry

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Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion

(N)AND Decoder

NOR Decoder

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Hierarchical Decoders
Multi-stage implementation improves performance
•••

WL 1

WL 0

A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3

•••
NAND decoder using
2-input pre-decoders
A1 A0 A0 A1 A3 A2 A2 A3

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 Dynamic Decoders
Precharge devices GND GND VDD

WL 3
VDD
WL 3

WL 2
WL 2 VDD

WL 1
WL 1
V DD
WL0
WL 0

VDD A0 A0 A1 A1
A0 A0 A1 A1

2-input NOR decoder 2-input NAND decoder

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 4-input pass-transistor based column
decoder BL BL BL BL 0 1 2 3

S0
A0
S1

S2

A1 S3

2-input NOR decoder

D

Advantages: speed (tpd does not add to overall memory access time)
Only one extra transistor in signal path
Disadvantage: Large transistor count

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4-to-1 tree based column decoder
BL 0 BL 1 BL 2 BL 3

A0

A0

A1

A1

D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions: buffers
progressive sizing
combination of tree and pass transistor approaches

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 Decoder for circular shift-register

V DD V DD V DD V DD V DD V DD

WL 0 WL 1 WL 2
f f f f f f
• • •
R f f R f f R f f
V DD

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Sense Amplifiers
make V as small
tp = C V
---------------- as possible
Iav

large small

Idea: Use Sense Amplifer

small
transition s.a.

input output

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Differential Sense Amplifier
V DD

M3 M4
y Out

bit M1 M2 bit

SE M5

Directly applicable to
SRAMs

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Differential Sensing ― SRAM
V DD V DD
PC

BL BL V DD V DD
EQ
y M3 M4 2y

WL i
x M1 M2 2x x 2x

SE M5 SE

SE
SRAM cell i

V DD
Diff.
x Sense 2x Output
Amp y

SE
Output
(a) SRAM sensing scheme (b) two stage differential amplifier

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Latch-Based Sense Amplifier (DRAM)
EQ
BL BL
VDD

SE

SE

Initialized in its meta-stable point with EQ

Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.

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Reliability and Yield

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Noise Sources in 1T DRam
BL substrate Adjacent BL
CWBL
a -particles

WL

leakage
CS
electrode

Ccross

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 Open Bit-line Architecture —Cross Coupling

EQ

WL 1 WL 0 WL WL D WL 0 WL 1
C WBL D C WBL
BL BL
C BL Sense C BL
C C C Amplifier C C C

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 Folded-Bitline Architecture

WL 1 WL 1 WL 0 C WL 0 WL D WL D
WBL

BL CBL x y

… C C C Sense
C C C
EQ Amplifier

BL CBL x y
CWBL

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Transposed-Bitline Architecture
Ccross
BL 9
BL
SA
BL
BL 99
(a) Straightforward bit-line routing

Ccross
BL 9
BL
SA
BL
BL 99

(b) Transposed bit-line architecture

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Alpha-particles (or Neutrons)
a -particle
WL V DD
BL
SiO 2
n1 1 2
1 2
2
1 2
1 2
1 2
1

1 Particle ~ 1 Million Carriers

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Redundancy
Row
Redundant Address
rows
Fuse
:
Bank
Redundant
columns
Memory
Array

Row Decoder
Column Decoder Column
Address

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Error-Correcting Codes
Example: Hamming Codes

e.g. B3 Wrong
with
1

1 =3

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Redundancy and Error Correction

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Sources of Power Dissipation in
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V DD

CHIP I DD 5 S C iD V if1S I DCP

nC DE V INT f m

selected mi act
C PT V INT f

I DCP
n

ROW non-selected m(n 2 1)i hld

DEC ARRAY

mC DE V INT f
PERIPHERY
COLUMN DEC

V SS

From [Itoh00] Memories

Programmable Logic Array
Pseudo-NMOS PLA
V DD
GND GND GND GND
GND

GND

GND

V DD X0 X0 X1 X1 X2 X2 f0 f1

AND-plane OR-plane

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Dynamic PLA
f AND

GND V DD
f OR

f OR
f AND
V DD X0 X0 X1 X1 X2 X2 f0 f 1 GND

AND-plane OR-plane

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Semiconductor Memory Trends
(updated)

From [Itoh01] Memories

Trends in Memory Cell Area

From [Itoh01] Memories

Semiconductor Memory Trends

Technology feature size for different SRAM generations

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