My First Niosii
My First Niosii
My First Niosii
CONTENTS
Chapter 1 Hardware Design...........................................................................1
1.1 Required Features................................................................................... 1 1.2 Creation of Hardware Design.................................................................. 1 1.3 Download Hardware Design to Target FPGA........................................ 44
Chapter 2
Chapter 3
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Chapter 1
Hardware Design
This tutorial provides comprehensive information that will help you understand how to create a FPGA based SOPC system implementing on your FPGA development board and run software upon it.
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Figure 1-2 New Project Wizard 2. Choose a working directory for this project, type project name and top-level entity name as shown in Figure 1-3. Then click Next, you will see a window as shown in Figure 1-4.
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Figure 1-3 Input the working directory, the name of project, top-level design entity
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settings the same as the Figure 1-5. Then click Next to next window as shown in Figure 1-6.
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Figure 1-5 New Project Wizard: Family & Device Settings [page 3 of 5] 4. Click Next and will see a window as shown in Figure 1-7. Figure 1-7 is a summary about our new project. Click Finish to finish new project. Figure 1-8 show a new complete project.
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Figure 1-10 Create New SOPC System [0] 6. Rename System Name as shown in Figure 1-11. Click OK and your will see a window as shown in Figure 1-12.
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Figure 1-12 Create New System [2] 7. Click the Name of the Clock Settings table, rename clk_0 to clk_50. Press Enter to complete the update. See Figure 1-13.
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Figure 1-16 Add Nios II CPU completely 10. Choose cpu_0 and right-click then choose rename, after this, you can update cpu_0 to cpu. See Figure 1-17 and Figure 1-18.
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Figure 1-18 Rename CPU Name (2) 11. Choose Library > Interface Protocols > Serial > JTAG UART to open wizard of adding JTAG UART. See Figure 1-19 and Figure 1-20.
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Figure 1-22 Rename JTAG UART 15. Choose Library > Memories and Memory Controllers > On-Chip > On-Chip Memory (RAM or ROM) to open wizard of adding On-Chip memory. See Figure 1-23 and Figure 1-24.
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Figure 1-24 On-Chip Memory Box 16. Modify Total memory size to 204800 as shown in Figure 1-25. Click Finish to return to the window as in Figure 1-26.
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18. Click cpu in the component list on the right part to edit the component. Update Reset vector and
Exception Vector as shown in Figure 1-28. Then click Finish to return to the window as shown
Figure 1-29.
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22. Choose System > Auto-Assign Base Addresses as shown in Figure 1-34. After that, you will find that there is no error in the message window as shown in Figure 1-35.
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Figure 1-35 No errors or warnings 23. Click Generate and then pop a window as shown in Figure 1-36. Click Save and the generation start. Figure 1-37 shows the generate process. If there is no error in the generation, the window will show successful as shown in Figure 1-38.
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Figure 1-41 New Verilog File 33. Choose Verilog HDL File and click OK to return to the window as shown in Figure 1-42. Figure 1-42 show a blank verilog file.
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35. Choose Save Icon in the tool bar. There will appear a window as shown in Figure 1-46. Click
Save.
Figure 1-46 Save Verilog file 36. Choose Processing > Start Compilation as shown in Figure 1-47. Figure 1-48 shows the compilation process.
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Figure 1-48 Execute Compilation Note: In the compilation, if there is the error which shows Error: The core supply voltage of 1.0v is illegal for the currently selected part., you should modify the text set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.0V to set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V in the myfirst_niosii.qsf of the project.
37. A window that shows successfully will appear as shown in Figure 1-49.
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Figure 1-49 Compilation project completely 45. Choose Assignments > Pins to open pin planner as shown in Figure 1-50. Figure 1-51 show blank pins.
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12. Click Hardware Setup in the top, left comer of the Quartus II programmer window. The Hardware Setup dialog box appears. 13. Select USB-Blaster from the Currently selected hardware drop-down list box. Note: If the appropriate download cable does not appear in the list, you must first install drivers for the cable. Refer to Quartus II Help for information on how to install the driver. See Figure 1-53.
Figure 1-53 Hardware Setup Window 14. Click Close. 15. Turn on the Program/Configure option for the programming file.(See Figure 1-54 for an example). 16. Click Start.
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Figure 1-54 Quartus II Programmer The Progress meter sweeps to 100% after the configuration finished. When configuration is complete, the FPGA is configured with the Nios II system, but it does not yet have a C program in memory to execute.
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Chapter 2
This Chapter covers build flow of Nios II C coded software program. The Nios II IDE build flow is an easy-to-use graphical user interface (GUI) that automates build and makefile management. The Nios II IDE integrates a text editor, debugger, the Nios II flash programmer, the Quartus II Programmer, and the Nios II C-to-Hardware (C2H) compiler GUI. The included example software application templates make it easy for new software programmers to get started quickly. In this section you will use the Nios II IDE to compile a simple C language example software program to run on the Nios II standard system configured onto the FPGA on your development board. You will create a new software project, build it, and run it on the target hardware. You will also edit the project, re-build it, and set up a debug session.
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Figure 2-2 Switch Workspace (2) 3. Choose File->New->NIOS II C/C++ Application to open the New Project Wizard. 4. In the New Project wizard, make sure the following things:
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Select the Hello World project template. Give the project a name. (hello_world_0 is default name) Select the target hardware system PTF file that locates in where the previously created hardware project resides as shown in Figure 2-3.
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Figure 2-4 Nios II IDE C++ Project Perspective for hello_world_0 When you create a new project, the NIOS II IDE creates two new projects in the NIOS II C/C++ Projects tab: hello_world_0 is your C/C++ application project. This project contains the source and header files for your application. hello_world_0_syslib is a system library that encapsulates the details of the Nios II system hardware. Note: When you build the system library for the first time the NIOS II IDE automatically generates files useful for software development, including: Installed IP device drivers, including SOPC component device drivers for the NIOS II hardware system Newlib C library, which is a richly featured C library for the NIOS II processor. NIOS software packages which includes NIOS II hardware abstraction layer, NicheStack TCP/IP
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Network stack, NIOS II host file system, NIOS II read-only zip file system and Micriums C/OS-II real time operating system(RTOS). system.h, which is a header file that encapsulates your hardware system. alt_sys_init.c, which is an initialization file that initializes the devices in the system. Hello_world_0.elf, which is an executable and linked format file for the application located in hello_world_0 folder under Debug.
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Figure 2-5 Nios II IDE hello_world_0 Build Completed After compilation complete, right-click the hello_world_0 project, choose Run As, and choose NIOS II Hardware. The IDE begins to download the program to the target FPGA development board and begins execution. When the target hardware begins executing the program, the message Hello from Nios II! appears in the NIOS II IDE Console tab. See Figure 2-6 for an example.
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Figure 2-6 Hello_World_0 Program Output Now you have created, compiled, and run your first software program based on NIOS II. And you can perform additional operations such as configuring the system properties, editing and re-building the application, and debugging the source code.
#include "system.h" #include "altera_avalon_pio_regs.h" int main() { printf("Hello from Nios II!\n"); int count = 0; int delay; while(1) { IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, count & 0x01); delay = 0; while(delay < 2000000) { delay++; } count++; } return 0; } 2. Save the project. 3. Recompile the file by right-clicking hello_world_0 in the NIOS II C/C++ Projects tab and choosing Run > Run As > Nios II Hardware. Note: You do not need to build the project manually; the Nios II IDE automatically re-builds the
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program before downloading it to the FPGA. 4. Orient your development board so that you can observe LEDG blinking.
Figure 2-7 system.h Location If you look at the system.h file for the Nios II project example used in this tutorial, you will notice the pio_led function. This function controls the LED. The Nios II processor controls the PIO ports (and thereby the LED) by reading and writing to the register map. For the PIO, there are four registers: data, direction, interrupt mask, and edge capture. To turn the LED on and off, the application writes to the PIO data register.
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The PIO core has an associated software file altera_avalon_pio_regs.h. This file defines the cores register map, providing symbolic constants to access the low-level hardware. The altera_avalon_pio_regs.h file is located in altera\<version number>\ip\sopc_builder_ip\altera_avalon_pio. When you include the altera_avalon_pio_regs.h file, several useful functions that manipulate the PIO core registers are available to your program. In particular, the function IOWR_ALTERA_AVALON_PIO_DATA (base, data) can write to the PIO data register, turning the LED on and off. The PIO is just one of many SOPC peripherals that you can use in a system. To learn about the PIO core and other embedded peripheral cores, refer to Quartus II Version <version> Handbook Volume 5: Embedded Peripherals. When developing your own designs, you can use the software functions and resources that are provided with the Nios II HAL. Refer to the Nios II Software Developers Handbook for extensive documentation on developing your own Nios II processor-based software applications.
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Figure 2-8 Set Breakpoint 2. To debug your application, right-click the application (hello_world_0 by default) and choose Debug as > Nios II Hardware. 3. If the Confirm Perspective Switch message box appears, click Yes. After a moment, the main () function appears in the editor. A blue arrow next to the first line of code indicates that execution stopped at that line. 5. Choose Run-> Resume to resume execution. When debugging a project in the Nios II IDE, you can pause, stop or single step the program, set breakpoints, examine variables, and perform many other common debugging tasks. Note: To return to the Nios II C/C++ project perspective from the debug perspective, click the two arrows >> in the top right corner of the GUI.
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5. Click OK to close the Properties for hello_world_0_syslib dialog box and return to the IDE workbench. Note: If you make changes to the system properties you must rebuild your project. To rebuild, right-click the hello_world_0 project in the Nios II C/C++ Projects tab and choose Build Project.
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Chapter 3
With the density of FPGAs increasing, the need for larger configuration storage is also increasing. If your system contains a common flash interface (CFI) flash memory, you can use your system for FPGA configuration storage as well.
Figure 3-2 Avalon-MM Tristate Bridge Box 2. Click Finish to close Avalon-MM Tristate Bridge box, and return to the window as shown in Figure 3-3.
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Figure 3-4
4. Choose Library > Memories and Memory Controllers > Flash > Flash Memory Interface
(CFI) to open Flash Memory Interface (CFI) wizard. See Figure 3-5 and Figure 3-6.
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Figure 3-7 Modify Address Width in Flash Memory Interface (CFI) 6. Choose Timing tab, modify settings as shown in Figure 3-8.
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Figure 3-12 Choose data box 11. Click Finish to close the Avalon-MM Tristate Bridge Box. Choose System > Auto-Assign Base Addresses, then click Generate to generate the sopc.
FL_ADDR, FL_CE_N, FL_DQ, FL_OE_N, FL_RESET_N, FL_RY, FL_WE_N, FL_WP_N, ); input output [7:0] CLOCK_50; LED;
//////////// Flash ////////// output output inout output output input output output [7:0] [22:0] FL_ADDR; FL_CE_N; FL_DQ; FL_OE_N; FL_RESET_N; FL_RY; FL_WE_N; FL_WP_N;
DE2_115_SOPC DE2_115_SOPC_inst (
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.clk_50
(CLOCK_50),
.out_port_from_the_pio_led (LED),
.reset_n );
(1'b1)
CLOCK_50 FL_ADDR[0] FL_ADDR[1] FL_ADDR[2] FL_ADDR[3] FL_ADDR[4] FL_ADDR[5] FL_ADDR[6] FL_ADDR[7] FL_ADDR[8] FL_ADDR[9] FL_ADDR[10] FL_ADDR[11] FL_ADDR[12] FL_ADDR[13] FL_ADDR[14] FL_ADDR[15] FL_ADDR[16] FL_ADDR[17] FL_ADDR[18] FL_ADDR[19] FL_ADDR[20] FL_ADDR[21] FL_ADDR[22] FL_CE_N FL_DQ[0] FL_DQ[1] FL_DQ[2] FL_DQ[3] FL_DQ[4] FL_DQ[5] FL_DQ[6] FL_DQ[7] FL_OE_N FL_RESET_N FL_RY FL_WE_N FL_WP_N LED[0] LED[1]
PIN_Y2 PIN_AG12 PIN_AH7 PIN_Y13 PIN_Y14 PIN_Y12 PIN_AA13 PIN_AA12 PIN_AB13 PIN_AB12 PIN_AB10 PIN_AE9 PIN_AF9 PIN_AA10 PIN_AD8 PIN_AC8 PIN_Y10 PIN_AA8 PIN_AH12 PIN_AC12 PIN_AD12 PIN_AE10 PIN_AD10 PIN_AD11 PIN_AG7 PIN_AH8 PIN_AF10 PIN_AG10 PIN_AH10 PIN_AF11 PIN_AG11 PIN_AH11 PIN_AF12 PIN_AG8 PIN_AE11 PIN_Y1 PIN_AC10 PIN_AE12 PIN_E21 PIN_E22
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3. Click OK to close the Properties for hello_world_0_syslib box and re-build hello_world_0
project.
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