Functional Components of a Computer

Computer: A computer is a combination of hardware and software resources which integrate together
and provides various functionalities to the user. Hardware are the physical components of a computer like
the processor, memory devices, monitor, keyboard etc. while software is the set of programs or
instructions that arerequired by the hardware resources to function properly. There
are a few basic components that aid the working-cycle of a computer i.e. the Input- Process- Output
Cycle and these are called as the functional components of a computer. It needs certain input, processes
that input and produces the desired output. The input unit takes the input, the central processing unit does
the processing of data and the output unit produces the output. The memory unit holds the data and
instructions during the processing.
Digital Computer: A digital computer can be defined as a programmable machine which reads the binary
data passed as instructions, processes this binary data, and displays a calculated digital output. Therefore,
Digital computers are those that work on the digital data.
Details of Functional Components of a Digital Computer

 Input Unit: The input unit consists of input devices that are attached to the computer. These
devices take input and convert it into binary language that the computer understands. Some of
the common input devices are keyboard, mouse, joystick, scanner etc.
 Central Processing Unit (CPU) : Once the information is entered into the computer by the input
device, the processor processes it. The CPU is called the brain of the computer because it is the
control center of the computer. It first fetches instructions from memory and then interprets them
so as to know

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 what is to be done. If required, data is fetched from memory or input device. Thereafter CPU
executes or performs the required computation and then either stores the output or displays on the
output device. The CPU has three main components which are responsible for different functions –
Arithmetic Logic Unit (ALU), Control Unit (CU) and Memory registers
 Arithmetic and Logic Unit (ALU): The ALU, as its name suggests performs mathematical
calculations and takes logical decisions. Arithmetic calculations include addition, subtraction,
multiplication and division. Logical decisions involve comparison of two data items to see which
one is larger or smaller or equal.
 Control Unit : The Control unit coordinates and controls the data flow in and out of CPU and also
controls all the operations of ALU, memory registers and also input/output units. It is also
responsible for carrying out all the instructions stored in the program. It decodes the fetched
instruction, interprets it and sends control signals to input/output devices until the required operation
is done properly by ALU and memory.
 Memory Registers: A register is a temporary unit of memory in the CPU. These are used to store
the data which is directly used by the processor. Registers can be of different sizes(16 bit, 32 bit, 64
bit and so on) and each register inside the CPU has a specific function like storing data, storing an
instruction, storing address of a location in memory etc. The user registers can be used by an
assembly language programmer for storing operands, intermediate results etc. Accumulator (ACC)
is the main register in the ALU and contains one of the operands of an operation to be performed in
the ALU.
 Memory : Memory attached to the CPU is used for storage of data and instructions and is called
internal memory The internal memory is divided into many storage locations, each of which can
store data or instructions. Each memory location is of the same size and has an address. With the
help of the address, the computer can read any memory location easily without having to search the
entire memory. when a program is executed, it’s data is copied to the internal memory ans is stored
in the memory till the end of the execution. The internal memory is also called the Primary memory
or Main memory. This memory is also called as RAM, i.e. Random Access Memory. The timeof
access of data is independent of its location in memory, therefore this memory is also called
Random Access memory (RAM). Output Unit: The output unit consists of output devices
that are attached with the computer. It converts the binary data coming from CPU to human
understandable form. The common output devices are monitor, printer, plotter etc.

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Interconnection between Functional Components
A computer consists of input unit that takes input, a CPU that processes the input and an output unit that
produces output. All these devices communicate with eachother through a common bus. A bus is a
transmission path, made of a set of conducting wires over which data or information in the form of
electric signals, ispassed from one component to another in a computer. The bus can be of three types –
Address bus, Data bus and Control Bus.
Following figure shows the connection of various functional components:

The address bus carries the address location of the data or instruction. The data bus carries data from one
component to another and the control bus carries the control signals. The system bus is the common
communication path that carries signals to/from CPU, main memory and input/output devices. The
input/output devices communicate with the system bus through the controller circuit which helps in
managing various input/output devices attached to the computer.

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Bus

Bus is a group of conducting wires which carries information, all the peripherals are connected to
microprocessor through Bus.

There are three types of buses.

1. Address bus –
It is a group of conducting wires which carries address only.Address bus is unidirectional because
data flow in one direction, from microprocessor to memory or from microprocessor to Input/output
devices (That is, Out ofMicroprocessor).

The Length of the address bus determines the amount of memory a system can address. Such as a
system with a 32-bit address bus can address 2^32 memory locations. If each memory location
holds one byte, the addressable memory space is 4 GB.However, the actual amount of memory that
can be accessed is usually much less than this theoretical limit due to chipset and motherboard
limitations.

2. Data bus

It is a group of conducting wires which carries Data only.Data bus is bidirectional because data
flow in both directions, from microprocessor to memory or Input/Output devices and from memory
or Input/Output devices tomicroprocessor.
The width of the data bus is directly related to the largest number that the bus can carry, such as an
8 bit bus can represent 2 to the power of 8 unique values, this equates to the number 0 to 255.A 16
bit bus can carry 0 to 65535.

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 3. Control bus

It is a group of conducting wires, which is used to generate timing and control signals to control all
the associated peripherals, microprocessor uses control bus to process data that is what to do with
selected memory location. Some control signals are:
 Memory read
 Memory write
 I/O read
 I/O Write
 Opcode fetch
If one line of control bus may be the read/write line.If the wire is low (no electricity flowing) then
the memory is read, if the wire is high (electricity is flowing) then the memory is written.

Bus Arbitration

Bus arbitration refers to the process by which the current bus master accesses and then leaves the control
of the bus and passes it to the another bus requesting processor unit. The controller that has access to
a bus at an instance is knownas Bus master.
A conflict may arise if the number of DMA controllers or other controllers or processors try to access the
common bus at the same time, but access can be given to only one of those. Only one processor or
controller can be Bus master at the same point of time. To resolve these conflicts, Bus Arbitration
procedure is implemented
to coordinate the activities of all devices requesting memory transfers. The selection of the bus master
must take into account the needs of various devices by establishing a priority system for gaining
access to the bus. The Bus Arbiter decides who would become current bus master.
There are two approaches to bus arbitration:

1. Centralized bus arbitration – A single bus arbiter performs the requiredarbitration.

2. Distributed bus arbitration – All devices participate in the selection of thenext bus master.

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Methods of Centralized BUS Arbitration –
There are three bus arbitration methods:
(i) Daisy Chaining method –
It is a simple and cheaper method where all the bus masters use the same line for making bus requests.
The bus grant signal serially propagates through each master until it encounters the first one that is
requesting access to the bus. This master blocks the propagation of the bus grant signal, therefore any
other requesting module will not receive the grant signal and hence cannot access the bus. During
any bus cycle, the bus master may be any device – the processor or any DMA controller unit, connected
to the bus.

Advantages –

 Simplicity and Scalability.

 The user can add more devices anywhere along the chain, up to a certainmaximum value.

Disadvantages –

 The value of priority assigned to a device is depends on the position of masterbus.

 Propagation delay is arises in this method.

 If one device fails then entire system will stop working.

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(ii) Polling or Rotating Priority method
In this, the controller is used to generate the address for the master (unique priority), the number of
address lines required depends on the number of masters connected in the system. The controller
generates a sequence of master address. When the requesting master recognizes its address, it activates the
busy line and begins to use the bus.

Advantages –

 This method does not favor any particular device and processor.

 The method is also quite simple.

 If one device fails then entire system will not stop working.

Disadvantages –

 Adding bus masters is difficult as increases the number of address lines of thecircuit.

(iii) Fixed priority or Independent Request method

In this, each master has a separate pair of bus request and bus grant lines and eachpair has a priority
assigned to it.

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The built-in priority decoder within the controller selects the highest priority request and asserts the
corresponding bus grant signal.

Advantages –

 This method generates fast response.

Disadvantages –

 Hardware cost is high as large no. of control lines are required.

Distributed BUS Arbitration

In this, all devices participate in the selection of the next bus master. Each device on the bus is assigned a
4bit identification number. The priority of the device will be determined by the generated ID.

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Bus and Memory Transfers

A digital system composed of many registers, and paths must be provided to transfer information from
one register to another. A bus structure, on the other hand, is more efficient for transferring information
between registers in a multi- register configuration system.

A bus consists of a set of common lines, one for each bit of register, through which binary information is
transferred one at a time. Control signals determine which register is selected by the bus during a
particular register transfer. The following block diagram shows a Bus system for four registers. It is
constructed with the help of four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two
selection inputs (S1 and S2).

The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers. The
selection lines choose the four bits of one register and transfer them into the four-line common bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs ofall four multiplexers
are selected and applied to the outputs that forms the bus.

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This, in turn, causes the bus lines to receive the content of register A since the outputs of this register are
connected to the 0 data inputs of the multiplexers.

Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content provided by
register B.

The following function table shows the register that is selected by the bus for each of the four possible
binary values of the Selection lines.

A bus system can also be constructed using three-state gates instead ofmultiplexers.

The three state gates can be considered as a digital circuit that has three gates, two of which are signals
equivalent to logic 1 and 0 as in a conventional gate. However, the third gate exhibits a high-impedance
state.

The most commonly used three state gates in case of the bus system is a buffer gate.

The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with three-state buffers.

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 o The outputs generated by the four buffers are connected to form a single busline.
o Only one buffer can be in active state at a given point of time.
o The control inputs to the buffers determine which of the four normal inputswill communicate
with the bus line.
o A 2 * 4 decoder ensures that no more than one control input is active at anygiven point of time.

Memory Transfer

Most of the standard notations used for specifying operations on memory transferare stated below.

o The transfer of information from a memory unit to the user end is calleda Read operation.
o The transfer of new information to be stored in the memory is called a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the memorytransfer operations.
o The address register is designated by AR and the data register by DR.
o Thus, a read operation can be stated as:

1. Read: DR ← M [AR]

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 o The Read statement causes a transfer of information into the data register(DR) from the
memory word (M) selected by the address register (AR).
o And the corresponding write operation can be stated as:

1. Write: M [AR] ← R1
o The Write statement causes a transfer of information from register R1 intothe memory word (M)
selected by address register (AR).

PROCESSOR ORGANIZATION

Figure below is a simplified view of a processor, indicating its connection to the rest of the system
via the system bus.

The ALU does the actual computation or processing of data. The control unit controls the movement of
data and instructions into and out of the processor and controls the operation of the ALU. In addition, the
figure shows a minimal internal memory, consisting of a set of storage locations, called registers.

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Figure below depicts is a slightly more detailed view of the processor.

The data transfer and logic control paths are indicated, including an element labeled internal processor
bus. This element is needed to transfer data between the various registers and the ALU because the ALU
in fact operates only on data in the internal processor memory. The figure also shows typical basic
elements of the ALU. Note the similarity between the internal structure of the computer as a wholeand the
internal structure of the processor. In both cases, there is a small collection of major elements (computer:
processor, I/O, memory; processor: control unit, ALU, registers) connected by data paths.

General Register based CPU Organization

When we are using multiple general purpose registers, instead of single accumulator register, in the CPU
Organization then this type of organization is known as General register based CPU Organization. In this
type of organization, computer uses two or three address fields in their instruction format. Each address
field may specify a general register or a memory word. If many CPU registers are available for heavily
used variables and intermediate results, we can avoid memory references much of the time, thus vastly
increasing program execution speed, and reducing program size.

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For example:
MULT R1, R2, R3
This is an instruction of an arithmatic multiplication written in assembly language. It uses three address
fields R1, R2 and R3. The meaning of this instruction is:
R1 <-- R2 * R3
This instruction also can be written using only two address fields as:MULT R1, R2
In this instruction, the destination register is the same as one of the sourceregisters. This
means the operation

R1 <-- R1 * R2
The use of large number of registers results in short program with limitedinstructions.

The advantages of General register based CPU organization –

 Efficiency of CPU increases as there are large numbers of registers are used inthis organization.
 Less memory space is used to store the program since the instructions arewritten in compact
way.
The disadvantages of General register based CPU organization –
 Care should be taken to avoid unnecessary usage of registers. Thus, compilers need to be more
intelligent in this aspect.
 Since large number of registers are used, thus extra cost is required in thisorganization.

General register CPU organisation of two type:

1. Register-memory reference architecture (CPU with less register)– In this organisation Source 1 is
always required in register, source 2 can be present either in register or in memory.Here two
address instruction format is the compatible instruction format.
2. Register-register reference architecture(CPU with more register)– In this organisation ALU
operations are performed only on a register data. So operands are required in the register. After
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 manipulation result is also placedin register.Here three address instruction format is the compatible
instruction format.

Stack based CPU Organization

The computers which use Stack-based CPU Organization are based on a data structure called stack. The
stack is a list of data words. It uses Last In First Out (LIFO) access method which is the most popular
access method in most of the CPU. A register is used to store the address of the topmost element of the
stack which is known as Stack pointer (SP). In this organization, ALU operations are performed on stack
data. It means both the operands are always required on the stack. After manipulation, the result is placed
in the stack.

The advantages of Stack based CPU organization –

 Efficient computation of complex arithmetic expressions.
 Execution of instructions is fast because operand data are stored inconsecutive
memory locations.
 Length of instruction is short as they do not have address field.
The disadvantages of Stack based CPU organization –
 The size of the program increases.
Note:Stack based CPU organisation uses zero address instruction.

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Addressing Modes-

The different ways of specifying the location of an operand in an instruction are called as addressing modes.

Types of Addressing Modes-

In computer architecture, there are following types of addressing modes-

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 1. Implied Addressing Mode-

In this addressing mode,

 The definition of the instruction itself specify the operands implicitly.
 It is also called as implicit addressing mode.

Examples-

 The instruction “Complement Accumulator” is an implied mode instruction.

 In a stack organized computer, Zero Address Instructions are implied mode instructions.
(since operands are always implied to be present on the top of the stack)

2. Immediate Addressing Mode-

In this addressing mode,

 The operand is specified in the instruction explicitly.
 Instead of address field, an operand field is present that contains the operand.

Examples-

 ADD 10 will increment the value stored in the accumulator by 10.

 MOV R #20 initializes register R to a constant value 20.

3. Direct Addressing Mode-

In this addressing mode,

 The address field of the instruction contains the effective address of the operand.
 Only one reference to memory is required to fetch the operand.
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 It is also called as absolute addressing mode.

Example-

 ADD X will increment the value stored in the accumulator by the value stored at memory location X.
AC ← AC + [X]

4. Indirect Addressing Mode-

In this addressing mode,

 The address field of the instruction specifies the address of memory location that contains the effective
address of the operand.
 Two references to memory are required to fetch the operand.

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 Example-

 ADD X will increment the value stored in the accumulator by the value stored at memory location
specified by X.
AC ← AC + [[X]]

5. Register Direct Addressing Mode-

In this addressing mode,

 The operand is contained in a register set.
 The address field of the instruction refers to a CPU register that contains the operand.
 No reference to memory is required to fetch the operand.

Example-

 ADD R will increment the value stored in the accumulator by the content of register R.
AC ← AC + [R]

NOTE-

It is interesting to note-
 This addressing mode is similar to direct addressing mode.
 The only difference is address field of the instruction refers to a CPU register instead of main memory.

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 6. Register Indirect Addressing Mode-

In this addressing mode,

 The address field of the instruction refers to a CPU register that contains the effective address of the
operand.
 Only one reference to memory is required to fetch the operand.

Example-

 ADD R will increment the value stored in the accumulator by the content of memory location specified
in register R.
AC ← AC + [[R]]

NOTE-

It is interesting to note-
 This addressing mode is similar to indirect addressing mode.
 The only difference is address field of the instruction refers to a CPU register.

7. Relative Addressing Mode-

In this addressing mode,

 Effective address of the operand is obtained by adding the content of program counter with the address
part of the instruction.

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 Effective Address
= Content of Program Counter + Address part of the instruction

NOTE-

 Program counter (PC) always contains the address of the next instruction to be executed.
 After fetching the address of the instruction, the value of program counter immediately increases.
 The value increases irrespective of whether the fetched instruction has completely executed or not.

8. Indexed Addressing Mode-

In this addressing mode,

 Effective address of the operand is obtained by adding the content of index register with the address part
of the instruction.

Effective Address
= Content of Index Register + Address part of the instruction

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 9. Base Register Addressing Mode-

In this addressing mode,

 Effective address of the operand is obtained by adding the content of base register with the address part
of the instruction.

Effective Address
= Content of Base Register + Address part of the instruction

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 10. Auto-Increment Addressing Mode-

 This addressing mode is a special case of Register Indirect Addressing Mode where-

Effective Address of the Operand

= Content of Register

In this addressing mode,

 After accessing the operand, the content of the register is automatically incremented by step size ‘d’.
 Step size ‘d’ depends on the size of operand accessed.
 Only one reference to memory is required to fetch the operand.

Example-

Assume operand size = 2 bytes.

Here,
 After fetching the operand 6B, the instruction register R AUTO will be automatically incremented by 2.
 Then, updated value of R AUTO will be 3300 + 2 = 3302.
 At memory address 3302, the next operand will be found.

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 NOTE-

In auto-increment addressing mode,

 First, the operand value is fetched.
 Then, the instruction register RAUTO value is incremented by step size ‘d’.

11. Auto-Decrement Addressing Mode-

 This addressing mode is again a special case of Register Indirect Addressing Mode where-

Effective Address of the Operand

= Content of Register – Step Size

In this addressing mode,

 First, the content of the register is decremented by step size ‘d’.
 Step size ‘d’ depends on the size of operand accessed.
 After decrementing, the operand is read.
 Only one reference to memory is required to fetch the operand.

Example-

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 Assume operand size = 2 bytes.
Here,
 First, the instruction register RAUTO will be decremented by 2.
 Then, updated value of R AUTO will be 3302 – 2 = 3300.
 At memory address 3300, the operand will be found.

NOTE-

In auto-decrement addressing mode,

 First, the instruction register RAUTO value is decremented by step size ‘d’.
 Then, the operand value is fetched.

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