K.Dhanumjaya,Dr.MN.Giri Prasad,Dr.K.Padmaraju,Dr.M.

Raja Reddy / International Journal of

Engineering Research and Applications (IJERA) ISSN: 2248-9622
www.ijera.com
Vol. 1, Issue 4, pp.2040-2045

Design of Low Power SRAM in 45 nm CMOS Technology

K.Dhanumjaya Dr.MN.Giri Prasad Dr.K.Padmaraju Dr.M.Raja Reddy

Research Scholar, Professor, JNTUCE, Professor, Asst vise-President,
JNTU Anantapur, Anantapur, JNTUCE, Kakinada, ReNew Power pvt ltd,,
AP, India. AP, India AP, India. Mumbai, India
09493919198

Abstract— SRAM is designed to provide an interface based Cache memories and System-on-chips are
with CPU and to replace DRAMs in systems that commonly used. Due to device scaling there are several
require very low power consumption. Low power design challenges for nanometer SRAM design. As the
SRAM design is crucial since it takes a large fraction integration density of transistors increases, power
of total power and die area in high performance consumption has become a major concern in today’s
processors. A SRAM cell must meet the requirements processors and SoC designs. Considerable attention has
for the operation in submicron/nano ranges. The been paid to the design of low power and high-
scaling of CMOS technology has significant impacts performance SRAMs as they are critical components in
on SRAM cell – random fluctuation of electrical both handheld devices and high performance processors.
characteristics and substantial leakage current. The Different design remedies can be undertaken; a decrease
random fluctuation of electrical property causes the in supply voltage reduces quadratically the dynamic
SRAM cell to have huge mismatch in transistor power and reduces leakage power linearly to the first
threshold voltage. Consequently, the static noise order. A six transistors (6T) SRAM cell configuration is
margin (Read Margin) and the write margin are proposed in this paper which will be a solution to the
degraded dramatically. The SRAM cell tends to be encountered problems in deep submicron and nano scale.
unstable and the low power supply operation becomes Compared with the 8T and 10T SRAM cells, the 6T
hard to achieve. A 6T SRAM cell at 45 nm feature size SRAM cell offers significant advantages in terms of
in CMOS is proposed to accomplish low power power consumption.
memory operation. Initially, this paper presents design The objective of this paper is to investigate the
of 6T SRAM cell considering low power consumption. transistor sizing of the 6T SRAM cell for optimum power
The paper presents the design of SRAM array and delay. A bitline balancing scheme and transmission
involving the decoders, sense amplifiers, transmission gate scheme are proposed for high performance operation
gates using Cadence tools. of SRAM cell. Cadence simulation results confirm that
the proposed scheme achieves nearly 40% of power
Keywords: SRAM, Cadence, Virtuoso, Noise Margin, savings compared to other designs.
45 nm technology
II. OPTIMAL SIZING FOR 6T SRAM
CELL
I. INTRODUCTION
For nearly 40 years CMOS devices have been A. Sizing of 6T SRAM cell
scaled down in order to achieve higher speed,
performance and lower power consumption. Technology The SRAM cell should be sized as small as
scaling results in a significant increase in leakage current possible to achieve high density in memory design.
of CMOS devices. Static Random Access Memory However, issues related to robustness impose a sizing
(SRAM) continues to be one of the most fundamental and constraint to the conventional SRAM design. Fig. 1 shows
vitally important memory technologies today. the conventional 6T SRAM cell configuration. The
transistor ratio between M3 and M6 must be greater than
Because they are fast, robust, and easily 1.2 to keep a proper noise margin during the read
manufactured in standard logic processes, they are nearly operation. The proposed 6T SRAM cell uses 1v for its
universally found on the same die with microcontrollers operation when compared to 1.8V used by conventional
and microprocessors. Due to their higher speed SRAM
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 K.Dhanumjaya,Dr.MN.Giri Prasad,Dr.K.Padmaraju,Dr.M.Raja Reddy / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622
www.ijera.com
Vol. 1, Issue 4, pp.2040-2045

180 nm SRAM cell. In this paper, we propose transistor contents. The SRAM to operate in read mode and write
of size 45nm whose voltage of operation is less than 1V. mode should have "readability" and "write stability"
As the supply voltage used for operation is low, the power respectively. The three different states work as follows:
consumption is scaled down by maximum extent.  Standby: If the word line is not asserted, the
access transistors M5 and M6 disconnect the cell
from the bit lines. The two cross coupled
Moreover, significant improvements in delay and inverters formed by M1 – M4 will continue to
power can be achieved by partitioning the cell array into reinforce each other as long as they are
smaller sub arrays, rather than having a single monolithic connected to the supply.
array.
Each bit in SRAM is stored on four transistors  Reading: Assume that the content of the
that form two cross coupled inverters. This storage cell memory is a 1, stored at Q. The read operation is
has two stable states which are used to denote 0 and 1. done by using the sense amplifiers that pull the
Two additional transistors serve as the access transistors data and produce the output. The row decoders
to control the storage cell during the read and write and column decoders are used to select the
operations. Generally, fewer transistors needed per cell, appropriate cell or cells from which the data is to
the smaller each cell can be. Since the cost of processing be read and are given to the sense amplifiers
silicon wafer is relatively fixed, using smaller cells through transmission gate.
reduces the cost per bit of memory.
Access to the cell is enabled by the word line  Writing: The start of a write cycle begins by
(WL in figure) which controls the two access transistors applying the value to be written to the bit lines.
M5 and M6 which, in turn, control whether the cell If we wish to write a 0, we would apply a 0 to
should be connected to the bit lines: BL and BL bar. They the bit lines, i.e. setting BL bar to 1 and BL to 0.
are used to transfer data for both read and write A 1 is written by inverting the values of the bit
operations. Although it is not strictly necessary to have lines. WL is then asserted and the value that is to
two bit lines, both the signal and its inverse are typically be stored is latched in. Note that the reason this
provided in order to improve noise margins. During read works is that the bit line input-drivers are
accesses, the bit lines are actively driven high and low by designed to be much stronger than the relatively
the inverters in the SRAM cell. weak transistors in the cell itself, so that they can
easily override the previous state of the cross-
coupled inverters.

III. DESIGN FLOW

Cadence design Systems is electronic design

automation software and engineering Services Company
that offers various types of design and verification tasks
that include:

 Virtuoso Platform - Tools for designing full-

custom integrated circuits, includes schematic
entry, behavioral modeling (Verilog-AMS),
circuit simulation, full custom layout, physical
verification, extraction and back-annotation.
Used mainly for analog, mixed-signal, RF, and
Fig 1: 6T SRAM cell standard-cell designs.

B. SRAM Operation  Encounter Platform - Tools for creation of digital

An SRAM cell has three different states it can be integrated circuits. This includes floor planning,
in: standby where the circuit is idle, reading when the data synthesis, test, and place and route. Typically a
has been requested and writing when updating the digital design starts from Verilog netlists.
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 K.Dhanumjaya,Dr.MN.Giri Prasad,Dr.K.Padmaraju,Dr.M.Raja Reddy / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622
www.ijera.com
Vol. 1, Issue 4, pp.2040-2045

schematic and symbol are as shown below.

 Incisive Platform - Tools for simulation and
functional verification of RTL including Verilog,
VHDL and System C based models. Includes
formal verification, formal equivalence
checking, hardware acceleration, and emulation.

The proposed work is done in Virtuoso platform

using gpdk45 nm technology. The flow of design is as
shown below.

Fig 3: Schematic of SRAM cell

B. Decoder Design
The decoder design depends on the size of the
SRAM array that we are going to design. For our
simulation, we have used 6to64 decoder. Using this, we
can also design larger array in the form of banks. The
schematic and symbol are as shown below.

Fig 2: Design Flow

A single bit storage SRAM cell is designed first,
symbol is created for it and then an array is designed
using the SRAM symbol. Other requirements of the
design are decoders, sense amplifiers, and transmission
gates.

A. SRAM cell Design

Single bit storage cell is designed using the nmos Fig 4: 6 to 64 decoder
and pmos transistors picked from the libraries. The

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 K.Dhanumjaya,Dr.MN.Giri Prasad,Dr.K.Padmaraju,Dr.M.Raja Reddy / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622
www.ijera.com
Vol. 1, Issue 4, pp.2040-2045

C. Sense Amplifier Design schematic and symbol are as shown below.

The sense amplifiers have to amplify the data

which is present on the bitlines during the read operation.
The memory cells are weak due to their small size, and
hence cannot the discharge the bitlines fast enough. Also,
the bitlines continue to slew till a large differential
voltage is formed between them. This causes significant
power dissipation since the bitlines have large
capacitances. Hence, by limiting the word line pulse
width we can control the amount of charge pulled down
by the bitlines and hence limit power dissipation. It
consists of two cross coupled gain stages which are
enabled by the sense clock signal. The cross coupled stage
ensures a full amplification of the input signal. This type
of amplifier consumes least amount of power, however
they can potentially be slower since some timing margin Fig 6: Schematic of Transmission gate
is needed for the generation of the sense clock signal. If
the sense amplifiers enabled before sufficient differential
IV. DESIGN OF SRAM ARRAY
voltage is formed, it could lead to a wrong output. Thus,
The row decoder and column decoder are used to
the timing of the sense clock signal needs to be such that
select the particular cell onto which the data is to be
the sense amplifier can operate over various process
written or from which the data is to be read. In our
corners and temperature ranges. The schematic and
simulation, we designed 64X64 array. The schematic of
symbol are as shown below.
the SRAM array is as shown below.

Fig 5: Schematic of sense amplifier

Fig 7: Schematic of SRAM array
D. Transmission Gate Design
Transmission gate is used to improve the noise V. SIMULATION RESULTS
margin. The data, whether from bit or bit bar is given to Cadence simulation of transient analysis and DC
transmission gate that consists of cascaded nmos and analysis gave good results. The results are shown in the
pmos transistors. The input for pmos is 0V, and input for timing diagram. The noise margins are very good and the
nmos is 1V when the data is to be read from SRAM. The
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 K.Dhanumjaya,Dr.MN.Giri Prasad,Dr.K.Padmaraju,Dr.M.Raja Reddy / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622
www.ijera.com
Vol. 1, Issue 4, pp.2040-2045

output is stable. Fig 9: Timing diagram2

Fig 9: Timing diagram 3

Fig 8: Timing Diagram

VI. CONCLUSION

This paper presents the design of SRAM array in

45 nm having very low power consumption. The low
power design of SRAM is investigated and 6T SRAM
architecture is chosen for memory bitcell and an array is
designed with that bitcell. Transient and parametric
analyses were carried out in the simulation process and
the power consumption is estimated. As stated earlier, the
power consumption can further be reduced by partitioning
the array and by using DWL scheme.

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 K.Dhanumjaya,Dr.MN.Giri Prasad,Dr.K.Padmaraju,Dr.M.Raja Reddy / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622
www.ijera.com
Vol. 1, Issue 4, pp.2040-2045

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