FPGA

1. Question 1. What Is Fpga ?

Answer :
A field-programmable gate array is a semiconductor device containing
programmable logic components called "logic blocks", and programmable
interconnects. Logic blocks can be programmed to perform the function of basic
logic gates such as AND, and XOR, or more complex combinational functions
such as decoders or mathematical functions. In most FPGAs, the logic blocks
also include memory elements, which may be simple flip-flops or more complete
blocks of memory. A hierarchy of programmable interconnects allows logic
blocks to be interconnected as needed by the system designer, somewhat like a
one-chip programmable breadboard.
Logic blocks and interconnects can be programmed by the customer or designer,
after the FPGA is manufactured, to implement any logical function—hence the
name "field-programmable". FPGAs are usually slower than their application-
specific integrated circuit (ASIC) counterparts, cannot handle as complex a
design, and draw more power (for any given semiconductor process). But their
advantages include a shorter time to market, ability to re-program in the field to fix
bugs, and lower non-recurring engineering costs. Vendors can sell cheaper, less
flexible versions of their FPGAs which cannot be modified after the design is
committed. The designs are developed on regular FPGAs and then migrated into a
fixed version that more resembles an ASIC.
2. Question 2. What Logic Is Inferred When There Are Multiple Assign
Statements Targeting The Same Wire?
Answer :
It is illegal to specify multiple assign statements to the same wire in a
synthesizable code that will become an output port of the module. The synthesis
tools give a syntax error that a net is being driven by more than one source.
However, it is legal to drive a three-state wire by multiple assign statements. 

Basic Simulation Interview Questions

3. Question 3. What Is Minimum And Maximum Frequency Of Dcm In Spartan-
3 Series Fpga?
Answer :
Spartan series dcm’s have a minimum frequency of 24 MHZ and a maximum of
248 
4. Question 4. Suppose For A Piece Of Code Equivalent Gate Count Is 600 And
For Another Code Equivalent Gate Count Is 50,000 Will The Size Of Bitmap
Change?in Other Words Will Size Of Bitmap Change It Gate Count Change?
Answer :
The size of bitmap is irrespective of resource utilization, it is always the same,for
Spartan xc3s5000 it is 1.56MB and will never change.
5. Question 5. What Are Different Types Of Fpga Programming Modes?what
Are You Currently Using ?how To Change From One To Another?
Answer :
Before powering on the FPGA, configuration data is stored externally in a PROM or
some other nonvolatile medium either on or off the board. After applying power,
the configuration data is written to the FPGA using any of five different modes:
Master Parallel, Slave Parallel, Master Serial, Slave Serial, and Boundary Scan
(JTAG). The Master and Slave Parallel modes 
Mode selecting pins can be set to select the mode, refer data sheet for further
details. 

Verilog Interview Questions

6. Question 6. Can You List Out Some Of Synthesizable And Non
Synthesizable Constructs?
Answer :
not synthesizable
o initial 
o ignored for synthesis.
o delays 
o ignored for synthesis.
o events 
o not supported.
o real 
o Real data type not supported.
o time 
o Time data type not supported.
o force and release 
o Force and release of data types not supported.
o fork join 
o Use nonblocking assignments to get same effect.
o user defined primitives 
o Only gate level primitives are supported.
synthesizable constructs
o assign,for loop,Gate Level Primitives,repeat with constant value...
7. Question 7. Can You Explain What Struck At Zero Means?
Answer :
These stuck-at problems will appear in ASIC. Some times, the nodes will
permanently tie to 1 or 0 because of some fault. To avoid that, we need to provide
testability in RTL. If it is permanently 1 it is called stuck-at-1 If it is permanently 0 it
is called stuck-at-0. 

Wireless Interview Questions

8. Question 8. Difference Between Fpga And Cpld?
Answer :
FPGA:
o SRAM based technology.
o Segmented connection between elements.
o Usually used for complex logic circuits.
o Must be reprogrammed once the power is off.
o Costly
CPLD:
o Flash or EPROM based technology.
o Continuous connection between elements.
o Usually used for simpler or moderately complex logic circuits.
o Need not be reprogrammed once the power is off.
o Cheaper 
9. Question 9. What Are Dcm's?why They Are Used?
Answer :
Digital clock manager (DCM) is a fully digital control system that uses feedback to
maintain clock signal characteristics with ahigh degree of precision despite
normal variations in operating temperature and voltage. 
That is clock output of DCM is stable over wide range of temperature and voltage ,
and also skew associated with DCM is minimal and all phases of input clock can
be obtained . The output of DCM coming form global buffer can handle more load.

Aerospace Interview Questions

10. Question 10. Can A Clb Configured As Ram?
Answer :
YES. The memory assignment is a clocked behavioral assignment, Reads from
the memory are asynchronous, And all the address lines are shared by the read
and write statements.
11. Question 11. What Is Purpose Of A Constraint File What Is Its Extension?
Answer :
The UCF file is an ASCII file specifying constraints on the logical design. You
create this file and enter your constraints in the file with a text editor. You can also
use the Xilinx Constraints Editor to create constraints within a UCF(extention) file.
These constraints affect how the logical design is implemented in the target
device. You can use the file to override constraints specified during design entry. 

System Verilog Interview Questions

12. Question 12. How Many Global Buffers Are There In Your Current
Fpga,what Is Their Significance?
Answer :
There are 8 of them in xc3s5000 
 An external clock source enters the FPGA using a Global Clock Input Buffer
(IBUFG), which directly accesses the global clock network or an Input Buffer
(IBUF). Clock signals within the FPGA drive a global clock net using a Global Clock
Multiplexer Buffer (BUFGMUX). The global clock net connects directly to the
CLKIN input. 

Basic Simulation Interview Questions

13. Question 13. Why Is Map-timing Option Used?
Answer :
Timing-driven packing and placement is recommended to improve design
performance, timing, and packing for highly utilized designs.
14. Question 14. What Are Different Types Of Timing Verifications?
Answer :
Dynamic timing:
o The design is simulated in full timing mode.
o Not all possibilities tested as it is dependent on the input test vectors.
o Simulations in full timing mode are slow and require a lot of memory.
o Best method to check asynchronous interfaces or interfaces between
different timing domains.
Static timing:
o The delays over all paths are added up.
o All possibilities, including false paths, verified without the need for
test vectors.
o Much faster than simulations, hours as opposed to days.
o Not good with asynchronous interfaces or interfaces between
different timing domains.
15. Question 15. Compare Pll & Dll ?
Answer :
PLL:
PLLs have disadvantages that make their use in high-speed designs problematic,
particularly when both high performance and high reliability are required. 
The PLL voltage-controlled oscillator (VCO) is the greatest source of problems.
Variations in temperature, supply voltage, and manufacturing process affect the
stability and operating performance of PLLs.
DLLs, however, are immune to these problems. A DLL in its simplest form inserts
a variable delay line between the external clock and the internal clock. The clock
tree distributes the clock to all registers and then back to the feedback pin of the
DLL.
The control circuit of the DLL adjusts the delays so that the rising edges of the
feedback clock align with the input clock. Once the edges of the clocks are
aligned, the DLL is locked, and both the input buffer delay and the clock skew are
reduced to zero.
 Advantages:
o precision
o stability
o power management
o noise sensitivity
o jitter performance.
VHDL Interview Questions
16. Question 16. Given Two Asics. One Has Setup Violation And The Other Has
Hold Violation. How Can They Be Made To Work Together Without Modifying
The Design?
Answer :
Slow the clock down on the one with setup violations. And add redundant logic in
the path where you have hold violations.
17. Question 17. Suggest Some Ways To Increase Clock Frequency?
Answer :
o Check critical path and optimize it.
o Add more timing constraints (over constrain).
o pipeline the architecture to the max possible extent keeping in mind
latency req's. 
XLink Interview Questions
18. Question 18. What Is The Purpose Of Drc?
Answer :
DRC is used to check whether the particular schematic and corresponding
layout(especially the mask sets involved) cater to a pre-defined rule set depending
on the technology used to design. They are parameters set aside by the
concerned semiconductor manufacturer with respect to how the masks should be
placed , connected , routed keeping in mind that variations in the fab process
does not effect normal functionality. It usually denotes the minimum allowable
configuration. 

Verilog Interview Questions

19. Question 19. What Is Lvs And Why Do We Do That. What Is The Difference
Between Lvs And Drc?
Answer :
The layout must be drawn according to certain strict design rules. DRC helps in
layout of the designs by checking if the layout is abide by those rules.
After the layout is complete we extract the netlist. LVS compares the netlist
extracted from the layout with the schematic to ensure that the layout is an
identical match to the cell schematic. 
20. Question 20. What Is Dft ?
 Answer :
DFT means design for testability. 'Design for Test or Testability' - a methodology
that ensures a design works properly after manufacturing, which later facilitates
the failure analysis and false product/piece detection
Other than the functional logic,you need to add some DFT logic in your
design.This will help you in testing the chip for manufacturing defects after it
come from fab. Scan,MBIST,LBIST,IDDQ testing etc are all part of this. (this is a
hot field and with lots of opportunities)

ASIC Interview Questions

21. Question 21. There Are Two Major Fpga Companies: Xilinx And Altera.
Xilinx Tends To Promote Its Hard Processor Cores And Altera Tends To Promote
Its Soft Processor Cores. What Is The Difference Between A Hard Processor
Core And A Soft Processor Core?
Answer :
A hard processor core is a pre-designed block that is embedded onto the device.
In the Xilinx Virtex II-Pro, some of the logic blocks have been removed, and the
space that was used for these logic blocks is used to implement a processor. The
Altera Nios, on the other hand, is a design that can be compiled to the normal
FPGA logic.
22. Question 22. When Are Dft And Formal Verification Used?
Answer :
DFT:
o manufacturing defects like stuck at "0" or "1".
o test for set of rules followed during the initial design stage.
Formal verification:
o Verification of the operation of the design, i.e, to see if the design
follows spec.
o gate netlist == RTL ?
o using mathematics and statistical analysis to check for equivalence.
23. Question 23. What Is Synthesis?
Answer :
Synthesis is the stage in the design flow which is concerned with translating your
Verilog code into gates - and that's putting it very simply! First of all, the Verilog
must be written in a particular way for the synthesis tool that you are using. Of
course, a synthesis tool doesn't actually produce gates - it will output a netlist of
the design that you have synthesised that represents the chip which can be
fabricated through an ASIC or FPGA vendor. 
24. Question 24. We Need To Sample An Input Or Output Something At
Different Rates, But I Need To Vary The Rate? What's A Clean Way To Do This?
Answer :
Many, many problems have this sort of variable rate requirement, yet we are
usually constrained with a constant clock frequency. One trick is to implement a
digital NCO (Numerically Controlled Oscillator). An NCO is actually very simple
and, while it is most naturally understood as hardware, it also can be constructed
in software. The NCO, quite simply, is an accumulator where you keep adding a
fixed value on every clock (e.g. at a constant clock frequency). When the NCO
"wraps", you sample your input or do your action.
By adjusting the value added to the accumulator each clock, you finely tune the
AVERAGE frequency of that wrap event. Now - you may have realized that the
wrapping event may have lots of jitter on it. True, but you may use the wrap to
increment yet another counter where each additional Divide-by-2 bit reduces this
jitter. The DDS is a related technique. I have two examples showing both an NCOs
and a DDS in my File Archive. This is tricky to grasp at first, but tremendously
powerful once you have it in your bag of tricks. NCOs also relate to digital PLLs,
Timing Recovery, TDMA and other "variable rate" phenomena